Self-aligned Structure Research Articles

Double-polysilicon self-aligned lateral bipolar transistors

A new lateral bipolar junction transistor that utilises a double-polysilicon self-aligned structure to maximise high-frequency performance is introduced. Silicon-on-oxide (SOI) wafers are used to isolate devices from the substrate and to minimise parasitic substrate capacitances (CJCS0) around 1.3–2.6 fF (substrate is ground). A SOI thickness of 0.2–0.5 μm combined with 0.13–0.25 μm lithography could allow a reduction of transistor dimensions down to (0.2–0.5) × (0.13–0.25) μm2 and give an estimated minimum emitter/base junction capacitance (CJE0) of 0.54–1.36 fF. Simple device isolation is predicted to produce a small collector/base junction capacitance (CJC0) of 0.42–2.00 fF. Furthermore, use of a double base contact can help reduce base resistance (RB) to 0.43–1.17 kΩ and a wide collector window directly contacted to the collector is estimated to result in around 0.66–1.58 kΩ collector resistance (RC). By taking all parameters into account a cut-off frequency (f T ) of 69–116 GHz and maximum oscillation frequency (fmax) of 61–128 GHz is predicted for this design, in addition a gain of 47–101 (using minimum gain enhancement) and roughly 10.6–21.0 ps ECL propagation delay time, at a current of 0.4–1.0 mA could be achieved. Our simulations indicate that this new doubled-polysilicon self-aligned structure could outperform all other silicon bipolar transistors that have been reported.

Novel Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors with Self-Aligned Structure

We proposed a new self-aligned gate-all-around metal–oxide–semiconductor field effect transistor (MOSFET) with a wide source/drain region. The device was fabricated by using the concept of the self-aligned double-gate fin-type FETs (FinFETs) with additional processes. The minimum gate length and fin width were 35 and 20 nm, respectively. The gate oxide thickness was 2.4 nm. For the fabricated devices, we confirmed that drain induce barrier lowering (DIBL) and sub-threshold swing (SS) were properly suppressed in spite of the short channel length. We also performed a simulation-based analysis to explore the effects induced by oversized bottom gate in the proposed device structure. If the lateral source/drain doping gradient was not steep, the oversized bottom gate could lead to the enhancement of the gate controllability and the suppression of short channel effects. As a result, the intrinsic gate delay of the proposed devices was improved when the bottom gate was somewhat oversized.

Low Damage Etching of GaN Surfaces via Bias-Assisted Photoenhanced Electrochemical Oxidation in Deionized Water

Properties of GaN surfaces etched by bias-assisted photoenhanced electrochemical (PEC) oxidation in deionized water and subsequent removal of the oxidized material are investigated using Schottky diodes fabricated on etched surfaces. It is demonstrated that with a short anneal at 700°C after removal of the oxide, it is possible to obtain a low damage surface with near ideal breakdown and capacitance-voltage (C-V) characteristics. Good quality Schottky diodes are fabricated on surfaces etched as much as 120 nm. The undercutting of masked surfaces is also demonstrated. Thus, given the band-gap selectivity, the possibility to undercut masked areas, and the low damage surfaces that can be obtained, the process demonstrated in this paper is suitable for use in fabrication of self-aligned GaN bipolar transistor structures.

50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and standard T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system

A Novel Self-Aligned Etch-Stopper Structure With Lower Photo Leakage for AMLCD and Sensor Applications

In this letter, the authors introduce a novel self-aligned etch-stopper sidewall-contact hydrogenated amorphous silicon (a-Si : H) thin-film transistor (ESSC-TFT), which reduces the photo leakage current by more than one order of magnitude and increases the on-off ratio to seven orders of magnitude under back light illumination. Such a TFT will enable high-resolution and high-brightness liquid-crystal displays (LCDs) for next-generation TV, monitor, notebook, and mobile-phone applications. This ESSC-TFT design reduces the volume of a-Si film in which the active region can totally be shielded by the gate metal resulting in the prevention from direct back light illumination. With the sidewall contact, the hole current is reduced due to the smaller contact area between drain/source and a-Si layer. As well as the source, drain parasitic intrinsic resistance of a-Si can be also lessened by the ESSC-TFT structure. Although the defects between etched a-Si and n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+ </sup> a-Si film may degrade the on current, the ESSC-TFT still exhibits higher on-off ratio and lower leakage than the one in traditional etch-stopper (ES)-TFT structure. The ESSC-TFT structure can be used not only for TFT-LCD application but also for the applications that demand high on-off ratio and low-leakage device, such as X-ray image sensor

Prospects for Complementary SiGeC BiCMOS on Thin-Film SOI

This paper reviews the concept, manufacturing process and electrical characteristics of a novel self-aligned SiGeC HBT structure suitable for thin-film SOI substrates. It then describes the integration of this device into 130nm SOI CMOS technology, and presents early results on the development of a complementary pnp HBT.

Self-aligned multi-level air gap integration

Dual damascene self-aligned air gap structures have been fabricated through selective removal of interline plasma-damaged SiOC material using dilute HF solutions after metal CMP. The extent of the gaps was shown to be tuneable. The creation of interline air gaps through removal of damaged dielectric yielded significant capacitance reduction plus in addition dielectric reliability improvement. The via-reliability of 2 metal-build air gap structures was tested by thermal cycling and constant thermal stress. No significant difference in via reliability was observed between SiOC interconnects with and without air gaps. However, failure analysis showed weak spots near the bottom of the barrier, which could be detrimental for dual damascene reliability. These weak spots at the barrier bottom could lead to catastrophic failures in both via and lines during electromigration stressing. Moreover, process-related issues such as bottom liner undercut and copper corrosion need to be controlled more stringent before this air gap approach can be successfully implemented.

스크린 프린팅 방법에 의해 게이트-에미터간 자체정렬된 3극 구조의 CNT FEA 제조

A carbon nanotube field emission display(CNT FED) panel with a 2 inch diagonal size was fabricated using a screen printing of a prepared photo-sensitive CNT paste and vacuum in-line sealing technology. After a surface treatment of the patterned CNT, only the carbon nanotube tips are uniformly exposed on the surface. The diameter of the exposed CNTs are usually about 20 nm. Using the photo-sensitive CNT paste, we have developed a triode type CNT FEA with a self-aligned gate-emitter structure. The turn on voltage was around 100 V which corresponds to according the turn on field of about <TEX>$40V/{\mu}m$</TEX>. By the creation of a self-aligned gate-emitter structure, it is expected that the screen printed photo-sensitive CNT paste is promising as a good candidate for the large size field emission display.

Characterization of optical accelerometers based on UV-sensitive polymers

The design, simulation, fabrication, and characterization of quad-beam polymer optical accelerometers is presented in this paper. An applied acceleration causes a misalignment between the waveguides that comprise the structure. Two different geometries with different beam widths have been tested. Both of them show high mechanical and optical sensitivity and negligible cross sensitivities. Self-alignment structures for fast and accurate fiber-optic positioning have also been implemented in the device. Stable, simple, and robust technology that only requires two technological steps is also presented. Static characterization shows experimental optical sensitivities of at least 15.8 and 6.2 dB/g for each optical accelerometer.

Self-aligned Thin Film Transistor Fabrication with an Ultra Low Temperature Polycrystalline Silicon Process on a Benzocyclobutene Planarized Stainless Steel Foil Substrate

AbstractCompared to plastic, from the view point of ultra low temperature poly-Si (ULTPS) processes for realizing flexible active matrix organic light emitting diode (AM-OLED) display, SSF offers high thermal resistance and chemical stability, and lithography stability. As SSF is stiffer than plastic film, SSF is expected to reduce stress which originates from difference in coefficient of thermal expansion. However, SSF substrate itself also bears surface roughness problem, which necessitates an appropriate planarization step. Also to fully integrate both the drive circuits and the pixel thin-film transistor(TFT)s in a monolithic complementary metal-oxide-semiconductor (CMOS) technology high mobility is required, calling for poly-Si usage.We will deal with the planarization process, and then address various processing issues. Especially, we will demonstrate our successful SLS of Si on SSF substrates. Finally we show the device performances. All fabrication temperatures were kept below 200 oC to meet a ULTPS process.Due to the rolling process for manufacturing foils, the SSF surface is rough. We have measured average roughness of 500 nm, respectively. With benzocyclobutene (BCB), we have successfully planarized the surface with average roughness was less than 0.5 nm.Our TFT's active layer was obtained by laser crystallizing amorphous Si (a-Si) films. To obtain a high quality gate dielectric film, we formed a SiO2 film using an O2 plasma treatment on the surface of the poly-Si film and then deposited Al2O3 film by plasma enhanced atomic layer deposition. Then gate metal was deposited and patterned. Source and drain regions were p+ doped by ion implantation to form a self-aligned gate structure. We have used SiNx film as interlayer dielectrics.Briefly we discuss a practical approach for realizing SLS on a SiO2 buffer. The Si-on-SiO2 layer stacking is energetically unstable. Should have not controlled the heat during laser crystallization, liquid Si would recede to expose the SiO2 layer. Dewetting is suppressed by adjusting the buffer density, and densifying the a-Si film. To implement the SLS, we have optimally conjugated the densities of the buffer film and the a-Si film to produce Si grains with sizes of ~6 ¥ìm on a BCB planarized SSF.Our p-channel TFT transfer performance exhibits a field effect mobility (¥ì) of 95 cm2/Vs, a threshold voltage (Vt) of -3 V and a sub-threshold swing(S-S) of 0.5 V/dec.. The off-current level is ~ 10 pA at drain voltage (Vd) of -1V and the Ion/Ioff is 106 . Especially our stable Vt consents to the electrical stability for driving displays. This feature might be attributed to the improved interface between the active layer and the gate dielectrics by plasma oxidation.

P-1: A Novel Self-Aligned Etch Stopper Structure with Lower Photo Leakage for AMLCD Applications

We introduce a novel self-aligned etch stopper, sidewall-contact a-Si:H TFT (ESSC-TFT) which allow us to reduce the photo leakage current by the island-in structure. This ESSC-TFT design reduces the volume of a-Si film, the active region can totally be shielded by the gate metal resulting in the prevention from direct back light illumination. With the sidewall-contact, the hole current is reduced due to the smaller contact area, and we expect the source, drain parasitic intrinsic resistance of a-Si can be also lessened by the ESSC-TFT structure. Although the defects between etched a-Si and n+ a-Si film may degrade the on current, the ESSC-TFT still exhibits higher on-off ratio than the one in traditional ES-TFT structure.

P-3: Organic Thin-Film Transistors with Solution-Processed Pentacene and Polysilazane Using Self-Aligned Device Structure

We have fabricated organic thin-film transistors that had a high field-effect mobility of 0.39 cm2/Vs, in which both the semiconductor and the gate-dielectric were solution-processed using pentacene and polysilazane. These materials were also applied to a self-aligned structure for the first time and exhibited good device performance with solution-processed electrodes.

Polymer microlenses with modified micromolding in capillaries (MIMIC) technology

A modification of the micromolding in capillaries (MIMIC) technology that allows the definition of three-dimensional (3-D) polymer microlenses is presented in this letter. In order to obtain high-quality meniscuses molds from which microlenses can be formed, microchannels defined by surfaces with identical contact angles are required. We have achieved this by using a modified SU-8 (XP SU-8 NO-2). This photoresist retains the structurability of the SU-8 (being then possible to define self-alignment structures for adequate fiber optics positioning) while having a lower refractive index than standard SU-8 (achieving light confinement by total internal reflection). Experimental measurements of the fabricated ellipsoidal microlenses have shown the two Sturm focals and the circle of least confusion. These results validate the presented modification of the MIMIC technology, with which polymer waveguides ending with 3-D microlenses and integrated self alignment structures for adequate fiber optics positioning have been defined.

Native oxide buried InAlAs ridge waveguide laser diode

InAlAs wet thermal oxidation process was adopted to fabricate ridge waveguide laser diodes. First, applying the oxidation process on the whole etched surface of an InAlAs upper cladding layer, we formed a current blocking and optical confining layer of ridge waveguide laser diode. This is a self-aligned structure, which makes the laser diode fabrication steps much simpler and etching-depth control less important. Assessment of the fabricated laser diode revealed that current-voltage characteristics and slope efficiency did not worsen, and threshold current was reduced by the oxidation process.

A New Scalable Self-Aligned Dual-Bit Split-Gate Charge-Trapping Memory Device

Devices based on charge trapping are a promising solution for Flash memory scaling. The nonconductivity of their storage medium makes them more robust with respect to data loss by charge leakage through the bottom oxide, which, on the contrary sets a hard limit to floating-gate Flash scalability. Their simple processing, highly compatible with CMOS, makes them rapidly integrable into short-term solutions. The well-known SONOS concept however, still suffers from insufficient data throughput and retention. On the other hand, the recently proposed NROM concept, storing two bits in a cell, offers very interesting characteristics by using hot carrier based program/erase operations. However, important drawbacks remain, like insufficient isolation of the bits for scalability, high-power programming, and degradation of the retention after cycling. In this paper, we present a dual-bit trapping device which solves most of these problems by using a split-gate structure which was inspired by the HIMOS concept. The device has a fully self-aligned structure which allows for both bits to be physically isolated in the cell. Those features make it very scalable. Programming can be performed by the very efficient source-side injection mechanism, while erase is done by injection of band-to-band tunneling induced hot holes, which compensate for the trapped electrons. This leads to performances comparable to NROM but with lower power consumption, and lower operating voltages.

Brightness enhancement of ITO/GaN LEDs by self‐aligned micro‐net structures

Arrays of square and hexagonal holes of various dimensions were patterned on indium-tin-oxide (ITO)/GaN light-emitting diodes (LEDs) using the self-aligned method to increase the light extraction area and shorten the optical paths. The hole region was etched to give the sidewall of the active layer a sloped profile, and it was passivated by SiOxNy films to extract more light. The self-aligned micro-net LED is at least 10% brighter than the conventional structure in the normal direction without loss of operating voltage or leakage current. The ratio of luminescence to total output power is increased by 25% at a current density of 100 A/cm2. Moreover, varying the hole dimensions and the designed density increased the peak external quantum efficiency by 5% at a current of 3 mA. The greater axial luminescence and the higher external quantum efficiency make LEDs self-aligned micro-net structures quite useful in surface-mounting and low-power-consuming devices, such as cellular phones. (© 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

100-nm n-/p-channel I-MOS using a novel self-aligned structure

We have fabricated a 100-nm n-/p-channel I-MOS by adopting a novel structure. The proposed structure shows some advantages over the conventional one in terms of self-alignment and reduced number of photolithography masks. It leads to low fabrication cost, accelerated scaling down, and enhanced performance due to reduced parasitic elements. It shows a normal transistor operation with small subthreshold swing less than 11.8 mV/dec at room temperature. The n- and p-channel I-MOS have an ON/OFF current of 81.1/2.8 and 78.2/3.4 μA per μm, respectively. The device performance provides a promise for near-ideal switch application.

A novel SOI lateral-power MOSFET with a self-aligned drift region

In this letter, a novel drift-region self-aligned SOI lateral-power MOSFET using a partial exposure technique is proposed and demonstrated for RF power amplifier applications. The drift self-aligned structure was achieved using a simple process and without the need of an additional mask. Furthermore, the drift length can be controlled conveniently using different layout designs. The fabricated SOI power device has a breakdown voltage of over 20 V. Using a 0.7-/spl mu/m nonsilicide technology, the cutoff frequency (f/sub t/) and maximum oscillation frequency (f/sub max/) of the device are 10.1 and 13.7 GHz, respectively.

Self-aligned carbon nanotube transistors with charge transfer doping

This letter reports a charge transfer p-doping scheme which utilizes one-electron oxidizing molecules to obtain stable, unipolar carbon nanotube transistors with a self-aligned gate structure. This doping scheme allows one to improve carrier injection, tune the threshold voltage Vth, and enhance the device performance in both the “ON-” and “OFF-” transistor states. Specifically, the nanotube transistor is converted from ambipolar to unipolar, the device drive current is increased by 2–3 orders of magnitude, the device OFF current is suppressed and an excellent Ion∕Ioff ratio of 106 is obtained. The important role played by metal–nanotube contacts modification through charge transfer is demonstrated.

Imprint lithography issues in the fabrication of high electron mobility transistors

In earlier work we described procedures for the fabrication of High Electron Mobility Transistors (HEMTs) using nanoimprint lithography to produce T-shaped resist profiles for gate metallization. For reliable liftoff the T-gate process requires a clear undercut in resist, and this is intrinsically impossible with imprint lithography. In addition, the imprinting process resulted in fracture defects in the resist unless release was carried out at elevated temperatures. Both these problems required improvement. In this article we describe an improved method for obtaining metallized imprinted T-gates by creating resist undercut using a double angled evaporation. HEMTs with self-aligned gate structures were fabricated using this procedure. Multilayer resist stacks were used to investigate resist flow during imprinting and we show that such stacks are not suitable for liftoff enhancement of T-gates. We further show how resist fracture defects can be minimized by increasing the pattern density on the die.