Self-aligned Structure Research Articles

Design and analysis of a new self-aligned asymmetric structure for deep sub-micrometer MOSFET

A new self-aligned asymmetric structure (SAAS) is proposed for deep sub-micrometer MOSFET and its device characteristics are analyzed. The proposed structure enables the source, drain and channel to be designed independently without additional lithography steps. SAAS with lateral asymmetric channel and highly doped source extension improves driving capability and short channel behavior without sacrificing hot carrier reliability. Based on the results of hydrodynamic device simulation over a wide range of process conditions, it is shown that highly doped asymmetric halo provides enhanced velocity overshoot and suppressed drain-induced barrier lowering. By employing asymmetric highly doped source extension, the degradation of driving capability is suppressed that can be caused by the increased parasitic resistance in highly doped asymmetric halo.

A high-efficiency thin-film SOI power MOSFET having a self-aligned offset gate structure for multi-gigahertz applications

A highly efficient radio-frequency (RF) thin-film SOI power MOSFET having a self-aligned offset gate structure has been fabricated, It was fabricated using a self-aligned offset gate structure based on a lightly doped drain (LDD) structure to reduce the on-resistance and thus increase the power-added efficiency. The target breakdown voltage was 10 V, and the fabricated device had a breakdown voltage of 14.3 V. The on-resistance of a thin-film SOI power MOSFET using titanium salicide process was lower than that of the one fabricated using a tungsten polycide process. The cutoff frequency and maximum oscillation frequency of the titanium salicide process were 17 and 24 GHz, respectively. Its power-added efficiency at 2 GHz was 67% and its saturation output power was 20 dBm when the drain supply voltage was 3.0 V. Its power-added efficiency at 5.8 GHz was 53% and its saturation output power was 19 dBm when the drain supply voltage was 3.0 V. The dc and RF performances of the power MOSFET fabricated using the titanium salicide process were better than those of the one fabricated using the tungsten polycide process.

Monolithically integrated 780-nm-band high-power and 650-nm-band laser diodes with real refractive index guided self-aligned structure

780-nm-band high-power and 650-nm-band laser diodes (LDs) with real refractive index guided self-aligned (RISA) structures are monolithically integrated for the first time. High-power and fundamental transverse mode operation at an output power of 100-mW continuous wave (CW) up to 80/spl deg/C is attained for the 780-nm-band LD. For the 650-nm-band LD, high temperature and fundamental transverse mode operation at an output power of 10-mW CW up to 80/spl deg/C is obtained.

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I/sub dsat/ of 820 /spl mu/A//spl mu/m at V/sub ds/=V/sub gs/=1.2 V and T/sub ox/=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm.

SELF-ALIGNED Si BJT/SiGe HBT TECHNOLOGY AND ITS APPLICATION TO HIGH-SPEED CIRCUITS

In a Si bipolar transistor (BJT) and a SiGe heterojunction bipolar transistor (HBT), self-aligned structures help to improve high-speed and high-frequency characteristics. These structures are used to reduce parasitic capacitance and resistance, and thus maximize the transistor's intrinsic performance. In addition to generally used process technology, selective metal deposition to form electrodes and selective epitaxial growth of Si/SiGe multilayers are applied in the fabrication process. To improve the intrinsic speed, the cutoff frequency, a shallow diffusion process for Si BJTs and a graded-Ge profile SiGe-base layer for SiGe HBTs are used. These also enable a high maximum oscillation frequency and a small gate delay in the emitter-coupled logic through the synergistic effect of the self-aligned structure. Both high-speed digital circuits — frequency dividers up to millimeter-wave bands and a multiplexer/demultiplexer for optical-fiber-links — and high-frequency analog circuits for optical-fiber-links — a preamplifier, an automatic gain control amplifier. a limiting amplifier, and a decision circuit — have been implemented by applying the self-aligned Si BJTs and/or SiGe HBTs.

A new laser-processed polysilicon TFT architecture

A new top gate polysilicon thin-film transistor (TFT) architecture is introduced which requires only a single laser process step to simultaneously crystallize the channel and activate the source-drain. The dummy-gate TFT (DGTFT) uses a light blocking layer patterned with the gate mask combined with two backside expose steps to allow a self-aligned device structure. N-channel TFTs fabricated using the new process have field effect mobilities greater than 100 cm/sup 2//Vs. By controlling the backside exposures it is also possible to form offset or graded doping structures to reduce field enhanced leakage currents.

Characterization of Low Temperature Polysilicon TFTs with Self-Aligned Graded LDD Structure

AbstractA simple process sequence for fabrication of low temperature polysilicon (LTPS) TFTs with self-aligned graded LDD structure was demonstrated. The graded LDD structure was self-aligned by side-etch of Al under the photo-resist followed by excimer laser irradiation for dopant activation and laterally diffusion. The graded LDD polysilicon TFTs were suitable for high-speed operation and active matrix switches applications because they possessed low-leakage-current characteristic without sacrificing driving capability significantly and increasing overlap capacitance. The leakage current of graded LDD polysilicon TFTs at Vd = 5V and Vg = −10V could attain to below 1pA/μm without any hygrogenation process, when proper LDD length and laser activation process were applied. The on/off current ratios of these devices were also above 108. Furthermore, due to graded dopant distribution in LDD regions, the drain electric field could be reduced further, and as a result, graded LDD polysilicon TFTs provided high reliability for high voltage operation.

Electrical detection and simulation of stress in silicon nitride spacer technology

The stress in deposited silicon dioxide and silicon nitride layers that are used in the fabrication of self-aligned bipolar transistor structures, is evaluated. The intrinsic and thermal stress of the layers is measured and these values are used in a finite element process simulator to calculate the pressure in the silicon around the emitter window during processing. Bipolar transistors are fabricated with different combinations of silicon oxide and silicon nitride and the yield of large transistor arrays is compared with the calculated pressure for the different combinations. The presence of a tensile pressure near the emitter coincides with a low measured device yield.

Si1−xGex selective epitaxial growth for ultra-high-speed self-aligned HBTs

Si1−xGex low temperature selective epitaxial growth was investigated by using a UHV/CVD system with high pressure H2 pre-cleaning of the substrate and SiGe HBTs were fabricated. The selective epitaxial growth was achieved by using different incubation times for Si(100) substrate and mask layers. Device performances show the good crystallinity of selectively grown Si1−xGex layer: an extremely high current gain of 45 000 and a high cutoff frequency of 154 GHz were achieved in the HBT with a maximum Ge content of 25%. Furthermore, the comparison of AC performance between self-aligned and non-self-aligned transistors demonstrates the advantage of the self-aligned structure formed by the Si1−xGex low-temperature selective epitaxial growth.

Optical and structural characterization of a self-aligned single electron transitor structure by cathodoluminescence microscopy

We report about optical and structural investigations of a self-aligned single electron transistor (SET) structure using cathodoluminescence-(CL) and transmission electron microscopy (TEM). The SET structures were fabricated by MBE growth of GaAs/AlAs on different prepatterned GaAs (100) substrates. This technique for the in situ formation of nanoscopic semiconductor heterostructures is presently a widely used and promising approach for the fabrication of low-dimensional systems like quantum wires and quantum dots (QD). The active region of the SET structure consists of a GaAs/AlGaAs-QD formed by thickness modulation of a single quantum well (SQW) during the MBE growth. The position and the size of the QD is defined by the design of the substrate pattern. The thickness modulation of the GaAs-SQW is evidenced by TEM investigations. The lateral confinement potential given by the thickness modulation of GaAs-SQW is directly imaged by CL microscopy.

An amorphous silicon thin-film transistor with fully self-aligned top gate structure

We have developed a novel fully self-aligned top gate amorphous silicon thin-film transistor, which shows excellent transistor characteristics. Self-alignment is achieved by patterning the gate electrode and then etching the silicon nitride gate insulator, followed by silicidation and ion implantation of the exposed a-Si in the contact regions. We obtain a long channel saturated mobility of 0.9 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V/sup -1/ s/sup -1/, while for channel lengths of 6 μm, we obtain an effective mobility of 0.6 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V/sup -1/ s/sup -1/, in the saturated region and 0.5 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V/sup -1/ s/sup -1/, in the linear region. This high level of performance, together with the negligible parasitic capacitance of the self-aligned structure, makes this transistor suitable for new demanding applications in active matrix liquid crystal displays and large area X-ray image sensors.

Elevated source drain devices using silicon selective epitaxial growth

Elevated source drain (ESD) structure in deep submicron metal oxide semiconductor field effect transistors (MOSFETs) can help reduce parasitic series resistance and simultaneously achieve shallow contacting junctions to minimize short channel effects. A self-aligned ESD structure in conventional complimentary metal–oxide–semiconductor processing can be achieved using silicon selective epitaxial growth (SEG). A robust low thermal budget high quality SEG process using a commercial rapid thermal chemical vapor deposition reactor for ESD formation has been demonstrated. The preclean sequence prior to SEG is the key to achieve facet-free epitaxy. Low line-to-line leakage confirms the high selectivity to nitride and oxide. The growth on exposed polysilicon (poly) gates leads to gate linewidth widening and lower gate sheet resistance. ESD parametric data suggest that the well doping needs to be optimized to counter the slight increase in n+-p diode leakage. Capacitance–voltage simulations indicate that the gate to drain capacitance initially decreases and then increases with SEG thickness.

Self-aligned current confinement structure using AlAs/InP tunnel junction in GaInAsP/InP semiconductor lasers

We propose a current confinement structure which can be self-formed by thermal annealing of a electrode metal with a self-aligning process. The migrated metal selectively destroys an AlAs/InP tunnel junction to form a high resistance isolation layer. The hole current can be injected through a preserved tunnel junction window. We confirmed its lateral confinement effect from the near-field pattern of fabricated GaInAsP/InP stripe lasers. The proposed current confinement structure is very simple and useful for the lateral injection in semiconductor optical devices including long-wavelength vertical-cavity surface-emitting lasers.

A self-aligned offset polysilicon thin-film transistor using photoresist reflow

A simple fabrication method for a self-aligned offset structure, which uses photoresist reflow, is developed to reduce the leakage current of polysilicon thin-film transistors (poly-Si TFTs). The reflow of photoresist can be controlled by varying photoresist thickness and reflow temperature. It is found that the reflow length increases in proportion to the photoresist thickness, and increases with increasing reflow temperature at less than 200/spl deg/C for the AZ5214A photoresist. Poly-Si TFTs are successfully demonstrated with offset lengths of 0.4 and 0.6 /spl mu/m, which show apparent reduction of the leakage current.

A new self-aligned offset staggered polysilicon thin-film transistor

A new self-aligned offset staggered polysilicon thin-film transistor (poly-Si TFT) has been proposed and demonstrated to have a suppressed leakage current. For the self-aligned offset structure, planarization with thick photoresist and etchback of photoresist are successfully utilized. The offset length can be easily controlled by the thickness of the gate material without photolithographic limitation. In the self-aligned offset polysilicon TFT's, the leakage current decreases with an increasing offset length.

A selective-epitaxial-growth SiGe-base HBT with SMI electrodes featuring 9.3-ps ECL-gate delay

An ultra-high-speed selective-epitaxial-growth SiGe-base heterojunction bipolar transistor (HBT) with self-aligned stacked metal/in-situ doped poly-Si (IDP) (referred to as SMI) electrodes is developed. A 0.5-/spl mu/m-wide SiGe base self-aligned to the 0.1-/spl mu/m-wide emitter was selectively grown by using a UHV/CVD system. This self-aligned structure effectively reduces collector capacitance. In SMI technology, a tungsten film is selectively stacked on all poly-Si electrodes (base, emitter, and collector) in a self-aligned manner by using selective deposition without any heat treatment. So this technology does not cause unwanted diffusion of the base dopants and keeps a shallow intrinsic base profile. SMI technology can therefore provide low parasitic resistances and is well-suited to an SiGe-base HBT. A 2-/spl mu/m-wide BPSG/SiO/sub 2/ refilled trench was introduced in order to reduce the substrate capacitance. The low dielectric constant of BPSG/SiO/sub 2/ and the wide trench are very effective in reducing the sidewall element of substrate capacitance. This technology makes it possible to obtain ultra-high-speed operation with a 9.3-ps-gate-delay emitter-coupled-logic (ECL) circuit.

Si/Ge x Si 1−x heterojunction bipolar transistors formed by Ge ion implantation in Si. Narrowing of band gap and base width

Si/Ge x Si 1− x heterojunction n-p-n bipolar transistors (HBT) with a double polycrystalline silicon (polysilicon) self-aligned structure were fabricated by using high dose Ge implantation for the formation of the Si/Ge x Si 1− x heterostructure and As and BF 2 implantation for emitter and base doping. Improvements in electrical characteristics compared to reference Si transistors are demonstrated and related to a band gap narrowing in the base region and to a reduction of B diffusion.

Low operating current and high-temperature operation of 650-nm AlGaInP high-power laser diodes with real refractive index guided self-aligned structure

Low operating current and high-temperature operation has been demonstrated in 650-nm AlGaInP high-power laser diodes with real refractive index guided self-aligned (RISA) structure. The RISA structure features an Al/sub 0.5/In/sub 0.5/P current blocking layer, which leads to small internal loss in the waveguide and substantially reduced operating carrier density. The resultant operating current for 50-mW continuous-wave at 70/spl deg/C is as low as 98 mA, which is almost a half of the lowest value ever reported.

A 1/2-in, 1.3 M-pixel progressive-scan CCD image sensor employing 0.25-μm gap single-layer poly-Si electrodes

A 1/2-in, 1.3 M-pixel progressive-scan interline-transfer charge coupled-device (IT-CCD) image sensor has been developed for low-power and high-sensitivity digital cameras. The image sensor uses 0.25-/spl mu/m gap single-layer poly-Si for CCD transfer electrodes in order to reduce the power consumption and number of fabrication process steps. The image sensor achieved a low driving voltage (2.1 V) on a horizontal CCD (H-CCD) at a frequency of 24.5 MHz. An original pixel layout and a self-aligned photodiode structure make it possible to achieve a progressive scan pixel with well-controlled photodiode readout characteristics. An output three-stage source follower amplifier with new multioxide transistors, whose gate insulator thickness is thinner than that of a CCD register, is able to attain 17% higher gain than that of the conventional amplifier. The sensor provides low-power (100 mW) and high output sensitivity. The total number of steps for fabricating the sensor was reduced to 70% of that for conventional three-layer poly-Si electrodes.

Optical Filter for Fabricating Self-Aligned Amorphous Si TFTS

AbstractSelf-aligned structures for bottom-gate amorphous Si TFTs provide a number of advantages, including reduced parasitic capacitance, smaller device dimensions, and improved uniformity in device performance for large-area electronics. A difficult challenge in making self-aligned TFT structures is the necessity of making source/drain contacts that exhibit low contact resistances and that are precisely aligned relative to the gate electrode. In this article, we describe a novel process for fabricating self-aligned amorphous Si TFTs. This process utilizes a pulsed excimer laser (308 nm) to dope or to activate dopants in a-Si to form the source/drain contacts. An important feature of the device design is an optical filter to protect the a-Si channel region from radiation damage during the 308 nm laser process. However, the optical filter allows the transmission of the uv light for lithography exposure from the backside of the substrate to align the channel region with the gate electrode. This new process enables the fabrication of high performance self-aligned a-Si TFTs with poly-Si source and drain contacts.