Self-aligned Structure Research Articles

Study on the Lateral Carrier Diffusion and Source-Drain Series Resistance in Self-Aligned Top-Gate Coplanar InGaZnO Thin-Film Transistors

We investigated the lateral distribution of the equilibrium carrier concentration (n0) along the channel and the effects of channel length (L) on the source-drain series resistance (Rext) in the top-gate self-aligned (TG-SA) coplanar structure amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The lateral distribution of n0 across the channel was extracted using the paired gate-to-source voltage (VGS)-based transmission line method and the temperature-dependent transfer characteristics obtained from the TFTs with different Ls. n0 abruptly decreased with an increase in the distance from the channel edge near the source/drain junctions; however, much smaller gradient of n0 was observed in the region near the middle of the channel. The effect of L on the Rext in the TG-SA coplanar a-IGZO TFT was investigated by applying the drain current-conductance method to the TFTs with various Ls. The increase of Rext was clearly observed with an increase in L especially at low VGSs, which was possibly attributed to the enhanced carrier diffusion near the source/drain junctions due to the larger gradient of the carrier concentration in the longer channel devices. Because the lateral carrier diffusion and the relatively high Rext are the critical issues in the TG-SA coplanar structure-based oxide TFTs, the results in this work are expected to be useful in further improving the electrical performance and uniformity of the TG-SA coplanar structure oxide TFTs.

From STT-MRAM to Voltage-Control Spintronics Memory (VoCSM) in Pursuit of Memory Systems with Lower Energy Consumption

We designed a voltage-control spintronics memory unit-cell, VoCSM, with high write-efficiency to prove a potential to reduce writing energy per bit. By optimizing a self-aligned structure, the cell has the critical switching current (ISUBcsw/SUB) smaller than 50 μA at 20 nsec. for designed MTJ size of about 50 × 150 ㎚². The value is much smaller than that for mature STT-MRAM with the similar dimension. VoCSM also was proved to have unlimited endurance. Finally, with an empirical equation of Icsw further reduction of ISUBcsw/SUB is estimated to clarify that VoCSM has a potential to reduce Icsw down to several μA.

Growth direction control of lithium dendrites in a heterogeneous lithiophilic host for ultra-safe lithium metal batteries

Dendritic growth of the metallic lithium anode cannot be fully avoided for prolonged cycling due to the inherent thermodynamic and kinetic tendency, which causes serious safety issues. Here, we strategically control the lithium metal growth direction by designing a three-dimensional porous host with lithiophilic-lithiophobic characterized ligaments. Therefore, lithium metal can only nucleate on the lithiophilic back surface and grow toward the direction away from the separator. Such ‘backside-growth’ can ensure safe battery operation even when lithium dendrites exist. For a proof-of-concept study, highly lithiophilic gold layer is sputtered on backside surface of each copper foam ligament. During lithium plating, lithium nucleates on the lithiophilic backside and keeps growing conformably from the existing nuclei towards the opposite direction to the separator, and eventually forms a lithium-metal layer with highly compacted self-aligned columnar structure. The novel approach controls lithium deposition in two aspects simultaneously: growth direction and morphology. Notably, the featured surface dendrite-free anode exhibits ultra-long-term stable cycling with a high Coulombic efficiency (e.g., 95.0% after 300 cycles, 0.5 mA cm−2, 1 mA h cm−2). This work may not only pave ways for building ultimate safe lithium batteries but also conceptually provides new opportunities for other metal anodes.

(Invited) High Write Efficiency in Voltage-Control Spintronics Memory (VoCSM) for Saving Energy Consumption of Nonvolatile Memories

MRAM based on spin-transfer-torque (STT) write operations has been intensively developed as a technology for saving energy. During the development of high-density STT-MRAM, issues have arisen that have placed an intrinsic physical limit on the miniaturization of STT-MRAM. Recently, we proposed and developed a voltage-control spintronics memory (VoCSM) that employs the voltage-controlled-magnetic-anisotropy (VCMA) effect for the selection of MTJs and the spin-Hall effect (SHE) for write operations [1]. We achieved high write efficiency in the VoCSM by taking the following approaches: (1) developing a self-aligned VoCSM structure; (2) improving the spin-Hall electrode to have a large spin-Hall angle; and (3) optimizing the magnetic design of the storage layer. The VoCSM in the present study employs in-plane MTJs. The critical switching current Ic0 in this VoCSM is expressed as follows: Ic0 ~ (2e/ħ)αM S t eff{-(H k_eff-H k_eff(V))/2}(w N t N/θ SH) Here, e is the charge of an electron, α is a damping constant, ħ is Planck’s constant divided by 2π, M S is the saturation magnetization, t eff is the effective thickness of the storage layer, H k_eff is the effective perpendicular magnetic anisotropy field, H k_eff(V) is the variation of H k_eff by the applied voltage (V MTJ), w N and t N are respectively the width and thickness of the spin-Hall electrode, and θ SH is the spin-Hall angle. Approach (1) We fabricated a VoCSM consisting of a string of several MTJs on spin-Hall electrodes as shown in Fig. 1. In the self-aligned VoCSM structure, since the width of the spin-Hall electrode and that of the MTJ are same, almost all of the spin-polarized electrons can exert torque on the storage layer. This enabled a large reduction in the Ic of the self-aligned VoCSM [2]. Furthermore, when the spin-Hall electrode was made thinner by using a highly-selective patterning process, Ic was further reduced [3]. Approach (2) We applied a novel amorphous-TaB/ β-Ta spin-Hall electrode in the VoCSM, as shown in Fig. 1. The amorphous TaB exhibits a large spin-Hall angle (θ SH = -0.18) that is twice that of β-Ta, because extrinsic effects likely have a dominant role in the SHE of TaB [4]. We successfully prepared an extremely small magnetic dead layer (DL) of the storage layer with small interface roughness by using the TaB spin-Hall electrode. The estimated interfacial transparency of CoFeB/TaB had a relatively high value of 0.60 due to the extremely small DL. Approach (3) In the precessional switching mode for in-plane MTJs as represented in Fig. 1, since the spins in the storage layer precess from in-plane to out-of-plane, increasing H k_eff has a big impact on lowering Ic. However, the total magnetization M S t eff and H k_eff are correlated significantly with the magnetic design of the device. In particular, although lowering the total magnetization M S t eff has the advantage of lowering Ic, it may also have the effect of decreasing the retention Δ. In this study, we were able to maintain the retention Δ by increasing t eff (i.e. reducing the size of DL) despite the decreased M S. Consequently, from the perspective of lowering Ic, we successfully achieved factors such as high θ SH, self-aligned device structure related to small w N t N, high H k_eff, low α, and low M S. Device properties of the VoCSM By combining the self-aligned fabrication technique with a novel TaB spin-Hall electrode, a quite small value of critical switching current (Ic ~ 79 μA) was achieved despite a relatively large MTJ size (60 nm × 150 nm). We successfully reduced the write current further to 48 μA by the VCMA effect. The write efficiency of the VoCSM without the VCMA effect is about 4 times higher, and furthermore the write efficiency of the VoCSM by using the VCMA effect can reach 8 times higher compared with STT write operations. The VoCSM device also demonstrates high reliability such as a low write error rate (< 1 × 10-8), high endurance (> 1 × 1012 cycles), and large break-down voltage (> 2.5 V). These results indicate that VoCSM could open a path to realizing high-density nonvolatile memories with low power consumption and high-speed read and write operations. This work was partly supported by the ImPACT Program of the Council for Science, Technology and Innovation (Cabinet Office, Government of Japan).

Low-Parasitic-Capacitance Self-Aligned 4H-SiC nMOSFETs for Harsh Environment Electronics

Low-parasitic-capacitance 4H-SiC nMOSFETs using a novel self-aligned process were suggested and demonstrated. In these nMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain, drain-source capacitance) were investigated and low parasitic capacitance was achieved by the self-aligned structure.

High-Resolution Inkjet-Printed Oxide Thin-Film Transistors with a Self-Aligned Fine Channel Bank Structure.

A self-aligned inkjet printing process has been developed to construct small channel metal oxide (a-IGZO) thin-film transistors (TFTs) with independent bottom gates on transparent glass substrates. Poly(methylsilsesquioxane) was used to pattern hydrophobic banks on the transparent substrate instead of commonly used self-assembled octadecyltrichlorosilane. Photolithographic exposure from backside using bottom-gate electrodes as mask formed hydrophilic channel areas for the TFTs. IGZO ink was selectively deposited by an inkjet printer in the hydrophilic channel region and confined by the hydrophobic bank structure, resulting in the precise deposition of semiconductor layers just above the gate electrodes. Inkjet-printed IGZO TFTs with independent gate electrodes of 10 μm width have been demonstrated, avoiding completely printed channel beyond the broad of the gate electrodes. The TFTs showed on/off ratios of 108, maximum mobility of 3.3 cm2 V-1 s-1, negligible hysteresis, and good uniformity. This method is conductive to minimizing the area of printed TFTs so as to the development of high-resolution printing displays.

Automated, high-throughput photonic packaging

Abstract Silicon photonics can enable optical circuits of unprecedented complexity and cost efficiency. It employs lithography to effectively pre-assemble optical devices on wafers fabricated in existing microelectronic facilities with decades of cost and reliability optimization. Unfortunately, the packaging of photonic chips still employs legacy approaches, which limit the device’s cost efficiency and scalability. To address this challenge, we have developed a novel approach to photonic packaging centered on shifting complexity from chip-level assembly to wafer-level planar fabrication. Self-alignment structures and large-mode converters are integrated on chip to enable photonic packaging in standard, automated, high-throughput microelectronic assembly tools. We demonstrate solutions to interfacing standard optical fibers to chips and to interfacing photonic chips to other photonic chips. We show wide spectral bandwidth and a peak transmission of −1.3 dB from a standard fiber patch cable to chip and −1.1 dB from chip to chip. We believe this new direction can help silicon photonics reach its full potential.

Structural coloration of transmission light through self-aligned and complementary plasmonic nanostructures.

Structural coloration of natural surfaces often originates from the change of reflected colors depending on the viewing or illumination angle. Recently, the structural coloration of nanoplasmonic structures has attracted a great deal of attention due to high compactness, robust stability and high color-tunability, as well as high sensitivity to the incidence angle. Here we report complementary plasmonic structures (CPS) for transmission structural coloration by tailoring a single spectral peak depending on the incidence angle of light. The CPS features self-aligned silver nanohole and nanodisk arrays, supported by dielectric nanopillar arrays of hydrogen silsesquioxane. Unlike the conventional hybridized nanostructures of plasmonic nanohole and nanodisk arrays, the nanodisks of CPS effectively attenuate undesired spectral peaks of nanoholes by exploiting an extinction peak of nanodisks, serving as a spectral suppressor. As a result, a single transmission spectral peak becomes red-shifted from 736 nm to 843 nm as the incidence angle varies from 0° to 30°. This unique configuration provides a new direction for tunable filters that can be utilized for compact multispectral or hyperspectral imaging applications.

Impact of SiNx capping on the formation of source/drain contact for In-Ga-Zn-O thin film transistor with self-aligned gate

Self-aligned gate structures are preferred for faster operation and scaling down of thin film transistors by reducing the overlapped region between source/drain and gate electrodes. Doping on source/drain regions is essential to fabricate such a self-aligned gate thin film transistor. For oxide semiconductors such as In-Ga-Zn-O, SiNx capping readily increases their carrier concentration. We report that the SiNx deposition temperature and thickness significantly affect the device properties, including threshold voltage, field effect mobility, and contact resistance. The reason for these variations in device characteristics mainly comes from the extension of the doped region to the gated area after the SiNx capping step. Analyses on capacitance-voltage and transfer length characteristics support this idea.

Monolithic InP Stokes Vector Receiver With Multiple-Quantum-Well Photodetectors

Stokes vector modulation direct-detection (SVM-DD) formats have attained special attention in the short-reach communication links to transmit multilevel signals without using costly coherent receivers. In this paper, we fabricate and experimentally demonstrate a potentially low-cost DD-based SV receiver with on-chip photodetectors (PD) on a compact InP chip. Compressively strained multiple-quantum-well PD array is monolithically integrated with the SV projection circuit, which consists of multimode interference splitter and SV rotators based on self-aligned half-ridge structure. From the photocurrent signals at three on-chip PDs, the SV of input light is retrieved successfully over the entire Poincare sphere. With potentially broad operating bandwidth of InP-based PDs, the demonstrated device may be an attractive candidate to realize low-cost and high-speed receivers for the future short-reach SVM-DD systems.

Origin of Electrical Instabilities in Self-Aligned Amorphous In–Ga–Zn–O Thin-Film Transistors

This paper examined the performance and bias stability of amorphous In–Ga–Zn–O ( ${a}$ -IGZO) thin-film transistors (TFTs) with a self-aligned coplanar structure. The activation energy barrier responsible for the positive bias thermal stress (PBTS)-induced instability of the ${a}$ -IGZO TFTs with low oxygen loadings can be attributed to the migration of cation interstitial defects. However, the IGZO TFTs with high oxygen loadings could not be explained by the existing defect model. The first-principle calculation indicates that the cation vacancy, such as ${V}_{\textsf {In}}$ , with the hydrogen incorporation plays an important role in determining the PBTS-dependent degradation of the threshold voltage.

Dendrite-Free Lithium Deposition with Self-Aligned Columnar Structure in a Carbonate–Ether Mixed Electrolyte

Batteries with lithium metal anodes are promising because of lithium’s high energy density. However, the growth of Li dendrites on the surface of the Li electrode in a liquid electrolyte during cycling reduces the safety and cycle performance of batteries, hindering their commercial application. In this work, we observe for the first time a smooth and dendrite-free Li deposition with a vertically grown, self-aligned, and highly compact columnar structure formed during cycling in a mixed carbonate–ether electrolyte. The stable microsized (∼10 μm in diameter and ∼20 μm in length) Li deposits are aligned in arrays on the surface of the Li electrode. The columnar Li deposits still exhibit a dendrite-free morphology and a compact structure after 200 cycles at a current density of 1 mA/cm2 and a 1.5 mAh/cm2 cycling capacity in a mixed carbonate–ether electrolyte. This work shows an optimiztic outlook for Li batteries with liquid electrolytes.

Systematic Decomposition of the Positive Bias Stress Instability in Self-Aligned Coplanar InGaZnO Thin-Film Transistors

We propose an experimental method to decompose the positive gate-bias stress (PBS)-induced threshold voltage shift ( $\Delta {V}_{\mathsf {th}})$ of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) into the contributions of distinct degradation mechanisms. Top-gate self-aligned coplanar structure TFTs are used for this letter. Stress-time-divided measurements, which combine the subgap density-of-states (DOS) extraction and the analysis on recovery characteristics, are performed to separate the $\Delta {V}_{\mathsf {th}}$ components. Change in excess oxygen ( $\text{O}_{\mathsf {ex}})$ -related DOS is clearly observed, and $\Delta {V}_{\mathsf {th}}$ by PBS is quantitatively decomposed into the contributions of the active $\text{O}_{\mathsf {ex}}$ , and the deep and shallow gate insulator traps. The quantitative decomposition of PBS-induced $\Delta {V}_{\mathsf {th}}$ provides physical insight and key guidelines for PBS stability optimization of a-IGZO TFTs.

Ultra-conformable Organic Field-Effect Transistors and circuits for epidermal electronic applications

In this work we report the development of electronic circuits based on low voltage Organic Field-Effect Transistors (OFETs), entirely fabricated on polymer nanosheets acting as sub-micrometric substrates. The overall thickness of the proposed circuits (including the substrate, a 400 nm-thick Parylene C nanosheet) is only 600 nm, thus making them highly flexible, ultra-conformable and light-weighted. A complete characterization of the fabricated devices is reported. Mechanical performances of the nanosheets are thoroughly discussed. Full swing complementary inverters fabricated on same substrate show low noise margins and gains up to 10. Thanks to a carefully designed self-aligned structure, these devices are characterized by a very good frequency response, with a cut-off frequency usually ranging around 100 kHz. The ultra-conformability of such nanosheets allows their transfer and adhesion on complex target surfaces, such as the human skin without a significant change in their electrical performances, representing a step forward to the realization of conformable electronics particularly suited for personal monitoring systems for healthcare and sport.

Enhanced performance in graphene RF transistors via advanced process integration

The state-of-the-art performance of a graphene radio-frequency (RF) field-effect transistor (FET) made of chemical vapor deposition (CVD) graphene is presented. The record high cut-off frequency as high as 380 GHz using CVD graphene was attributed to the implementation of advanced process integration. On the one hand, interface engineering has become critical in two-dimensional (2D) electronics since the charge transport of a 2D electron system like graphene is highly affected by the interface. The interface engineering was made for both the top and bottom of the graphene surface by implementing a non-polar material (1, 3, 5-trimethyl-1, 3, 5-trivinyl cyclotrisiloxane). In contrast to conventional polar materials, such as SiO2, the non-polar materials significantly reduce the surface optical phonon scattering in the graphene channel, leading to the enhanced RF performance of graphene FET. On the other hand, micro-scaled holes over the multilayer graphene and self-aligned structure also become a critical factor in minimizing the parasitic resistance that is inversely proportional to RF performance. As the growth technique of CVD graphene greatly advances, the advanced process integration scheme could bring graphene electronics one step further towards practical application.

Self-aligned nanoislands nanobeam bandedge lasers.

We propose and demonstrate a novel one-dimensional nanobeam bandedge laser constituted by self-aligned nanoisland quantum-well (QW) structures. The formation of self-aligned InGaAsP nanoislands sandwiched between two InP claddings is the result of selective removal of QW through wet-etching processes. By controlling wet-etching time, we show a good spatial and spectral overlap between the dielectric mode and the self-aligned nanoisland structures leads to the realization of nanobeam bandedge lasers with low-threshold operations and high slope efficiencies. Optical characterization results indicate a strong correlation between the size of individual nanoisland and the threshold power of our nanobeam bandedge lasers. We obtain an approximately 81% reduction in the absorbed threshold power as we optimize the size of the nanoislands.

Anisotropic magnetoresistive transducers on the basis of a self-aligned structure

A new design of anisotropic magnetoresistive structures, in which the shape of ferromagnetic elements repeats the shape of nonmagnetic conducting shunts, is proposed in order to increase sensitivity. Numerical simulation taking into account the nonuniform distribution of magnetization shows that selfaligned structures have a significantly higher sensitivity than classical “barber-pole” structures. Presumably, this advantage can be explained by the nonuiniformity of the magnetization in self-aligned structures, which compensates the influence of irregularity of the electric-current distribution.

Silicon and Dopant Ink-Based CMOS TFTs on Flexible Steel Foils

ABSTRACTPolysilicon complementary metal oxide semiconductor (CMOS) thin film transistors (TFTs) are fabricated on large area, flexible stainless steel foils using novel ink depositions within a hybrid printed/conventional process flow. A self-aligned top gate TFT structure is realized with an additive materials approach to substitute the use of high capital cost ion implantation and lithography processes. Polyhydrosilane-based silicon ink is coated and laser crystallized to form the polysilicon channel. Semiconductor grade P-type and N-type unique dopant ink formulations are screen printed and combined with thermal drive in and activation to form self-aligned doped source and drain regions. A high refractory top gate material is chosen for its process compatibility with printed dopants, chemical resistance, and work function. Steel foil substrates are fully encapsulated to allow for high temperature processing. The resultant materials set and process flow enables TFT electrical characteristics with NMOS and PMOS mobilities exceeding 120 cm2/Vs and 60 cm2/Vs, respectively. On/Off ratios are &gt;107. Reproducibility, uniformity, and reliability data in a production environmental is shown to demonstrate high volume, high throughput manufacturability. The device characteristics and scheme enable NFC (13.56MHz) capable circuits for use in flexible NFC and display-based smart labels and packaging.

Surface-Enhanced Infrared Absorption of Self-Aligned Nanogap Structures

Plasmonic nanostructures are often used in surface-enhanced infrared absorption (SEIRA) spectroscopy to probe surface assembled molecules or the dielectric environment surrounding the metallic nanostructures. Here we fabricate metallic nanogap structures using self-aligned techniques on an intrinsic silicon substrate and correlate resulting SEIRA spectra with the choice of metal nanostructure geometry. A motivation is to compare the enhancement from hybridization of bright plasmon modes with the effect of hybridization between bright and dark plasmon modes. These structures provide a gap size below 10 nm and support strong field enhancements. The structures demonstrate their sensitivity through the enhanced absorption signature of the Si–O stretch in the native silicon oxide layer of nanometer thickness beneath the metal. Simulations reveal this thin layer plays a critical role in determining the plasmon modes of the nanostructures. Numerical simulations of the optical properties are consistent with the observations that stronger Si–O stretch signals are detected on self-aligned nanogap structures than nanorod arrays, highlighting the enhanced electromagnetic fields in the underlying native oxide.

Bottom-Gate Self-Aligned Homojunction TFT with Double Oxide Semiconducting Layers

After huge effort has been made over the last decade, oxide thin-film transistors (TFTs) have been successfully adopted in the backplane of high resolution AM-LCD and AM-OLED displays. However, as displays and electronic devices evolve to next generations, it is necessary to not only enhance field-effect mobility, but also reduce RC-delay for high driving speed [1, 2]. In this regard, self-aligned structure has been considered as one of promising candidates for satisfying these requirements [3] due to the minimum parasitic capacitances between electrodes. Nonetheless, there are several concerns especially in doping process at contact region because it is difficult to control dopant diffusion, resulting in unstable performance and another unexpected parasitic capacitance. Here, we propose improved structure adopting double oxide semiconducting layers, which can precisely define the channel dimension by gate electrode. Figure 1 demonstrates both structures of conventional self-aligned TFT and our improved self-aligned TFT. As shown in the figure, first channel layer of oxide material with high mobility and high carrier density plays as the real electron flow path and the contacts with source/drain (S/D) metal electrode without additional doping process. Consequently, the issues originated from doping process can be easily overcome. Meanwhile, second active layer with the relatively low carrier density is defined by the gate electrode and plays a role as a carrier controlling part for reliable switching performance. To fabricate our self-aligned TFTs, gate metal was firstly patterned on glass substrate by wet etching. After depositing SiO2 by PECVD as a gate insulator, first semiconducting layer was grown by sputter or plasma-enhanced atomic layer deposition (PEALD). The second active layer was deposited and formed by back-side exposure using gate electrode as a masking layer. Then, SiO2 by PECVD was deposited to passivate whole device. Finally, S/D metal layer was formed, followed by annealing process in vacuum condition. As a starting research, we had to carefully consider proper oxide semiconductors according to their characteristics and etch selectivity between first and second channel layers. Although adopting highly conducting oxides such as ITO and In2O3 as a first channel layer would be better for lowering the contact resistance, it is hard to deplete the carriers. Hence, thinner film thickness (<10nm) or other deposition method such as PEALD should be considered to obtain semiconducting behavior. Accordingly, we have firstly investigated the switching behavior of In2O3/ZnO double layered TFT by means of PEALD with bottom-gate coplanar structure. The In2O3/ZnO TFT shows mobility of 32 cm2/Vs with good bias stability as shown in Figure 2. The improved self-aligned TFTs were successfully fabricated and well-performed using sputtered ITO/IGZO and PEALD In2O3/ZnO. We will report the device characteristics and further investigate and reveal the origin of stable electrical behavior by simulation. [Acknowledgement] This work was supported by Open Innovation Lab Project from National Nanofab Center (NNFC). [Reference] [1] K. Yokoyama, S. Hirakata, S. Yamazaki, M. Nakada, T. Sato, and N. Goto, “A 2.78-in 1058-ppi ultra-high-resolution OLED display using CAAC-OS FETs,” SID digest 2015, 46, 1039-1042. [2] J. U. Bae, D. H. Kim, K. Kim, K. Jung, W. Shin, I. Kang, and S. D. Yeo, “Development of oxide TFT’s structures,” SID digest 2013, 44, 89-92. [3] N. Morosawa, Y. Ohshima, M. Morooka, T. Arai, and T. Sasaoka, “Novel self-aligned top-gate oxide TFT for AMOLED displays,” Journal of the society for Information Display 2012, 20 (1), 47-52. Figure 1