Bottom-Gate Self-Aligned Homojunction TFT with Double Oxide Semiconducting Layers

Abstract

After huge effort has been made over the last decade, oxide thin-film transistors (TFTs) have been successfully adopted in the backplane of high resolution AM-LCD and AM-OLED displays. However, as displays and electronic devices evolve to next generations, it is necessary to not only enhance field-effect mobility, but also reduce RC-delay for high driving speed [1, 2]. In this regard, self-aligned structure has been considered as one of promising candidates for satisfying these requirements [3] due to the minimum parasitic capacitances between electrodes. Nonetheless, there are several concerns especially in doping process at contact region because it is difficult to control dopant diffusion, resulting in unstable performance and another unexpected parasitic capacitance. Here, we propose improved structure adopting double oxide semiconducting layers, which can precisely define the channel dimension by gate electrode. Figure 1 demonstrates both structures of conventional self-aligned TFT and our improved self-aligned TFT. As shown in the figure, first channel layer of oxide material with high mobility and high carrier density plays as the real electron flow path and the contacts with source/drain (S/D) metal electrode without additional doping process. Consequently, the issues originated from doping process can be easily overcome. Meanwhile, second active layer with the relatively low carrier density is defined by the gate electrode and plays a role as a carrier controlling part for reliable switching performance. To fabricate our self-aligned TFTs, gate metal was firstly patterned on glass substrate by wet etching. After depositing SiO2 by PECVD as a gate insulator, first semiconducting layer was grown by sputter or plasma-enhanced atomic layer deposition (PEALD). The second active layer was deposited and formed by back-side exposure using gate electrode as a masking layer. Then, SiO2 by PECVD was deposited to passivate whole device. Finally, S/D metal layer was formed, followed by annealing process in vacuum condition. As a starting research, we had to carefully consider proper oxide semiconductors according to their characteristics and etch selectivity between first and second channel layers. Although adopting highly conducting oxides such as ITO and In2O3 as a first channel layer would be better for lowering the contact resistance, it is hard to deplete the carriers. Hence, thinner film thickness (<10nm) or other deposition method such as PEALD should be considered to obtain semiconducting behavior. Accordingly, we have firstly investigated the switching behavior of In2O3/ZnO double layered TFT by means of PEALD with bottom-gate coplanar structure. The In2O3/ZnO TFT shows mobility of 32 cm2/Vs with good bias stability as shown in Figure 2. The improved self-aligned TFTs were successfully fabricated and well-performed using sputtered ITO/IGZO and PEALD In2O3/ZnO. We will report the device characteristics and further investigate and reveal the origin of stable electrical behavior by simulation. [Acknowledgement] This work was supported by Open Innovation Lab Project from National Nanofab Center (NNFC). [Reference] [1] K. Yokoyama, S. Hirakata, S. Yamazaki, M. Nakada, T. Sato, and N. Goto, “A 2.78-in 1058-ppi ultra-high-resolution OLED display using CAAC-OS FETs,” SID digest 2015, 46, 1039-1042. [2] J. U. Bae, D. H. Kim, K. Kim, K. Jung, W. Shin, I. Kang, and S. D. Yeo, “Development of oxide TFT’s structures,” SID digest 2013, 44, 89-92. [3] N. Morosawa, Y. Ohshima, M. Morooka, T. Arai, and T. Sasaoka, “Novel self-aligned top-gate oxide TFT for AMOLED displays,” Journal of the society for Information Display 2012, 20 (1), 47-52. Figure 1