Self-aligned Titanium Silicide Research Articles

Self-aligned-TiSi2 bottom contact with APM cleaning and post-annealing for sputtered-MoS2 film

Electrical contact characteristics between self-aligned titanium silicide (TiSi2) and sputtered-molybdenum disulfide (MoS2) films were newly demonstrated. In contrast with metal contacts, the surface of the TiSi2 bottom-contact was cleaned by using an ammonia and hydrogen peroxide mixture (APM) before MoS2 deposition, because the TiSi2 film has high oxidation resistance. In order to extract the contact resistance, a transmission line model device was fabricated. A two-order reduction in the contact resistance was achieved by a post-annealing at 650 °C in forming gas ambient (3% H2 in N2). This reduction was attributed to selective titanium diffusion from bottom contact into the MoS2 film. The TiSi2 contact is thus speculated as a candidate for a practical contact material in MoS2 devices.

A study of self-aligned formation of C54 Ti(Si1−xGex)2 to P+ and N+ Si0.7Ge0.3 alloys using rapid thermal annealing

In this paper, solid state reactions of titanium with boron and phosphorus doped Si0.7Ge0.3 alloys have been investigated for application in a self-aligned germanosilicide process. Wet chemical etching of the germanosilicide with respect to unreacted Ti in a solution of 1:1:5 NH4OH:H2O2:H2O has been investigated. Characterization was performed using four-point probe sheet resistance measurements, x-ray diffraction, cross-sectional transmission electron microscopy, Nomarski optical imaging, and scanning electron microscopy. The C54 Ti(Si1−yGey)2 phase was observed to form for reactions on both boron and phosphorus doped Si0.7Ge0.3 alloys. Grain structures of the C54 phases were found to be similar to grain structures of intrinsic alloy reactions with lateral grain dimensions on the order of 0.3 Μm. Resistivities of 22 ΜΩ-cm have been determined for the boron and phosphorus reactions. Although the germanosilicide phases were observed to etch slowly in 1:1:5 NH4OH:H2O2:H2O, which is conventionally used in the self-aligned titanium silicide process, the much higher etch rate of titanium nitride compounds and unreacted Ti provided for a self-aligned germanosilicide process. A first anneal in a nitrogen ambient was found to be necessary to eliminate lateral silicidation over surrounding oxide during self-aligned germanosilicide formation.

Titanium silicide/silicon nonohmic contact resistance for NFET's, PFET's, diffused resistors, and NPN's in a BiCMOS technology

Self-aligned titanium silicide is often used to minimize the polysilicon and diffusion sheet resistances. Current is delivered to the channel of FET's, the body of diffused resistors, and into the active region of NPN's through the titanium silicide/silicon interface. This contact resistance can represent a significant fraction of the total device resistance for devices of small dimensions, and contributes to a loss in circuit performance. The impedance of this interface is a function of the doping level in the silicon immediately below the interface, and this doping level is a sensitive function of the heat applied to the structure after the formation of the silicide. The correspondence of FET series resistance, emitter resistance, the diffused resistor end effects and the non-ohmic nature of a contact after heat is applied is presented. Use of a rapid thermal anneal to obtain the requisite silicide characteristics while minimizing the impact on the contact resistance is demonstrated for a 0.8-/spl mu/m BiCMOS technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Ultra-Shallow Raised P+N Junctions with Self-Aligned Titanium Silicide Contacts formed by Boron Outdiffusion from Selectively Deposited Silicon Epitaxial Layers

AbstractIn this study, we have fabricated ultra-shallow p+n junctions by boron outdiffusion from selectively deposited Si epitaxial layers. The undoped layers (900 – 1000 Å) were selectively deposited on active areas in a UHV-RTCVD reactor using Si2H6 and Cl2 at 800°C and at a total pressure less than 30 mTorr. Junctions were formed by BF2 ion-implantation into epitaxial layers with and without Ge preamorphization followed by RTA at 1000°C and 1050°C for 10 s in Ar. Junction depths ranging from 400 Å to 700 Å were formed at a background concentration of l×1016 cm−3. Abrupt boron profiles with epitaxy/substrate interface concentrations on the order of 1020 cm-3 were formed. Self-aligned TiSi2 was formed at four different thicknesses by evaporating 100, 200, 300 or 400 Å thick Ti followed by a two-step RTA cycle with a selective etch between to remove the unreacted Ti on Si02. Our results show that raised junctions with a Ti thickness of 400 Å (corresponding to a TiSi2 thickness over 900 Å and consumption of the entire epitaxial layer) exhibit a reverse leakage of less than 10 pA for a device area of 800×800 μm2. This corresponds to areal and peripheral leakage current densities of 67 pA/cm2 and 4 pA/cm. Therefore, thick silicide layers can be used on raised junctions reducing the junction sheet resistance and eliminating the possibility of silicide agglomeration. Furthermore, implantation damage in substrate is eliminated by confining the implant into the raised region which is later consumed during silicide formation.

Response Surface for CMOS Self-Aligned Titanium Silicide Process

ABSTRACTSputtered deposited titanium films on silicon substrates were used to study the effects of first rapid thermal anneal temperature, duration of anneal time and thickness of the titanium films for TiSi2 formation. A central composite, coupled with a cross design was used to analyze response surface. Empirical models were developed and contour plots were generated to describe the outcome of the first anneal. A window of operation to control the process of titanium silicide formation was recommended. Response surface analysis of data revealed an operating window of ±10° C for RTA1 for stable TiSi2 formation. Within this window of operation, the within wafer uniformity was found to be at its minimum. Anneal time was found to have minimum effect on the variability although sheet resistance decreases monotonically with increasing anneal time. Thickness of titanium films were found to be very critical in determining final TiSi2 thickness as determined by RBS and/or XRF techniques.

Use of screening and response surface experimental designs for development of a 0.5 μm CMOS self-aligned titanium silicide process : Robert E. Jones and Thomas C. Mele. IEEE Trans. Semicond. Mfg4(4), 281 (1991)

Use of screening and response surface experimental designs for development of a 0.5 μm CMOS self-aligned titanium silicide process : Robert E. Jones and Thomas C. Mele. IEEE Trans. Semicond. Mfg4(4), 281 (1991)

Insitu TEM observation of epitaxial CoSi2 formation on (100) silicon

Self-aligned titanium and cobalt silicide layers on silicon (Salicides) have been used as low resistivity metal contacts for advanced CMOS devices. However, the scaling of devices to smaller dimensions places increasing requirements on Salicide properties. Controlling junction consumption, interface roughness, lateral growth, thermal stability and resistivity during silicide formation limit the use of these materials. Epitaxial silicides offer significant advantages over polycrystalline films because of their thermal stability and low resistivity. Epitaxial Ti and Co disilicides have been grown on (111)Si by MBE. Recently, growth of epitaxial Co disilicide on (001)Si has been reported using bimetallic layers of Co and Ti as source materials. Planar CoSi2/Si interfaces with defect free grains have been produced. Uniform low resitivity films are produced using standard processing conditions. The process involves sequential deposition of Ti and Co on (001 )Si. Titanium is a reactive metal which acts as a getter for the residual native oxide on the Si surface and as a reaction barrier between Co and Si at low temperatures.

Use of screening and response surface experimental designs for development of a 0.5- mu m CMOS self-aligned titanium silicide process

A manufacturable self-aligned titanium silicide process for 0.5- mu m CMOS technologies has been developed. Factorial and fractional-factorial screening experiments, as well as physical models, were used to identify important process factors. Central-composite and D-optimal response surface designs were used to optimize the process; short-loop process and device experiments and 0.5- mu m technology static random access memory (SRAM) circuit flows were used. By using this comprehensive experimental design methodology, problems with diode leakage and silicide-to-silicon contact resistance were resolved, and specified device characteristics were achieved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

ChemInform Abstract: Thermally Stable, Low-Leakage Self-Aligned Titanium Silicide Junctions.

It is found that the thermal stability of TiSi2 films formed on single-crystalline Si depends on the processing conditions used for film preparation.

Optimization of a self-aligned titanium silicide process for submicron technology

The optimization of a manufacturable self-aligned titanium silicide process is described. In particular, the integrity of the TiSi/sub 2/ layer has been studied versus the BPSG reflow conditions. Excellent contact resistance and very low leakage currents have been obtained. The good device parameters obtained with an n/sup +/ or n/sup +//p/sup +/ gate have demonstrated that the self-aligned process can be integrated in a 0.8- mu m double-metal CMOS process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Loss of titanium during formation of self-aligned titanium silicide

Titanium disilicide (TiSi 2) is used in semiconductor circuits for interconnection. An attractive method of fabrication is sputter deposition of titanium on silicon and a subsequent heat treatment in a rapid thermal processor. This method is “self-aligning”, which means that suicide is only formed in silicon windows and not on top of silicon dioxide (SiO 2). During silicidation not all titanium is converted into titanium disilicide. It is found that on top of the TiSi 2 layer a non-conducting layer of oxygen-saturated titanium [Ti(O)] is formed. From thickness measurements it is determined that from the sputter deposited Ti layer 5.3 nm titanium is lost to this non-conducting layer. The formation of this non-conducting layer and hence the loss of Ti is suppressed by deposition of a thin silicon layer (4 nm) on top of the titanium. It is shown that the self-aligned feature is retained in this modified process.

Integrated Processinyg of Silicided Shallow Junctions using Rapid Thermal Annealing Prior to Dopant Activation

ABSTRACTA method for producing shallow silicided diodes for MOS devices (with junction depths of about 0.1 µm), by implanting after forming the silicide layer was investigated. The key to this integrated process is the use of rapid thermal annealing (RTA) to activate the dopants in the silicon, so that there is very little thermal broadening of the implant distribution. Self-aligned titanium silicide (TiSi2) films with thicknesses ranging from 40 to 80 nm were grown by RTA of sputter deposited titanium films on silicon substrates. After forming the TiSi2, arsenic and boron were implanted. A second RTA step was used after implantation to activate these dopants. It was found that implanting either dopant caused a sharp increase in the sheet resistivity of the TiSi2. The resistivity can be easily restored to its original value (about 18 µΩ-cm) by a post implant RTA anneal. RBS analysis showed that arsenic diffuses rapidly in the TiSi2 during RTA at temperatures as low as 600°C. SIMS data indicated that boron was not mobile up to temperatures of 900°C, possibly because it forms a compound with the titanium which precipitates in the TiSi 2. Coalescence of TiSi2 occurs during post implant furnace annealing, leading to an increase in the sheet resistivity. The amount of coalescence depends on the film thickness, but not on whether or not the film had been subject to implantation. Spreading resistance profiling data showed that both arsenic and boron diffused into the TiSi2 during furnace annealing, reducing the surface concentrations of dopant at the TiSi2/Si interface. Both N+/P and P+/N diodes formed by this technique exhibited low leakage currents after the second RTA anneal. This is attributed to removal of the implant damage by the RTA. In summary, the second RTA serves the dual purpose of removing implant damage in the TiSi2 and creating the shallow junction by dopant activation.

A HIGH PERFORMANCE LIQUID-NITROGEN CMOS SRAM TECHNOLOGY

A 3.5 ns ECL-compatible 64Kb liquid-nitrogen CMOS (LN-CMOS) SRAM technology with 2.5V power-supply voltage is described. Key features of this high performance 0.5?m-channel LN-CMOS SRAM technology optimized for 77K operation include 0.6,?m optical lithography for the gate level, dual polysilicon work functions, retrograde n-well, low resistance arsenic and boron source/drain diffusions, self-aligned titanium silicide, and two-level metal interconnects. For the first time, the leverage of liquid nitrogen CMOS with 2.3X chip level performance improvement at 77K over room temperature CMOS is demonstrated.

A FULLY CHARACTERISED PROCESS FOR TITANIUM SILICIDE BY RTA FOR ONE MICRON CMOS

A fully characterised process for self-aligned titanium silicide by RTA is described. Factors influencing formation; surface pre-clean, time-temperature schedules and ambient choice are all discussed. The sensitivity of the formation process to implanted arsenic is also described and a model presented for this effect. The technique is proven by its inclusion in a one-micron trench isolated CMOS process schedule and electrical results for devices and circuits thus fabricated are presented.

Titanium silicide interconnect technology for submicrometer DRAMs

A self-aligned titanium silicide interconnect structure, in which the silicide wire on the isolation oxide is connected with the silicided diffusion layer directly without any contact holes, is discussed. The interconnection is fabricated by using the simultaneous reaction of Ti with the patterned amorphous Si and single-crystalline Si substrate through Si/sup +/ ion-beam interface mixing, rapid thermal annealing at 625 degrees C, and subsequent furnace annealing at 900 degrees C. Here, the physical cross section of the interconnection is clarified and the properties of titanium silicide obtained by this technology are discussed. As an application of this interconnect technology, a bit-line contact structure on a trench-type DRAM (dynamic random-access memory) cell where an Al/bit line contacts the diffusion layer through the titanium silicide pad is proposed. The effectiveness of introducing this pad in the memory cell is also discussed. >

Process and device performance of a high-speed double poly-Si bipolar technology using borosenic-poly process with coupling-base implant

Use of boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly emitter-base process) produces a transistor base width of less than 100nm with an emitter junction depth of 50 nm and an emitter-to-base reverse leakage current of approximately 70 pA. The borosenic-poly process resolves both the channeling and shadowing effects of a sidewall-oxided spacer during the base boron implantation. The process also minimizes crystal defects generated during the emitter and base implantations. The coupling-base boron implant significantly improves a wide variation in the emitter-to-collector periphery punchthrough voltage without degrading the emitter-to-base breakdown voltage current gain, cutoff frequency, or ECL gate delay time. A deep trench isolation with 4- mu m depth and 1.2- mu m width reduces the collector-to-substrate capacitance to 9 fF, while maintaining a transistor-to-transistor isolation voltage of greater than 25 V. The application of self-aligned titanium silicide technology to form polysilicon resistors without holes and to reduce the sheet resistance of the emitter and collector polysilicon electrodes to 1 Omega /square is discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Self-aligned titanium silicide device technology by NH3 plasma assisted thermal annealing

The self-aligned titanium silicide device technology has been studied by using NH3 plasma assisted thermal annealing and ion implant through titanium metal or silicide film. Enhanced surface nitridation of titanium by activated species suppresses lateral silicide growth and oxide contamination. NH3 plasma assisted annealing can be used as an effective method to form TiSi2 and activate implanted dopant. P+N junction and P channel metal–oxide–semiconductor field-effect transistor can be produced by boron implant through Ti metal or its silicide and the NH3 plasma assisted thermal annealing.

Rapid Thermal Processing for Self-Aligned Silicide Technology

ABSTRACTA self-aligned titanium silicide process which combines the use of ion-beam mixing and rapid thermal processing (RTP) has been developed for CMOS VLSI applications. Shallow silicided junctions are formed by implanting dopants into silicide layers previously formed by ion-beam mixing with Si ions and low temperature annealing, and the subsequent drive-in of the implanted ions into the Si substrate during high temperature RTP. In addition, the formation of TiN on TiSi2 is achieved simultaneously during this process as a diffusion barrier for Al metallization. Short-channel MOS transistors with SALICIDE structure have been successfully fabricated and tested. Results of the impurity diffusion in silicide layer, the impurity segregation at both silicide/Si and oxide/silicide interfaces, contact stabilit of Al/TiN/TiSi2 structure, and device characteristics will be reported. Issues related to this process and its application to submicron device fabrication are discussed and foreseeable problem areas identified.

The Effects of Processing Ambient on the Reaction Rate of Ti and Si Using Rapid Thermal Processing

AbstractThe reaction rate of sputter deposited Ti films on c-Si as a function of process ambient was studied. Sintering temperatures ranging from 600 to 1100° C, under pure ammonia, forming gas, nitrogen and argon were used. The additional effect of a reactively sputtered TiN cap on the reaction rate was also investigated. Processed films were then analyzed using AES, RBS and four point probe resistivity mapping. It was found that for temperatures below 700° C, an ammonia ambient has the most pronounced effect on reducing the rate of formation of titanium silicide, followed by forming gas (N 2/H2 10% vol), nitrogen and argon. Additionally, the presence of the TiN cap further reduced the reaction rate while exhibiting significant diffusion of nitrogen into the silicide film. For the samples annealed in ambients containing nitrogen, a thin layer of Tix Ny was simultaneously formed on top of the silicide film. The thickness and Stoichiometry of this titanium nitride films were then correlated with the sintering temperature and ambient. The details of these findings and their impact on the formation of the self-aligned titanium silicide (salicide) will be presented.

Application of the self-aligned titanium silicide process to very large-scale integrated n-metal-oxide-semiconductor and complementary metal-oxide-semiconductor technologies

This paper reviews recent progress towards integrating the self-aligned titanium silicide process into VLSI NMOS and CMOS technologies, to simultaneously reduce the gate and junction sheet resistances to below 1 Ω/sq. In addition to reviewing the base line self-aligned TiSi2 process, the key issues that must be addressed if the process is going to be successfully integrated into a VLSI process flow, without having adverse effects on device parameters, will be discussed. Such issues are how the sheet resistance can be reduced to &amp;lt;1 Ω/sq without bridging between the gate and source/drain regions, the effect of silicide stress on gate oxide integrity, and how both P- and N-type junctions can be silicided without adversely affecting diode or transistor properties. Recent results on the hot electron hardness of silicided devices compared to unsilicided transistors will also be presented. The implementation of the self-aligned titanium silicide process using rapid thermal processing to simultaneously fabricate transistor gates and junctions with a sheet resistance of 1 Ω/sq will also be described. Using the self-aligned TiSi2 technology, fully functional VLSI CMOS and NMOS circuits of the 64K static random access memory class of complexity, with 1 μm gates, have been fabricated with yield that is similar to unsilicided parts.