Self-aligned Thin-film Transistors Research Articles

Engineering a Subnanometer Interface Tailoring Layer for Precise Hydrogen Incorporation and Defect Passivation for High-End Oxide Thin-Film Transistors.

Top-gate self-aligned structured oxide thin-film transistors (TFTs) are suitable for the backplanes of high-end displays because of their low parasitic capacitances. The gate insulator (GI) deposition process should be carefully designed to manufacture a highly stable, high-mobility oxide TFT, particularly for a top-gate structure. In this study, a nanometer-thick Al2O3 layer via plasma-enhanced atomic layer deposition (PE-ALD) is deposited on the top-gate bottom-contact structured oxide TFT as the interface tailoring layer, which can also act as the hydrogen barrier to modulate carrier generation from hydrogen incorporation into the active layer of the TFT during the following process such as postannealing. Al-doped InSnZnO (Al/ITZO) with an Al/In/Sn/Zn atomic ratio composition of 1.7:24.3:40:34 was used for high mobility oxide semiconductors, and an Al2O3/Si3N4 bilayer was used for the GI. The degradation issue due to the excellent barrier characteristics of Al2O3 and Si3N4 can be minimized. An oxide TFT fabricated without the interface tailoring layer exhibits conductor-like characteristics owing to the excessive carrier generation by hydrogen incorporation. However, TFTs with additional interface layers exhibit reasonable characteristics and distinct trends in electrical characteristics depending on the thicknesses of the interface layers. The optimized devices exhibit an average turn-on voltage (Von) of -0.31 V with 33.63 cm2/(V s) of high mobility and 0.09 V/dec of subthreshold swing value. The interfaces between the active layer and hydrogen barriers were investigated using a high-resolution transmission electron microscope, contact angle measurement, and secondary ion mass spectroscopy to reveal the origin of the trends in properties between the devices. The top-gate device with a hydrogen barrier using the four-cycle deposition exhibits optimum electrical characteristics of both high mobility and good stability with only a 0.04 V shift of Von under positive-bias temperature stress (PBTS). We realize a high-end, self-aligned TFT with high mobility [34.7 cm2/(V s)] and negligible Von shift of -0.06 V under PBTS by applying a subnanometer hydrogen barrier.

Monolithic Integration, Performance, and Comparison of Self-Aligned and Conventional IGZO Thin-Film Transistors on a Flexible Substrate

Flexible electronics, most prominently thin-film transistors (TFTs) on plastic substrates are considered the prime building block for the realization of innovative wearable systems. Two of the currently most successful fabrication processes of transistors on free standing polymer foils are large-area compatible devices structured by conventional UV lithography and high-speed transistors realized by self-alignment. Here, both processes, based on InGaZnO technology, are combined for the first time. This demonstrates their compatibility, but also showcases the differences between the resulting devices. Concerning the geometry, TFTs with the same nominal designed channel length of 1.5 μm, exhibit real channel length of 1.5 μm (self-aligned) and 4.5 μm (conventional). Furthermore, the integrated side by side fabrication enables the electrical comparison of both types of TFTs excluding external factors. While all TFTs exhibit similar threshold voltages around 0 V and excellent on/off ratios of ≈10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> , conventional TFTs are easier to fabricate, and have comparably higher mobilities up to 16 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . At the same time, self-aligned TFTs demonstrate better AC performance, demonstrating a maximum oscillation frequency of 216 MHz. This integration shows new possibilities for the realization of complex systems made from building blocks optimized for reliability and speed.

Remarkably stable high mobility self-aligned oxide TFT by investigating the effect of oxygen plasma time during PEALD of SiO2 gate insulator

Oxide thin-film transistors (TFTs) should be manufactured with high mobility and stability based on a self-aligned top-gate structure to drive high-end displays. In this study, the effect of oxygen plasma time over one cycle of plasma-enhanced atomic layer deposition (PEALD) SiO2 on the properties of top-gate oxide TFTs was investigated systemically. The subsurface reaction of oxygen plasma causes a difference in oxygen vacancy (Vo). In addition, hydrogen incorporation also differs according to plasma time. Considering Vo and hydrogen are donors, tendency of electric properties could be explained. These surface reactions and atomic incorporation also induce differences in the positive bias temperature stress (PBTS) stability. Based on oxygen plasma time of 2.0 s, a positive shift in threshold voltage (Vth) due to interfacial degradation was observed when the plasma was longer, while an abnormal negative shift due to H+ drift was observed when it was shorter. When the oxygen plasma time is 2.0 s, the TFT was free from the deterioration of the interface and SiO2. Based on this condition, a self-aligned TFT with superior performance including a high mobility of 31.1 cm2/Vs, positive Vth and high stability of 0.016 V shifting during the PBTS was fabricated successfully.

(Invited) Highly Reliable Metal Oxide Thin Film Transistors for Flexible Devices

Amorphous oxide semiconductors (AOS), such as amorphous InZnO (IZO), have been widely explored as channel material for thin-film transistors (TFTs) due to its high mobility (μ) and excellent uniformity.Its solution processability allows for application to cheap and flexible electronics. To achieve cheaper manufacturing cost and large-area production, successful integration of solution-based layers is necessary. In fact, other popular solution-based conductive films, such as carbon nanotubes and polymeric materials have been previously used as electrodes. However, their conductivity is generally lower and their integration requires complex processes. Meanwhile, AOS show promising optoeletronic properties as well as good contact with oxide channels. In this work, solution-based IZO semiconductor was functionalized for electrode applications using photo-assisted treatments, namely UV and excimer laser irradiation, and was employed in an all-solution oxide TFT fabrication.IZO functionalization was achieved through either UV (λ=254 nm) irradiation for 15 to 60 mins or with additional excimer laser (λ=248 nm) irradiation in vacuum, air, or N2 at a fluence from 100 to 140 mJ cm-2. The results of X-ray photoelectron spectroscopy O 1s analysis suggests oxygen vacancy generation which effectively increases the carrier concentration in the irradiated IZO film. Moreover, IZO was crystallized from the amorphous as-deposited film after irradiation as obtained from X-ray diffraction and scanning transmission electron microscopy analyses. The laser-induced heating likely caused the IZO crystallization which provided the enhanced charge transport in the oxide film. Finally, the metal-oxide functionalization was employed in an all-solution processed oxide TFT fabrication using IZO for the channel and the electrodes, and fluorinated polysiloxane for the gate insulator. The self-aligned TFT structure that was employed, enabled the selective functionalization of the IZO gate, source, and drain electrodes. The metal oxide functionalization using UV and excimer laser irradiation yielded oxide TFTs with excellent transfer characteristics and good stability even after three months of storage in air. The all-solution processed fabrication demonstrated in this work is relevant for high throughput fabrication such as roll-to-roll processing.

(Invited) Highly Reliable Metal Oxide Thin Film Transistors for Flexible Devices

Fully solution-processed amorphous InZnO (a-IZO) thin-film transistors (TFTs) were demonstrated utilizing solution-based channel, gate insulator, and electrodes with a maximum fabrication temperature of 300°C. Particularly, a single layer of a-IZO was used as both the channel and the source/drain electrode layer by selectively tuning the role of a-IZO as a semiconductor or a conductor through photo-assisted treatments. By employing a self-aligned TFT structure, the a-IZO electrodes were functionalized by UV irradiation and excimer laser annealing (ELA). The fully solution-processed a-IZO TFTs exhibited high performance with an average mobility of up to 38 cm2 V-1 s-1, which surpasses those of previously reported approaches for fully solution-processed oxide TFTs. Moreover, the overall device performance, including subthreshold swing of 225 mV dec-1 and on-voltage of -0.4 V, is comparable to those of vacuum-processed oxide TFTs.

Fabrication and AC Performance of Flexible Indium-Gallium-Zinc-Oxide Thin-Film Transistors

The internet of things or foldable phones call for a variety of flexible sensor conditioning and transceiver circuits. However, the realization of high-performance, large-area, and deformable analog circuits is limited by the materials and the processes compatible with mechanically flexible substrates. Among the different semiconductors, InGaZnO is one of the most promising materials to realize high-frequency flexible thin-film transistors (TFTs) and circuits. In this work, the effect of different geometries, including self-aligned, vertical, and double-gate structures on the AC behaviour of flexible IGZO TFTs is presented. All TFTs are based on Al2O3 insulating layers, InGaZnO semiconductor, and polyimide substrates. The presented TFTs exhibit state-of-the-art performance including a field-effect mobility up to 15 cm2/Vs and a mechanical bendability down to radii of 3.5 mm. Due to different trade-offs required in the fabrication, flexible IGZO TFTs with the shortest channel length of 160 nm do not exhibit the highest measured frequency, whereas exceptional maximum oscillation and transit frequencies of 304 MHz and 135 MHz are demonstrated for 500 nm long self-aligned TFTs. Such optimized transistors can be used to realize entirely flexible analog circuits leading towards imperceptible electronic systems.

Inkjet-Printed Self-Aligned Short-Channel Metal-Oxide Thin-Film Transistors Based on Coffee Stripe Dewetting Method

It is difficult to implement high-resolution layer-to-layer alignment by direct inkjet printing because of the limitation of position accuracy of the common inkjet printer. The poor alignment of conventional printers generally causes large parasitic overlap capacitances between the gate and source/drain (S/D) of thin-film transistors (TFTs), which degrades device operating speeds. In this paper, a self-aligned method was proposed to minimize the parasitic overlap capacitance. In this method, a hydrophobic fluoropolymers (Cytop) coffee stripe prepared by inkjet printing was utilized to define the gate electrodes, and to dewet deposited ink droplet for self-aligned S/D electrodes. This kind of inkjet-printed self-aligned TFTs with In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.95</sub> Sc <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.05</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> channel layer have a parasitic overlap capacitance as small as 0.31-0.45 pF. The TFTs in array exhibited an on/off ratio larger than 107 and a maximum saturation mobility of 4.63 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> .

Bottom-Gate Self-Aligned Homojunction TFT with Double Oxide Semiconducting Layers

After huge effort has been made over the last decade, oxide thin-film transistors (TFTs) have been successfully adopted in the backplane of high resolution AM-LCD and AM-OLED displays. However, as displays and electronic devices evolve to next generations, it is necessary to not only enhance field-effect mobility, but also reduce RC-delay for high driving speed [1, 2]. In this regard, self-aligned structure has been considered as one of promising candidates for satisfying these requirements [3] due to the minimum parasitic capacitances between electrodes. Nonetheless, there are several concerns especially in doping process at contact region because it is difficult to control dopant diffusion, resulting in unstable performance and another unexpected parasitic capacitance. Here, we propose improved structure adopting double oxide semiconducting layers, which can precisely define the channel dimension by gate electrode. Figure 1 demonstrates both structures of conventional self-aligned TFT and our improved self-aligned TFT. As shown in the figure, first channel layer of oxide material with high mobility and high carrier density plays as the real electron flow path and the contacts with source/drain (S/D) metal electrode without additional doping process. Consequently, the issues originated from doping process can be easily overcome. Meanwhile, second active layer with the relatively low carrier density is defined by the gate electrode and plays a role as a carrier controlling part for reliable switching performance. To fabricate our self-aligned TFTs, gate metal was firstly patterned on glass substrate by wet etching. After depositing SiO2 by PECVD as a gate insulator, first semiconducting layer was grown by sputter or plasma-enhanced atomic layer deposition (PEALD). The second active layer was deposited and formed by back-side exposure using gate electrode as a masking layer. Then, SiO2 by PECVD was deposited to passivate whole device. Finally, S/D metal layer was formed, followed by annealing process in vacuum condition. As a starting research, we had to carefully consider proper oxide semiconductors according to their characteristics and etch selectivity between first and second channel layers. Although adopting highly conducting oxides such as ITO and In2O3 as a first channel layer would be better for lowering the contact resistance, it is hard to deplete the carriers. Hence, thinner film thickness (<10nm) or other deposition method such as PEALD should be considered to obtain semiconducting behavior. Accordingly, we have firstly investigated the switching behavior of In2O3/ZnO double layered TFT by means of PEALD with bottom-gate coplanar structure. The In2O3/ZnO TFT shows mobility of 32 cm2/Vs with good bias stability as shown in Figure 2. The improved self-aligned TFTs were successfully fabricated and well-performed using sputtered ITO/IGZO and PEALD In2O3/ZnO. We will report the device characteristics and further investigate and reveal the origin of stable electrical behavior by simulation. [Acknowledgement] This work was supported by Open Innovation Lab Project from National Nanofab Center (NNFC). [Reference] [1] K. Yokoyama, S. Hirakata, S. Yamazaki, M. Nakada, T. Sato, and N. Goto, “A 2.78-in 1058-ppi ultra-high-resolution OLED display using CAAC-OS FETs,” SID digest 2015, 46, 1039-1042. [2] J. U. Bae, D. H. Kim, K. Kim, K. Jung, W. Shin, I. Kang, and S. D. Yeo, “Development of oxide TFT’s structures,” SID digest 2013, 44, 89-92. [3] N. Morosawa, Y. Ohshima, M. Morooka, T. Arai, and T. Sasaoka, “Novel self-aligned top-gate oxide TFT for AMOLED displays,” Journal of the society for Information Display 2012, 20 (1), 47-52. Figure 1

(Invited) Low-Temperature Processed and Self-Aligned InGaZnO Thin-Film Transistor with an Organic Gate Insulator for Flexible Device Applications

Recently, metal-oxide thin-film transistors (TFTs) have attracted considerable attention for use in next-generation flat panel displays. An amorphous InGaZnO (IGZO) semiconductor is widely accepted as a promising channel material for TFT applications owing to its outstanding electrical properties. Moreover, since oxide semiconductor can be deposited even at room temperature by sputtering, it is recognized as a promising material for flexible device applications. From the standpoint of flexible devices, an organic insulating material is a good candidate for gate insulator (GI) even for the oxide thin-film transistors (TFTs). In this presentation, a self-aligned and top-gated IGZO TFT with an organic gate insulator was demonstrated at a maximum processing temperature of 150 ºC. First, the controlling methods of the hybrid interface between the InGaZnO channel and the organic gate insulator were investigated. It was demonstrated that an organic protection layer of the IGZO channel and controlling the oxygen content in the IGZO channel are effective to achieve good performance TFTs at low processing temperature; however, it was also revealed that an excess oxygen acted as an electron trap existing at the IGZO/GI interface and degraded the TFT’s reliability. Second, carrier concentration in the IGZO was selectively controlled by helium plasma treatment with a substrate bias for source and drain (S/D) regions of self-aligned TFT. It was revealed that lateral diffusion from S/D extension to the IGZO channel was influenced by the doping methods. We achieved a self-aligned and top-gated IGZO TFT with an organic gate insulator that was fabricated at a maximum processing temperature of 150 ºC. Field effect mobility of over 10 cm2/Vs and subthreshold swing of below 0.2 V/dec. have been obtained. Details will be discussed at the conference.

Investigation of Carrier Generation Mechanism in Fluorine-Doped n+-In–Ga–Zn-O for Self-Aligned Thin-Film Transistors

We investigated the carrier generation mechanism in the stacked film of fluorinated silicon nitride $(\hbox{SiN}_{x}\hbox{:F})$ on InGaZnO $(\hbox{IGZO/SiN}_{x}\hbox{:F})$ through post-annealing and compared its mechanism to that of the $\hbox{SiO}_{x}$ stack $(\hbox{IGZO/SiO}_{x})$ . The resistivity $(\rho)$ and carrier concentration $(n)$ of two types of the stacked films through post-annealing were measured by the Hall measurement. The as-deposited $\hbox{n}^{+}$ a-IGZO film with the $\hbox{SiN}_{x}\\hbox{:F}$ stack showed $\rho$ of 3.3 $\times\hbox{ 10} ^{-3}~\Omega\cdot\hbox{cm}$ and $n$ of 1.0 $\times \hbox{ 10} ^{20}~\hbox{cm}^{-3}$ , which was approximately one order of magnitude higher than that with the $\hbox{SiO}_{x}$ stack. X-ray photoelectron spectroscopy (XPS) analyses indicated that ${\rm V}_{\rm O}$ defect was the main source of free electrons in both of the as-deposited $\hbox{IGZO/SiO}_{x}$ and $\hbox{IGZO/SiN}_{x}\hbox{:F}$ stacks. After post-annealing at 300 $^{\circ}\hbox{C}$ , the carrier generation mechanism in the $\hbox{IGZO/SiN}_{x}\hbox{:F}$ stack changed from defects related to ${\rm V}_{\rm O}$ to the fluorine doping. XPS depth profile analyses also revealed that fluorine in IGZO film passivated ${\rm V}_{\rm O}$ and substituted metal–oxygen to thermally stable metal–fluorine (M-F) bonds simultaneously. As a consequence, the thermal stability of $n$ in the $\hbox{IGZO/SiN}_{x}\hbox{:F}$ stack drastically improved, as compared with that in the $\hbox{IGZO/SiO}_{x}$ stack. Therefore, we consider that this fluorine doping method in IGZO is suitable for achieving self-aligned thin-film transistors to improve operation speed of system-in-display.

Self-Aligned Coplanar Top Gate In-Ga-ZnO Thin-Film Transistors Exposed to Various DUV Irradiation Energies

Self-aligned coplanar top gate indium–gallium–zinc-oxide thin-film transistors (TFTs), with source/drain (S/D) regions that were heavily doped by various deep-ultraviolet (DUV) irradiation energies at dual wavelengths of 185 and 254 nm, were investigated. The electrical performances of TFTs improved as the DUV irradiation energy increased. The proposed TFTs, with DUV irradiation of 20 J/cm2, have a field-effect mobility of 22.0 cm2/ $\text {V}\cdot \text {s}$ , a threshold voltage of 2.2 V, a subthreshold swing value of 0.24 V/decade, and an on/off current ratio of $1.34 \times 10^{6}$ . In addition, the channel length modulation ( $\Delta L$ ) and the width-normalized contact resistance ( $R_{\mathrm {SD}}W$ ) were 1.04 $\mu \text{m}$ and 60.5 $\Omega \cdot \text {cm}$ , respectively. Such short $\Delta L$ and low $R_{\mathrm {\mathbf {SD}}}W$ values indicate that the S/D regions were properly formed by the DUV irradiation. This simple and cost-effective doping technique can be useful for the fabrication of self-aligned TFTs.

Thermal Sensor Using Poly-Si Thin-Film Transistors With Self-Aligned and Offset Gate Structures

We propose a thermal sensor using poly-Si thin-film transistors (TFTs) with self-aligned and offset gate structures. First, the temperature dependences of the transistor characteristic are compared between the self-aligned and offset TFTs. It is found that both the TFTs have the temperature dependence of the off-leakage current, whereas the off-leakage current of the self-aligned TFT is larger than that of the offset TFT. Next, the self-aligned and offset TFTs are included in a cell circuit to detect the temperature utilizing the off-leakage current, which is composed of a pair of 1-transistor and 1-capacitor. It is found that low and high temperatures can be detected using the self-aligned and offset TFTs, respectively. We think that it is promising to integrate this thermal sensor in certain applications using TFTs.

Self-Aligned Coplanar a-IGZO TFTs and Application to High-Speed Circuits

We report a self-aligned coplanar amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) using an a-IGZO/SiO2 stack layer. From the channel-length dependence of the total resistance for the TFTs, the channel and parasitic resistances were found to be 8.4 kΩ/μm and 9.7 kΩ/sq, respectively. The fabricated a-IGZO TFT exhibits field-effect mobility of 23.3 cm2/V ·s, threshold voltage of 3.6 V, and gate voltage swing of 203 mV/dec. A 23-stage ring oscillator made of the self-aligned TFTs exhibits a propagation delay time of 17 ns/stage at a supply voltage of 22 V.

Fabrication of self-aligned TFTs with a ultra-low temperature polycrystalline silicon process on metal foils

We have fabricated self-aligned thin-film transistors (TFTs) using a ultra-low temperature ( T < 200 °C) polycrystalline silicon process on stainless steel foil substrates. The overall processing scheme and technical details were discussed from the viewpoint of electrical and mechanical stabilities. Large grain poly-Si films were obtained with sequential lateral solidification (SLS) method. Plasma enhanced atomic layer deposition (PEALD) method was used to form Al 2O 3 gate dielectric films. The TFT performances were enhanced by plasma oxidation of the polycrystalline Si surface prior to Al 2O 3 gate dielectric film deposition. The fabricated TFT showed a field effect mobility of 95 cm 2/Vs, a threshold voltage of −3 V and a sub-threshold swing of 0.45 V/dec.

Mechanism Analysis of Off-Leakage Current in Poly-Si TFTs with LDD Structure

We have analyzed the mechanism of off-leakage current in a lightly doped drain (LDD) poly-Si thin film transistor (TFT) structure using a two-dimensional device simulation and by evaluating the temperature dependence. The off-leakage current in the self-aligned TFTs is mainly caused by band-to-band tunneling, and the off-leakage current in the LDD TFTs is mainly caused by phonon-assisted tunneling with the Poole-Frenkel effect. The carrier generation mostly occurs near the intersection of the front-insulator interface and the interface between the LDD and drain regions because both the electron and hole densities are simultaneously low and the electric field is strong.

Self-Aligned Top-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

Self-aligned techniques are often used in conventional CMOS and Si-based thin-film transistors (TFTs) technologies due to various merits. In this paper, we report self-aligned coplanar top-gate InGaZnO TFTs using PECVD a-SiNinfin:H patterned to have low hydrogen content in the channel region and high hydrogen content in the source/drain region. After annealing to induce hydrogen diffusion from a-SiNinfin:H into the oxide semiconductor, the source-drain regions become more conductive and yet the channel region remains suitable for TFT operation, yielding a working self-aligned TFT structure. Such fabrication involves neither back-side exposure nor ion implantation, and thus may be compatible with the typical and cost-effective TFT manufacturing.

Self-Aligned Nanocrystalline Silicon Thin-Film Transistor With Deposited n+ Source/Drain Layer

AbstractWe demonstrated self-aligned nanocrystalline silicon (nc-Si:H) n-channel thin film transistors (TFTs) with directly deposited n+ layer. The silicon layers were deposited by plasma-enhanced chemical vapor deposition at a substrate temperature of 150°C. The TFTs were made in a staggered top-gate, bottom-source/drain geometry with a seed layer underneath. The self-alignment of top-gate to the bottom-source/drain was achieved by backside exposure photolithography through the glass substrate and the silicon layers, followed by a lift-off process. An extent of gate to source/drain overlap of 1.5 mm was obtained. The self-aligned TFTs have similar characteristics to their non-self-aligned counterpart. This result represents an important step toward directly deposited nc-Si:H TFT backplanes on plastic substrates.

Self-aligned Thin Film Transistor Fabrication with an Ultra Low Temperature Polycrystalline Silicon Process on a Benzocyclobutene Planarized Stainless Steel Foil Substrate

AbstractCompared to plastic, from the view point of ultra low temperature poly-Si (ULTPS) processes for realizing flexible active matrix organic light emitting diode (AM-OLED) display, SSF offers high thermal resistance and chemical stability, and lithography stability. As SSF is stiffer than plastic film, SSF is expected to reduce stress which originates from difference in coefficient of thermal expansion. However, SSF substrate itself also bears surface roughness problem, which necessitates an appropriate planarization step. Also to fully integrate both the drive circuits and the pixel thin-film transistor(TFT)s in a monolithic complementary metal-oxide-semiconductor (CMOS) technology high mobility is required, calling for poly-Si usage.We will deal with the planarization process, and then address various processing issues. Especially, we will demonstrate our successful SLS of Si on SSF substrates. Finally we show the device performances. All fabrication temperatures were kept below 200 oC to meet a ULTPS process.Due to the rolling process for manufacturing foils, the SSF surface is rough. We have measured average roughness of 500 nm, respectively. With benzocyclobutene (BCB), we have successfully planarized the surface with average roughness was less than 0.5 nm.Our TFT's active layer was obtained by laser crystallizing amorphous Si (a-Si) films. To obtain a high quality gate dielectric film, we formed a SiO2 film using an O2 plasma treatment on the surface of the poly-Si film and then deposited Al2O3 film by plasma enhanced atomic layer deposition. Then gate metal was deposited and patterned. Source and drain regions were p+ doped by ion implantation to form a self-aligned gate structure. We have used SiNx film as interlayer dielectrics.Briefly we discuss a practical approach for realizing SLS on a SiO2 buffer. The Si-on-SiO2 layer stacking is energetically unstable. Should have not controlled the heat during laser crystallization, liquid Si would recede to expose the SiO2 layer. Dewetting is suppressed by adjusting the buffer density, and densifying the a-Si film. To implement the SLS, we have optimally conjugated the densities of the buffer film and the a-Si film to produce Si grains with sizes of ~6 ¥ìm on a BCB planarized SSF.Our p-channel TFT transfer performance exhibits a field effect mobility (¥ì) of 95 cm2/Vs, a threshold voltage (Vt) of -3 V and a sub-threshold swing(S-S) of 0.5 V/dec.. The off-current level is ~ 10 pA at drain voltage (Vd) of -1V and the Ion/Ioff is 106 . Especially our stable Vt consents to the electrical stability for driving displays. This feature might be attributed to the improved interface between the active layer and the gate dielectrics by plasma oxidation.

Improved electrical stability in asymmetric fingered polysilicon thin film transistors

Recently, we proposed asymmetric fingered polysilicon thin film transistors, where the transistor channel region is split into two zones with different lengths separated by a floating n + region, which allows an effective reduction of the kink effect. In this work, we analysed the experimental electrical characteristics by using numerical simulations for a specific channel configuration and then we studied the effects of prolonged bias stress on these devices and conventional non self-aligned thin film transistors. We found that asymmetric fingered transistors are characterized by a substantial reduction of the transconductance degradation induced by hot carrier effect, if compared to conventional thin film transistors. By modeling the device with two transistor in series, we could explain the reduced effects of hot carrier-induced degradation.

High-Performance Polycrystalline Silicon Thin-Film Transistors Fabricated by High-Temperature Process with Excimer Laser Annealing

Polycrystalline silicon (p-Si) thin-film transistors (TFTs) were fabricated using a high-temperature process that included solid-phase crystallization (SPC) and dry thermal oxidation with excimer laser annealing (ELA). X-ray diffraction and transmission electron microscopy analyses showed that the ELA process improved the quality of p-Si films markedly. The p-Si TFTs exhibited a higher performance than the SPC and a-Si+ELA p-Si TFTs. The field-effect mobility for n-type self-aligned TFTs was 251 cm2·V-1·s-1. The longitudinal junction diffusion length of the p-Si TFTs was shorter than that of the SPC p-Si TFTs. This is favorable for fine design rules. This fabrication process is consistent with the high-temperature-processed p-Si TFT development trend towards using large substrates, low temperatures, and fine design rules.