Self-aligned Technology Research Articles

Noise parameters of InP-based double heterojunction base-collector self-aligned bipolar transistors

The noise performances of a new base-collector self-aligned technology of double-heterojunction single-finger InGaAs-InP bipolar transistor are investigated at 300 K. Noise parameter variations are studied versus frequency in the 2-18 GHz range, versus collector current and emitter area. A low minimum noise figure F/sub min/=0.6 dB is demonstrated at 2 GHz with a 4.8-/spl mu/m/sup 2/ emitter. Variations of F/sub min/ show a minimum versus collector current. The high cutoff frequencies of the devices limit the increase of F/sub min/ versus frequency.

Reduction of the Floating Body Effect in SOI MOSFETs by Using Schottky Source/Drain Contacts

A new silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI MOSFET) structure, which employs the Schottky contacts at the source/drain, is proposed to suppress the floating-body effect. Using a Schottky contact, excess holes in the channel region are smoothly absorbed into the source and the impact ionization near the drain is reduced due to the built-in field. Analysis with two-dimensional simulation verifies these effects. As a result, the early drain breakdown of the SOI MOSFET is suppressed. A test device fabricated using Er silicide self-aligned technology proves the technical feasibility of the proposed device.

A Fully Self-Aligned Amorphous Silicon Tft Technology for Large Area Image Sensors and Active-Matrix Displays

ABSTRACTWe have developed a fully self-aligned amorphous silicon TFT technology, which is suitable for large area image sensors and active matrix displays. Self-alignment is achieved by defining the top nitride by back exposure and then forming source and drain contacts by ionimplantation and silicidation. We incorporate a low resistance gate metallisation process, by using Al metal, capped by Cr. We have compared the process of forming the silicide after the ion-implantation step, with a new process of forming the silicide first and then implanting through the formed silicide. We find a significant advantage to the latter method, where we can achieve a higher doping level and reduced contact resistance. We have therefore optimised our process based on this method. Transistor characteristics as a function of channel length for both methods show the improved contact resistance, obtained with the latter method. We obtain field effect mobilities of 0.7cm2V−1s−1, measured in the saturated region, for a channel length of 8μm.

Feasibility of Fabricating a Modified Volcano-Shaped Field Emitter

We fabricate modified volcano-shaped field emission arrays (MVSFEAs) using one photomask process and self-aligned technology. Because the enhanced electric field at the tips causes a larger value of β, the resulting onset voltage is lower and the emission current is higher for MVSFEA than for conventional FEA. According to our results, the emission current density at a gate voltage of 380 V is 8.64×106 A/cm2 and emits about 58 nA/tip when the radius of the volcano aperture, a, is equal to 0.75 µ m. The emission current density of MVSFEAs for a=0.75 µ m is 37.9-fold larger in magnitude than that of a=0 µ m owing to the larger value of β for MVSFEAs.

Gas flow effects on precision solder self-alignment

Self-aligning soldering technology is being developed for low cost, passive, precision optical alignments. To avoid contamination problems, the solder reflow process must use reacting or inert gas instead of chemical flux materials. Since the accuracy of these optical alignments should reach the range of a few micrometers (/spl mu/m), the gas flow may affect the aligning process. Therefore, the effects of the gas flow on the self-aligning process must be understood. The experiments described show that gas flow effects do exist. The top plate, 8.4 mm/spl times/8.4 mm, can be moved by the gas flow by as much as 4.5 /spl mu/m and 7.8 /spl mu/m at gas flow rates of 2.5 L/min and 5.0 L/min, respectively. The numerical analysis in this study models the gas flow effects for a wide range of chip sizes, solder geometry, and gas flow direction. In the numerical analysis, fluid computation and solder force calculation are conducted to study the gas flow effects on chip displacement that is the distance away from the well aligned position along the gas flow direction. The results show that the gas flow effects are related to many factors including chip size, gas flow rate, solder height, and flow direction. For a one-dimensional (1-D) laser array, these effects are negligible because the chip size is very small. However, for a chip larger than 5 mm/spl times/5 mm, the effects should be controlled for micron-level precision alignment.

Low-resistance self-aligned Ti-silicide technology for sub-quarter micron CMOS devices

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-/spl mu/m CMOS devices with low-resistance and uniform TiSi/sub 2/ on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi/sub 2/ films were achieved on all narrow, long n/sup +/ and p/sup +/ poly-Si and diffusion layers of 0.15-/spl mu/m CMOS devices. TiSi/sub 2/ films with a sheet resistance of 5 to 7 /spl Omega//sq were stably and uniformly formed on 0.15-/spl mu/m-wide n/sup +/ and p/sup +/ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi/sub 2/ films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-/spl mu/m NMOSFET's and PMOSFET's with self-aligned TiSi/sub 2/ films.

46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz static frequency divider in silicon bipolar technology

High-speed multiplexers, demultiplexers, and static frequency dividers are key electronic components in future optical broadband communication systems. In this paper we present a 50 Gb/s multiplexer, a 46 Gb/s demultiplexer, and a 30 GHz static frequency divider. The IC's were fabricated in a self-aligning double-polysilicon bipolar technology using state-of-the-art production process modules. The achieved results are record speeds not only for silicon, but, except for the static divider, for all semiconductor technologies. The high performance of this chipset shows that circuits in silicon bipolar technology will play an important role in future multigigabit-per-second fiber-optic communication systems, at data rates of 20 Gb/s or even at 40 Gb/s.

A novel 3-D integrated HFET/RTD frequency multiplier

A merged heterostructure field-effect transistor/resonant tunneling diode (HFET/RTD) combination is proposed to act as a (sub)millimeter wave source via highly efficient frequency multiplication and its functionality is demonstrated at intermediate frequency. On a semi-insulating InP-substrate a HFET followed by a double barrier RTD-layer sequence is grown in a single molecular beam epitaxy (MBE)-run. A novel monolithic frequency multiplier circuitry is developed where the RTD is used as load in contrast to other concepts where the RTD is inserted in the input of a three-terminal device. The resulting output voltage is rectangular type and rich in higher odd harmonics. This approach avoids classical disadvantages of the RTD because biasing in the negative-differential-regime is not required and bistability of the I-V-characteristic is used rather than the negative differential resistance. The small signal parameters of the single devices realized with optical lithography, wet etching, and self-aligned process technology are used as input data for a microwave design software (MDS) and the frequency multiplication is modeled up to submillimeter wave frequencies.

A lightly doped deep drain GaAs MESFET structure for linear amplifiers of personal handy-phone systems

An improved GaAs MESFET structure, named a buried p-layer lightly doped deep drain (BP-LD3) structure, is proposed. This structure can be fabricated by the conventional self-aligned gate and selective ion implantation technologies, and the FET characteristics show a high transconductance, a high breakdown voltage, and a low drain-source resistance. The lightly doped deep drain characterizing this structure was introduced on the basis of a two-dimensional numerical analysis including an impact ionization for a buried p-layer lightly doped drain (BP-LDD) structure which has been applied for high-speed digital ICs. The simulated results clarified that a low breakdown voltage of the BP-LDD structure originates from a high rate of carrier generation due to the impact ionization in the lightly doped drain region. The reason is that both electric field and current density become high in the region. In the new BP-LD3 structure, the electron current expands due to the deep formation of lightly doped drain, therefore impact ionization is reduced. This BP-LD3 structure was fabricated and the FET characteristics were compared with those of the conventional BP-LDD structure, and a structure which is now being studied for linear amplifiers of 1.9 GHz personal handy-phone systems. The measured breakdown voltage of 8.1 V, transconductance of 360 mS/mm, and drain-source resistance of 2.5 /spl Omega//mm for the BP-LD3 structure indicate high potentiality for analog applications.

Novel WSi/Au T-shaped gate GaAs metal–semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

A fully ion-implanted self-aligned T-shaped gate GaAs metal–semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier with an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology.

A high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications

A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 /spl mu/m design rules (0.5 /spl mu/m as one nesting tolerance) has achieved f/sub l/ and f/sub max/ for npn bipolar (A/sub e/=1/spl times/2 /spl mu/m/sup 2/) of 23 GHz and 24 GHz at V/sub ce/=3 V, respectively, with BV/sub ceospl ges/5.5 volts, and /spl beta/V/sub A/ product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (A/sub e/=1/spl times/2 /spl mu/m/sup 2/; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 /spl Aring/, L/sub eff/=0.6 /spl mu/m; V/sub th,nch/=0.45 V; V/sub th,pch/=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 /spl mu/m; gate L/sub eff/=0.7 /spl mu/m) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Silicon Etching in Rapid Thermal Chemical Vapor Deposition of Tisi2

AbstractDownscaling of microelectronics devices into the deep submicron regime requires ultrashallow junctions with reliable, low-resistivity contacts. The conventional self-aligned TiSi2 technology exhibits a serious limitation in forming contacts to ultra-shallow junctions due to silicon substrate consumption. Selective chemical vapor deposition of TiSi2 is being investigated because of its potential for overcoming this difficulty. In this process Si and Ti are supplied from the gas phase. The standard source gas for Ti has been TiCl4 while several gases including SiH4, Si2H6 and SiH2Cl2 are available for Si. The reports on this process indicate that optimized process conditions can deliver TiSi2 films without substrate consumption. Although this promise is significant, the deposition has a complicated chemistry involving processes such as silicon etching, silicon consumption or silicon pedestal deposition taking place along with TiSi2 deposition. Although, suppression of Si-substrate etching by excess H2 has been reported previously, a broad quantitative analysis has been lacking up until this reporting. In this work, we have examined silicon etching trends as a function of temperature for different H2:TiCl4 flow ratios using thermodynamic equilibrium calculations. We have also performed experiments in a lamp heated rapid thermal chemical vapor deposition reactor to study substrate etching over the temperature range of 600°C to 800°C and for H2 flows from 0 to 1000 sccm. A silicon conversion efficiency is defined as a measure of the amount of Si converted to TiSi2 relative to total Si used from the substrate and it is evaluated via both thermodynamic calculations and experiments with good agreement between the two. Our calculations suggest that at high temperatures, etching occurs mainly via formation of SiCl2. Addition of H2 into the reaction chemistry encourages formation of HCl reducing the amount of Cl available for SiCl2 formation responsible for substrate etching. Our results show that by optimizing the H2 flow rate and the process temperature silicon substrate etching can be effectively suppressed.

Manufacturability Issues for Application of Silicides In 0.25 μm CMOS Process and Beyond

AbstractKey issues associated with the self-aligned silicide technology, such as formation of silicides on narrow poly gate, shallow silicided junction formation, gate to source/drain bridging, and interface contact resistance, are discussed. The comparison of important technological aspects for TiSi2 and CoSi2 is presented. The emphasis of this work is focused on the CoSi2 salicide technology with different variations, namely conventional process, Co/Ti capping process, and Ti/Co process. Based on the experimental results, CoSi2 should be considered as an attractive alternative to TiSi2 for the applications in sub-0.25 μm ULSI integrated circuits.

GaInP/GaAs heterojunction bipolar transistors grown by low pressure metalorganic chemical vapour deposition for voltage-controlled oscillators and power amplifier microwave monolithic integrated circuits

This paper reports the first GaInP/GaAs voltage-controlled oscillators (VCOs) and power amplifier heterojunction bipolar transistor (HBT) microwave monolithic integrated circuits (MMICs) grown by low pressure metalorganic chemical vapour deposition. A self-aligned technology was developed for the fabrication of such MMIC circuits. Small signal S parameter measurements carried out from 0.5 to 45 GHz on a single 2 × 30 μ m 2 emitter finger HBT exhibited an f t and f max of 60 and 120 GHz. The VCO circuits integrate HBTs and varactor diodes and they operate at 14 and 28 GHz with tuning bandwidths ranging from 10.7% to 19.6%. Two-stage power amplifier MMICs have been fabricated using one eight-finger HBT in the first stage and two twelve-finger HBTs in parallel in the second stage. The output power of this amplifier is higher than 1 W with a power gain of 14 dB at 10 GHz.

Studies of the promising material CoSi2 on GaAs substrates

The thermal stability of CoSi2 thin films on GaAs substrates has been studied using a variety of techniques. The CoSi2 thin films were formed by depositing Co(500 A) and Si(1800 A) layers on GaAs substrates by electron-beam evaporation followed by annealing processes, where the Si inter-layer was used as a diffusion/reaction barrier at the interface. The resistivity of CoSi2 thin films formed is about 30 μΩ cm. The Schottky barrier height of CoSi2/n-GaAs is 0.76 eV and the ideality factor is 1.14 after annealing at 750° C for 30 min. The CoSi2/GaAs interface is determined to be thermally stable and the thin film morphologically uniform on GaAs after 900° C/30 s anneal. The CoSi2 thin films fulfill the requirements in GaAs self-aligned gate technology.

Monte-Carlo simulation of the dynamic behavior of a CMOS inverter struck by a heavy ion

We present a theoretical study using Monte-Carlo simulation of the behavior of a CMOS inverter struck by an ionizing particle. The inverter is made of two complementary enhancement-mode MOSFETs according to a SIMOX self-aligned technology with an effective gate length of 0.35 /spl mu/m. The effect of the ionizing particle (heavy ion) is simulated by electron-hole pairs generation with an energy of 1 eV for each carrier. We studied the return to the steady-state of the device after a transient irradiation. Either the P-channel transistor or the N-channel transistor is irradiated, and the gate operating is considered in both cases of 0 V and 5 V input voltage. The irradiation of the off-state transistors induces a significant transient variation of the output voltage whereas irradiation of the on-state transistors has weak effects on the output. The return to the stationary regime, which is reached after about 50 ps in all irradiation cases, is achieved by evacuation of the carriers in excess through the different electrodes without trapping effect in the device. >

High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology

We have designed and fabricated a high-bit-rate, high-input-sensitivity decision circuit for future optical communication systems using an advanced super self-aligned Si bipolar process technology (SST-1C). The SST-1C transistors are fabricated by 0.5-/spl mu/m photolithography. The peak cut-off frequency of a typical transistor is 31 GHz at a collector-emitter voltage of 3 V. The circuit design involves the optimization of individual transistor sizes to boost the speed and the adoption of a wide-band preamplifier to enhance input sensitivity. The circuit operates at up to 15 Gb/s with an input sensitivity of 40 mV/sub p-p/. An extremely high input sensitivity of 15 mV/sub p-p/ and a wide phase margin of 260/spl deg/ at 10 Gb/s are achieved. >

Precise analog synapse for Kohonen feature maps

A plastic medium-term analog synapse is presented that fulfils the stringent specifications necessary for the Kohonen algorithm. The principle is based on a switched capacitor-like technique implementing a variable time-constant integrator. The memory leakage standard deviation is 2 mV/s for a voltage range of 2 V at room temperature and the learning gain can be varied over two decades. Its differential structure leads to good CMRR, PSRR, and charge injection cancellation. The total synapse area is 1/16 mm/sup 2/ using a 3-/spl mu/m self-aligned contact single-metal CMOS technology. Measurement results of a test chip are also presented. >

An ultra-high-speed ECL-BiCMOS technology with silicon fillet self-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 /spl mu/m gate and 50 ps on 0.6 /spl mu/m gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 /spl mu/m emitter ring oscillators with collector current density of 40 kA/cm/sup 2/. A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology. >

A-Si TFT Technologies for AM-LCDS

AbstractA technical trend for a-Si TFTs is their application to large-size, high-pixel density AMLCDs such as XGA, EWS, and HDTV. In order to realize these LCDs, the TFT device characteristics must be improved. Future technologies, which will be necessary to fabricate TFTs with improved characteristics are as follows,(1) Fully self-aligned TFT technology: A SA-TFT structure reduces the feedthrough voltage caused by parasitic capacitance due to gate/source overlap. This results in an improved picture quality and a higher aperture ratio. Fabrication of such a structure would require ion doping technology.(2) Ion doping technology: This non-mass-separated implantation technique has large area doping capability and much higher doping speed compared to conventional ion implantation technique. The major problems with the ion doping technique is the implantation of unwanted species which deteriorate the quality of source/drain and channel regions of TFTs.