Self-aligned Polysilicon Emitter Research Articles

Dopant Redistribution during Rapid Thermal Annealing in a Self-Aligned Polysilicon Emitter Bipolar Structure Compatible with a Complementary Metal-Oxide-Semiconductor Technology

Arsenic and boron concentration profiles, diffused from polycrystalline silicon (polysilicon) into an underlying single crystalline silicon, are analyzed by secondary ion mass spectrometry. This bilayer is the basic structure of a self-aligned bipolar transistor, compatible with a complementary metal-oxide-semiconductor; arsenic and boron codiffusions are studied in an emitter and extrinsic base configuration of bipolar transistors. Rapid thermal annealings are performed to obtain shallow junctions, with temperature and annealing plateau duration as parameters. Finally, the codiffusion process is investigated using simulations. It indicates that diffusion of the dopant at the lowest fluence is slowed, much more because of the in-depth inhomogeneous grain growth induced by amorphization and annealing, than a built-in electric field. Then, it should be assumed that the dopant at the highest dose saturates the grain boundary traps. This hypothesis concerns essentially arsenic, but also boron, to a less extent.

Characteristics of impact-ionization current in the advanced self-aligned polysilicon-emitter bipolar transistor

Using an algorithm to calculate the base current increase due to local thermal effects, the authors show that one can accurately measure the impact ionization current over the full range of collector current. From the measured impact ionization ratio, it was possible to quantitatively describe the characteristics of the space-charge modulation and base push-out effect over a wide range of collector current. Computer simulation results support the measured data. It is also shown that one can use the measured impact ionization ratio to distinguish small collector concentration variations and thickness differences. The characterization was performed for self-aligned polysilicon-emitter transistors in an advanced BiCMOS technology. >

Efficient two-dimensional multilayer process simulation of advanced bipolar devices

In order to study advanced bipolar transistors including several polysilicon layers and U-groove isolation, a dedicated two-dimensional multilayer process simulator, IMPACT4, has been developed. From the simulation point of view, the new aspects introduced by these devices, namely the multilayer and non planar characteristics, are carefully taken into account by the program. Especially, the algorithmic procedure solving the dopant redistribution at interfaces is discussed. The application to a self-aligned polysilicon emitter bipolar transistor is presented. Intrinsic and extrinsic bases formation has been studied, it has been demonstrated that the segregation phenomenon greatly affects bases connection. Typical 2-D effects induced by the walled emitter configuration, such as lateral base thinning are also detailed.

Informed device design and gain-speed trade-off for self-aligned polysilicon-emitter transistors

A theoretical polysilicon contact with and without an interfacial layer has been optimized relative to the dopant concentration and thickness of the polysilicon layer, the underlying emitter profile, and, when necessary, transport parameters for the interfacial layer. The numerical computer simulation that is used for this optimization procedure has been demonstrated (in a previous paper) to be valid for accurately predicting the measured characteristics of extended-emitter polysilicon contacts. The optimization here focuses on defining contacts with the lowest surface recombination velocity and the lowest contact resistance. For transistors with optimized contacts, emitter efficiency is then traded-off for higher base dopant concentration and lower base sheet resistance. For transistors with shallow junctions (⩽2000 Å), the optimized polysilicon contacts are demonstrated to have emitter quasi-static delays, associated with f T, that are greater than the base delays. The transistor with a contact, acting like an extension of the original emitter, is demonstrated to have lower quasi-static delays than the one having a contact with the optimized interfacial layer. However, when considered relative to the scale-down for the ECL gate and its delay, the transistor with the latter contact is shown to have an advantage, because of the trade-off between emitter efficiency and base sheet resistance.

Modeling hot-carrier effects in polysilicon emitter bipolar transistors

In self-aligned polysilicon emitter transistors a large electric field existing at the periphery of the emitter-base junction under reverse bias can create hot-carrier-induced degradation. The degradation of polysilicon emitter transistor gain under DC stress conditions can be modelled by Delta I/sub B/ varies as I/sub R//sup m+n/t/sup n/ where n approximately=0.5 and m approximately=0.5. The more complex relationships of Delta beta (I/sub C/, I/sub R/, t) and beta (I/sub C/, I/sub R/, t) result naturally from the simple Delta I/sub B/ model. Using these relationships the device lifetime can be extrapolated over a wide range of reverse stress currents for a given technology. >

A Model for Dopant Pile-Up at the Interface in a Self-Aligned Polysilicon-Emitter Process

ABSTRACTA model for dopant pile-up in conjunction with a self-aligned polysilicon-emitter process model is presented that accurately predicts the total dopant profiles of the polysilicon layer, the interfacial pile-up and the underlying emitter, taken from SIMS measurements. The pile-up model assumes that, after the dopant is implanted into the polysilicon layer and instantaneously redistributes there during the anneal, the dopant diffuses from its polysilicon source into the interfacial and underlying base region. In the disordered interfacial region, the dopant transport occurs by hopping, with a, certain fraction of dopant sticking in vacant sites. The model for dopant pile-up is implemented into SUPREM III. As further support, device simulations, using the respective electrically active dopant profiles, are found to be in good agreement with measurements on self-aligned phosphorus-implanted transistors.