Informed device design and gain-speed trade-off for self-aligned polysilicon-emitter transistors

Abstract

A theoretical polysilicon contact with and without an interfacial layer has been optimized relative to the dopant concentration and thickness of the polysilicon layer, the underlying emitter profile, and, when necessary, transport parameters for the interfacial layer. The numerical computer simulation that is used for this optimization procedure has been demonstrated (in a previous paper) to be valid for accurately predicting the measured characteristics of extended-emitter polysilicon contacts. The optimization here focuses on defining contacts with the lowest surface recombination velocity and the lowest contact resistance. For transistors with optimized contacts, emitter efficiency is then traded-off for higher base dopant concentration and lower base sheet resistance. For transistors with shallow junctions (⩽2000 Å), the optimized polysilicon contacts are demonstrated to have emitter quasi-static delays, associated with f T, that are greater than the base delays. The transistor with a contact, acting like an extension of the original emitter, is demonstrated to have lower quasi-static delays than the one having a contact with the optimized interfacial layer. However, when considered relative to the scale-down for the ECL gate and its delay, the transistor with the latter contact is shown to have an advantage, because of the trade-off between emitter efficiency and base sheet resistance.