A Model for Dopant Pile-Up at the Interface in a Self-Aligned Polysilicon-Emitter Process

Abstract

ABSTRACTA model for dopant pile-up in conjunction with a self-aligned polysilicon-emitter process model is presented that accurately predicts the total dopant profiles of the polysilicon layer, the interfacial pile-up and the underlying emitter, taken from SIMS measurements. The pile-up model assumes that, after the dopant is implanted into the polysilicon layer and instantaneously redistributes there during the anneal, the dopant diffuses from its polysilicon source into the interfacial and underlying base region. In the disordered interfacial region, the dopant transport occurs by hopping, with a, certain fraction of dopant sticking in vacant sites. The model for dopant pile-up is implemented into SUPREM III. As further support, device simulations, using the respective electrically active dopant profiles, are found to be in good agreement with measurements on self-aligned phosphorus-implanted transistors.