Self-aligned Manner Research Articles

Demultiplexing of 168-Gb/s data pulses with a hybrid-integrated symmetric Mach-Zehnder all-optical switch

We have developed a hybrid-integrated symmetric Mach-Zehnder all-optical switch and evaluated the demultiplexing of 168-Gb/s data pulses at a repetition rate of 10 GHz with this switch. A compact, stable device was realized by assembling semiconductor optical amplifiers as nonlinear waveguides on a planar lightwave circuit in a self-aligned manner. A 6.0-ps switching window needed for 168-Gb/s demultiplexing was provided by the push-pull operation of the symmetric Mach-Zehnder all-optical switch. Demultiplexed signal light showed a high extinction ratio of better than 18 dB. Error-free demultiplexing with a bit error rate of 10/sup -11/ was achieved.

A selective-epitaxial-growth SiGe-base HBT with SMI electrodes featuring 9.3-ps ECL-gate delay

An ultra-high-speed selective-epitaxial-growth SiGe-base heterojunction bipolar transistor (HBT) with self-aligned stacked metal/in-situ doped poly-Si (IDP) (referred to as SMI) electrodes is developed. A 0.5-/spl mu/m-wide SiGe base self-aligned to the 0.1-/spl mu/m-wide emitter was selectively grown by using a UHV/CVD system. This self-aligned structure effectively reduces collector capacitance. In SMI technology, a tungsten film is selectively stacked on all poly-Si electrodes (base, emitter, and collector) in a self-aligned manner by using selective deposition without any heat treatment. So this technology does not cause unwanted diffusion of the base dopants and keeps a shallow intrinsic base profile. SMI technology can therefore provide low parasitic resistances and is well-suited to an SiGe-base HBT. A 2-/spl mu/m-wide BPSG/SiO/sub 2/ refilled trench was introduced in order to reduce the substrate capacitance. The low dielectric constant of BPSG/SiO/sub 2/ and the wide trench are very effective in reducing the sidewall element of substrate capacitance. This technology makes it possible to obtain ultra-high-speed operation with a 9.3-ps-gate-delay emitter-coupled-logic (ECL) circuit.

Ultra-low-power and high-speed SiGe base bipolar transistors for wireless telecommunication systems

Ultra-low-power and high-speed SiGe base bipolar transistors that can be used in RF sections of multi-GHz telecommunication systems have been developed. The SiGe base and a poly-Si/SiGe base-contact were formed by selective growth in a self-aligned manner. The transistors have a very small base-collector capacitance (below 1 fF for an emitter area of 0.2/spl times/0.7 /spl mu/m) and exhibit a high maximum oscillation frequency (30-70 GHz) at low current (5-100 /spl mu/A). The power-delay product of an ECL ring oscillator is only 5.1 fJ/gate for a 250-mV voltage swing. The maximum toggle frequency of a one-eighth static divider is 4.7 GHz at a switching current of 68 /spl mu/A/FF.

Application of Excimer-Laser Annealing to Amorphous, Poly-Crystal and Single-Crystal Silicon Thin-Film Transistors

An excimer-laser annealing method has been reviewed as a powerful fabrication technology for various kinds of high-performance thin-film transistors (TFTs) on glass. The method was confirmed very attractive, for the short-channel a-Si TFT, to form selectively the highly-conductive source and drain in a self-aligned manner. A non-stoichiometric SiC0.2 film was crystallized uniformly due to extremely non-isothermal melt-regrowth kinetics, and was applied to the poly-Si based hetero-TFT. This TFT had a low off-current even under strong illumination conditions. Various modifications have been done for enlarging the grain size to more than the TFT feature size. Combination of these modifications enables the single-crystal Si TFT to enter into a practical developmental stage.

Self-aligned metal/IDP Si bipolar technology with 12-ps ECL and 45-GHz dynamic frequency divider

Ultra-high-speed operation using a self-aligned stacked metal/in situ doped poly-Si (IDP) (referred to as SMI) Si bipolar transistor technology that offers low base resistance while keeping collector capacitance low is demonstrated. This SMI technology provides a base electrode consisting of metal and in situ boron-doped poly-Si (IBDP). Here, metal is fully stacked on the IBDP by using selective tungsten CVD in the self-aligned manner, which means that the structure has low sheet resistance and the fabrication process has a small thermal budget. Thus, low base resistance and low collector capacitance can be achieved. Three types of base electrode, an IBDP, a partially stacked SMI, and a fully stacked SMI, were fabricated to investigate the usefulness of this SMI technology and the importance of the low base resistance. Using the SMI technology, the base resistance was reduced to about 40% and the maximum oscillation frequency was raised by about 30% with respect to the conventional poly-Si base electrode. This technology makes it possible to obtain ultra-high-speed operation with a 12-ps gate-delay emitter-coupled logic (ECL) circuit, and with 45-GHz-dynamic and 28-GHz-static frequency dividers, even when using a conventional ion-implanted base.

A novel GaAs power MESFET with low distortion characteristics employing semi-insulating setback layer under the gate

A low distortion GaAs power MESFET has been developed by employing a semi-insulating setback layer under the gate. The setback region was obtained by diffusing chromium from the Cr/Pt/Au gate metal in self-aligned manner. The novel power FET with the setback layer was found to be insensitive to surface trapping effects. They showed only 5-6 percent frequency dispersion of drain current at 1 MHz compared to DC condition. Because of this small frequency dispersion, the typical measurement FET, which has a surface setback layer, with a gate width of 36 mm exhibited 1.5 dB larger output power at 1 dB gain compression point than that of the FET without the setback layer. Moreover, in the /spl pi//4 shift-QPSK modulation that has been most popular in digital mobile communication system, the FET exhibited 11 dB smaller adjacent channel leakage power than the conventional one at the output power of 31.5 dBm.

Amorphous-Silicon TFTs with Self-Aligned Poly-Silicon Source and Drain

A new self-aligned a-Si TFT has been proposed. The TFT has the highly conductive n+ poly-Si source and drain with self-aligned manner. The key process technique employed to this TFT is of excimer-laser selective recrystallization. Two ways have been successfully demonstrated to acheive the selectivity of recrystallization. The fabricated TFT had the field- effect mobility of 0.8cm2/Vs and high on/off current-ratio more than 107.

4935378 Method for manufacturing a semiconductor device having more than two conductive layers

According to a semiconductor device manufacturing method of the invention, a first polycrystalline silicon layer doped with an impurity, a thin oxide film, a second polycrystalline silicon layer, and a silicon nitride film are sequentially formed, one upon the other. The silicon nitride film, the second polycrystalline silicon layer, the thin oxide film, and the first polycrystalline silicon layer are then etched, in a self-aligned manner, by means of a photolithography process. A thick oxide film is formed on a side wall portion of the first polycrystalline silicon layer, using the silicon nitride film as a mask, and after the silicon nitride film is removed, a conductive film is formed on the entire surface. Since a film formation process advances without patterning the first polycrystalline silicon layer, the first polycrystalline silicon layer is not damaged by an RIE process and the like. A defect density of the oxide film formed on the first polycrystalline silicon layer can be reduced. Since the thick oxide film is formed on the side wall portion of the first polycrystalline silicon layer, a withstand voltage and reliability of this portion are largely improved.

Application of self-aligned CoSi/sub 2/ interconnection in submicrometer CMOS transistors

CoSi/sub 2/ interconnection layers of 0.14-0.40- mu m thickness were applied in a self-aligned manner to 0.75- mu m-gate-length n-channel and p-channel transistors in a complete CMOS device fabrication flow. The sheet resistance above the active regions ranged from 1.6 to as low as 0.46 Omega /square for the four CoSi/sub 2/ thicknesses examined. Using an Al-Cu/TiW metallization, the resistance per contact for 1- mu m-diameter openings to CoSi/sub 2/ was >

Self-aligned NiSi 2 electrode fabrication by MBE and its application to etched-groove Permeable Base Transistor (PBT)

A self-aligned NiSi 2 electrode fabrication process was developed. Epitaxial NiSi 2 films were selectively grown on a Si substrate by MBE with a thin SiO 2 film mask. NiSi 2 electrodes were fabricated simultaneously on the bottom and the top surfaces of grooved Si substrates in a self-aligned manner. These electrodes showed good Schottky characteristics. By using this method, etched-groove permeable base transistors (PBTs) were fabricated, where the NiSi 2 layers on the etched grooves were used as gate and source electrodes. The highest mutual conductance ( g m) was obtained as 32 mS/mm, which agreed well with the results of computer simulation.

Self-aligned AlGaAs/GaAs HBT with low emitter resistance utilizing InGaAs cap layer

A self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT) with an InGaAs emitter cap layer that has very low emitter resistance is described. In this structure, a nonalloyed emitter contact allows the emitter and base electrodes to be formed simultaneously and in a self-aligned manner. The reduction of emitter resistance greatly improves the HBT's transconductance and cutoff frequency. In fabricated devices with emitter dimensions of 2 mu m*5 mu m, a transconductance-per-unit-area of 16 mS/ mu m/sup 2/ and a cutoff frequency of 80 GHz were achieved. To investigate high-speed performance, a 21-stage ECL ring oscillator was fabricated using these devices. Propagation delay times as low as 5.5 ps/gate were obtained, demonstrating the effectiveness of this structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A self-aligned ridge substrate laser fabricated by single-step MOVPE

A novel self-aligned structure semiconductor laser, called a self-aligned ridge substrate (SAR) laser has been successfully fabricated by a single-step MOVPE process. The single-step process is attained by the epitaxial growth on a ridge formed along the 〈011〉 direction on a (100) substrate, taking advantage of the anisotropic and isolated growth on the ridged substrate. As a result the current-injection region and the active region are formed in a self-aligned manner. A CW operation under a threshold current of 46 mA typically has been obtained at room temperature in the SAR laser.

A novel technology for formation of a narrow active layer in buried heterostructure lasers by single-step MOCVD

A new technology of fabricating a buried heterostructure laser with a narrow active layer in a single-step MOCVD process other than the conventional two-step process is proposed. The technology is based on the separate growth on the undercut ridge. The anisotropic growth has been found to be very useful for formation of a very narrow active region in a self-aligned manner. The novel RBH laser implemented by the single-step MOCVD process has been proposed. The RBH laser has exhibited CW lasing oscillation with a threshold current as low as 30 mA at room temperature and with the circular beam spot.

Self-aligned AlGaAs/GaAs HBT with InGaAs emitter cap layer

A new self-aligned AlGaAs/GaAs HBT with an InGaAs emitter cap layer is presented. This HBT has nonalloyed ohmic contacts to the emitter and base that are formed simultaneously and in a self-aligned manner. The low emitter contact resistance of 1.4×10-7 Ωcm2 and the high transconductance per unit area of 3.3 mS/μm2 demonstrate the effectiveness of this structure.

High performance polymers: Their origin and development

Near-field electrospinning (NFES) is a newly-established technique by electrically charged a polymer solution to produce the site addressable one-dimensional (1D) fibers or two-dimensional (2D) aligned fibrous meshes. Nevertheless, the direct electrospinning of fibers into controllable is still a nascent technology. In this paper, a new integration of paper-based self-powered sensors (PSS) and three-dimensional (3D) architectures of NFES electrospun polyvinylidene fluoride (PVDF) micro/nano fibers (MNFs) is demonstrated in a direct-write and in-situ poled manner. Owing to the principle of piezoelectricity, the uni-poled dipole moment will be accumulated across the electrospun fibers and the output voltage and current could reach to 4 V and 100 nA respectively. Such charge transfer grounds the locally deposited fibers and renders them the preferential sites for the deposition of subsequent fibers. We apply NFES to directly write arbitrarily shaped 3D structures through consistent and spatially controlled fiber-by-fiber stacking of PVDF fibers. An element central to the success of this 3D electrospinning is the use of a printing paper placed on the grounded conductive plate and acting as a fiber collector. Once deposited on the paper, residual solvents from near-field electrospun fibers can infiltrate the paper substrate, enhancing the charge transfer between the deposited fibers and the ground plate via the fibrous network within the paper. Such charge transfer grounds the deposited fibers and turns them into locally fabricated electrical poles, which attract subsequent in-flight fibers to deposit in a self-aligned manner on top of each other. Finger striking and pushing motions are validated the open-circuit voltage and short-circuit current can be harvested during one finger–striking motion is measured as ~1.2 V/60 nA. The proposed technique has the potential to advance the existing electrospinning technologies in constructing 3D structures for biomedical and wearable electronics.

A new channel-doping technique for high-voltage depletion-mode power MOSFET's

A new channel-doping technique for high-voltage depletion-mode double-diffused MOSFET (DMOSFET) is demonstrated. The technique that is used is channel doping performed at the surface of the laterally diffused body region in a self-aligned manner. Decrease of the breakdown voltage due to decrease of the threshold voltage is successfully prevented by using the new technique. A 1050-V DMOSFET was experimentally fabricated with a negative threshold voltage of -2 V.