Self-aligned Ion Implantation Research Articles

A Novel SiC Trench MOSFET with Self-Aligned N-Type Ion Implantation Technique.

We propose a novel silicon carbide (SiC) self-aligned N-type ion implanted trench MOSFET (NITMOS) device. The maximum electric field in the gate oxide could be effectively reduced to below 3 MV/cm with the introduction of the P-epi layer below the trench. The P-epi layer is partially counter-doped by a self-aligned N-type ion implantation process, resulting in a relatively low specific on-resistance (Ron,sp). The lateral spacing between the trench sidewall and N-implanted region (Wsp) plays a crucial role in determining the performance of the SiC NITMOS device, which is comprehensively studied through the numerical simulation. With the Wsp increasing, the SiC NITMOS device demonstrates a better short-circuit capability owing to the reduced saturation current. The gate-to-drain capacitance (Cgd) and gate-to-drain charge (Qgd) are also investigated. It is observed that both Cgd and Qgd decrease as the Wsp increases, owing to the enhanced screen effect. Compared to the SiC double-trench MOSFET device, the optimal SiC NITMOS device exhibits a 79% reduction in Cgd, a 38% decrease in Qgd, and a 41% reduction in Qgd × Ron,sp. A higher switching speed and a lower switching loss can be achieved using the proposed structure.

Effects of trench profile and self-aligned ion implantation on electrical characteristics of 1.2 kV 4H-SiC trench MOSFETs using bottom protection p-well

The effects of a trench profile and self-aligned ion implantation on the electrical characteristics of 1.2 kV 4H-SiC trench MOSFETs employing a bottom protection p-well (BPW) were investigated to improve blocking capability by simulation studies. The trench profile and thickness of a SiO2 spacer during self-aligned ion implantation for BPW affect electrons flow through a trench gate as well as E-field concentration at the gate insulator on a trench bottom. At trench angle higher than 84° and a SiO2 spacer thicker than 0.2 µm showed that the Al concentration penetrated into the trench sidewall during ion implantation is less than 0.3% in comparison with the background doping concentration in a drift region. Under the optimum conditions with a trench angle of 90° and 0.2-µm-thick SiO2 spacer, a high breakdown voltage of 1.45 kV with a low E-field peak in the gate insulator was achieved.

Self-aligned formation of the trench bottom shielding region in 4H-SiC trench gate MOSFET

To suppress the electric field in the gate oxide in a trench gate MOSFET (UMOSFET) with small cell pitch, we developed a technique to form the p+ region using self-aligned ion implantation under the gate trench. To prevent Al+ injection into the trench sidewalls, conditions of thin oxide layer deposition and Al+ implantation were optimized by process simulation. The resulting SiC trench MOS capacitors exhibited long-term reliability, with no degradation in lifetime by the p+ shielding region, and a specific on-resistance of 9.4 mΩ cm2 with a blocking voltage of 3800 V was achieved in the UMOSFET.

Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications

Guided by the Wentzel-Kramers–Brillouin approximation for band-to-band tunneling (BTBT), various performance boosters for Si TFETs are presented and experimentally verified. Along this line, improvements achieved by the implementation of uniaxial strain in nanowires (NW), the benefits of high-k/metal gates, and newly engineered tunneling junctions as well as the effect of scaling the NW to diameters of 10 nm are demonstrated. Specifically, self-aligned ion implantation into the source/drain silicide and dopant segregation has been exploited to achieve steep tunneling junctions with less defects. The obtained devices deliver high on-currents, e.g., gate-all-around (GAA) NW p-TFETs with 10 nm diameter show ${I} _{\rm D} = 64~\mu $ A/ $\mu $ m at ${V} _{\rm DS} = {V} _{\rm GS} - {V} _{\rm off} = -1.0$ V, and good inverse subthreshold slopes (SS). Tri-gate TFETs reach minimum SS of 30 mV/dec. Dopant segregation helps to minimize the defect density in the junction and thus trap assisted tunneling (TAT) is reduced. Pulsed current-voltage (I-V) measurements have been used to investigate TAT. We could show that scaled NW devices with multigates are less vulnerable to TAT compared to planar devices due to a shorter tunneling path enabled by the inherently good electrostatics. Furthermore, SiGe NW homo- and heterojunction TFETs have been investigated. The advantages of a SiGe/Si heterostructure as compared to a homojunction device are revealed and the effect of line tunneling which results in an increased BTBT generation is demonstrated. It is also shown that complementary strained Si TFET inverters and p-TFET NAND gates can be operated at ${V} _{\rm DD}$ as low as 0.2 V. This suggests a great potential of TFETs for ultralow power applications. The analysis of GAA NW TFETs for analog applications provided a high transconductance efficiency and large intrinsic gain, even higher than for state-of-the-art 20 nm FinFETs at low voltages.

Improvement of floating island and thick bottom oxide trench gate metal–oxide–semiconductor field-effect transistor

A metal–oxide–semiconductor field-effect transistor (MOSFET) structure called FITMOS (floating island and thick bottom oxide trench gate MOSFET) has been successfully developed that exhibits outstanding low loss. This unique feature of the FITMOS is realised by fabricating deep trenches in the n-type drift layer, by forming p-type floating islands below the individual trenches using self-aligned ion implantation, and by fabricating trench gates with a thick oxide layer on the bottom. Then, the trade-off between the drain-to-source breakdown voltage and on-resistance has been further optimised by changing the shape of the floating islands from spherical to ellipsoidal. By improving the device structure, a breakdown voltage of 91 V and specific on-resistance of 41.5 mΩ mm2 have been obtained in a 4.5×4.5 mm square device with ellipsoidal floating islands. The relationship between the device structure and the reverse recovery characteristics is also investigated.

Properties of III-N MOS structures with low-temperature epitaxially regrown ohmic contacts

A significant limitation in the fabrication of III-N MOSFET relates to the formation of ohmic contacts for enhancement-mode MOSFET structures. Unlike existing III-N HFET devices, which include a high free-carrier density two-dimensional electron gas (2DEG) in the semiconductor substrate, a MOSFET in either accumulation or inversion mode require low free-carrier concentrations for the semiconductor channel to have an off-state. The applied gate bias enhances the free-carrier density in the channel, turning on the FET. Unfortunately, a low free-carrier density substrate is problematic for the formation of ohmic contacts, a problem usually dealt with in silicon MOS through self-aligned ion implantation. The high annealing temperatures associated with activating implanted dopants to substitutional sites limits the use of ion implantation for III-N MOSFET fabrication. To overcome this difficulties, selected area epitaxial re-growth of doped III-N materials was developed to form source-drain contacts on otherwise low-doped III-N epitaxial substrates, yielding the needed N+/n−/N+ or N+/p−/N+ structures. Contact re-growth was performed by MOVPE using a silicon nitride dielectric mask defining plasma-etched recesses in the source-drain region. A significant acceleration in the growth rate and surface roughening was observed following re-growth relative to a non-selective area epitaxial growth due to the reduced fill-factor, motivating a general change in MOVPE-operating conditions during re-growth. As the re-growth was intentionally designed to limit the lateral extent of the source-drain regions, the MOVPE re-growth process was performed under conditions limiting lateral overgrowth. III-N MOSFET structures with epitaxial regrown contacts are projected to provide a pathway for low threshold voltage devices suitable for amplifier or logic applications.

Effect of post-implantation anneal on the electrical characteristics of Ni 4H-SiC Schottky barrier diodes terminated using self-aligned argon ion implantation

The effects of post-implantation annealing on the electrical characteristics of Ni 4H-SiC Schottky barrier diodes terminated using self-aligned Ar + ion implantation have been investigated. Results show that the Ar + edge termination may be modelled as a shunt linear resistive path at low to moderate reverse bias levels and at low forward bias levels. Low temperature (400–700°C) annealing is shown to increase the equivalent resistance of the edge termination by two orders of magnitude without significant effect on the breakdown voltage. Annealing temperatures above 600°C are, however, shown to degrade the on-state performance. A breakdown voltage of 1530 V was achieved on the implanted and annealed samples, representing 90% of the theoretical parallel plane breakdown voltage. Temperature dependent measurements, made over the temperature range 25–400°C show that the equivalent resistance of the edge termination is thermally activated with an exponential temperature coefficient of −0.02 K −1. Behaviour at moderate forward bias levels is typical of thermionic emission whilst operation at high forward bias is dominated by a linear series resistance which shows a quadratic temperature dependence, increasing by a factor of 6 over the range 25–400°C.

GaAs quantum wire lasers grown on v-grooved substrates isolated by self-aligned ion implantation

Multiple vertically stacked GaAs/Al/sub x/Ga/sub 1-x/As quantum wires laser diodes have been fabricated via MOVPE on v-grooved GaAs substrates. The devices are electrically isolated by oxygen ion implantation, utilizing the nonplanarity of the device. The process is self-aligning and requires no masking, yielding significant simplification in the device fabrication. Optimum implant conditions are determined. A quantum internal efficiency of 65.8% is measured for the optimum implanted devices, which exhibit a 5.5 mA threshold current.

Ultraminiature silicon capacitive pressure-sensing elements obtained by silicon fusion bonding

We present a technology to fabricate ultraminiature capacitive-type sensing elements for use in blood-pressure measurements, each of them having a side dimension of only 130 μm. The devices, which are made in an array configuration, are fabricated using the silicon fusionbonding technique and self-aligned boron ion implantation. The process is simple, requiring only three mask levels, and has high yield. Throughout the paper we compare the fabrication process as well as the measurement results of the array configuration with single membranes having the same measurement range. Measurement results are presented for both static and dynamic pressure conditions.

Miniaturization of Si diaphragms obtained by wafer bonding

A technology is presented to fabricate ultraminiature capacitive type sensing elements for use in blood pressure measurements with each of them having a side dimension of only 130 μm. The devices that were made in an array configuration were fabricated using the silicon fusion bonding technique and self-aligned boron ion implantation. The process is simple requiring only three mask levels and high yield. Results are presented for both static and dynamic pressure conditions.

Fabrication of a New Si Field Emitter Tip with Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) Structure

A current-controllable silicon field emitter tip with a metal-oxide-semiconductor field-effect transistor (MOSFET) structure is fabricated. The device has a simple structure in which a conical Si tip is made in the drain region of a MOSFET. The gate performs two roles; one is that of a conventional extraction gate and the other is that of a control gate for the drain current supplied to the tip. The fabrication process is very simple. In order to form n-type regions for the source and drain, only two steps including a self-aligned ion implantation were added to the conventional silicon tip fabrication process. Experimental results showed that the emission current was well controlled and stabilized by the drain current of the MOSFET. Stable emission of about 0.8 µA was obtained with a single tip. We also discuss a dual-gate MOSFET for further extension of the fabrication process introduced.

Comparison of Standard and Low-Dose Separation-by-Implanted-Oxygen Substrates for 0.15 µm SOI MOSFET Applications

The influence of buried oxide thickness on short-channel effects in silicon-on-insulator metal-oxide-semiconductor field-effect transistors (SOI MOSFET's) is investigated. It is shown by analytical modeling and numerical simulation that, although a thin buried oxide helps to reduce the charge-sharing component of source and drain electric fields through the oxide layer, substrate depletion underneath the thin buried oxide counteracts the oxide thinning. Although this effect is desired below the source and drain regions to maintain the SOI inherent low junction capacitances, it is detrimental to short-channel-effect suppression. The calculated results are experimentally confirmed on 0.1 µm SOI MOSFET's fabricated on both standard and low-dose separation-by-implanted-oxygen (SIMOX) substrates. A new structure for 0.15 µm SOI MOSFET applications on a thin buried oxide substrate is proposed in which substrate depletion below the channel-forming region can be suppressed locally using self-aligned deep ion implantation.

A lightly doped deep drain GaAs MESFET structure for linear amplifiers of personal handy-phone systems

An improved GaAs MESFET structure, named a buried p-layer lightly doped deep drain (BP-LD3) structure, is proposed. This structure can be fabricated by the conventional self-aligned gate and selective ion implantation technologies, and the FET characteristics show a high transconductance, a high breakdown voltage, and a low drain-source resistance. The lightly doped deep drain characterizing this structure was introduced on the basis of a two-dimensional numerical analysis including an impact ionization for a buried p-layer lightly doped drain (BP-LDD) structure which has been applied for high-speed digital ICs. The simulated results clarified that a low breakdown voltage of the BP-LDD structure originates from a high rate of carrier generation due to the impact ionization in the lightly doped drain region. The reason is that both electric field and current density become high in the region. In the new BP-LD3 structure, the electron current expands due to the deep formation of lightly doped drain, therefore impact ionization is reduced. This BP-LD3 structure was fabricated and the FET characteristics were compared with those of the conventional BP-LDD structure, and a structure which is now being studied for linear amplifiers of 1.9 GHz personal handy-phone systems. The measured breakdown voltage of 8.1 V, transconductance of 360 mS/mm, and drain-source resistance of 2.5 /spl Omega//mm for the BP-LD3 structure indicate high potentiality for analog applications.

High Mobility Non-Hydrogenated Low Temperature Polysilicon TFTs

AbstractWe have fabricated polysilicon (poly-Si) thin film transistors (TFTs) using a standard 4-mask sequence, with self-aligned ion implantation for source and drain doping. The active layer was obtained by solid phase crystallisation of high purity Si2H6-deposited amorphous Si, whereas the gate oxide was synthesised by a novel plasma deposition technique, namely distributed electron cyclotron resonance plasma enhanced chemical vapour deposition (DECR PECVD). We have obtained high carrier mobilities (70 cm2V−1s−1 for electrons and 40 cm2V−1s−1 for holes) with an excellent uniformity and without the need for a post-hydrogenation treatment. Moreover, we show that the TFT characteristics are practically insensitive to hot carrier effects.

The effect of fluorine on MOSFET channel length

The effect of fluorine on MOS device channel length has been evaluated. Fluorine has been introduced into the transistor by self-aligned ion implantation after the lightly doped drain (LDD) implant. The impact of fluorine in the LDD region, and its effect on the electrically determined channel length (L/sub eff/), has been examined. Measurements taken from 0.6- mu m LDD MOSFETs show a significant dependence of the L/sub eff/ on fluorine implant dose. The n/sup +/ resistor also shows more width reduction compared to unfluorinated samples. The decrease in channel length reduction by adding fluorine in the LDD region may yield way to relieve short-channel effects for the continuous scaling of CMOS devices into the deep-submicrometer region. >

A 0.4- mu m gate-length AlGaAs/GaAs P-channel HIGFET with 127-mS/mm transconductance at 77 K

WN-gate, p-channel AlGaAs-GaAs heterostructure insulated-gate field-effect transistors (HIGFETs) fabricated on a metalorganic vapor-phase epitaxy (MOVPE) wafer are discussed. A self-aligned Mg ion implantation (80 keV, 6*10/sup 13/ cm/sup -2/) annealed at 850 degrees C in an arsine atmosphere and the control of the SiO/sub 2/ sidewall dimensions allow the fabrication of p-channel HIGFETs with a gate length smaller than 0.5 mu m with low subthreshold current. P-channel HIGFETs with 0.4- mu m gate lengths exhibit extrinsic transconductances as high as 127 mS/mm at 77 K and 54 mS/mm at 300 K. >

High-performance short-channel MESFETs with WSiN gate suppressing As-outdiffusion (SAINT-GEN.II)

The formation of a highly conductive channel, which is one of the most effective methods to achieve high-performance GaAs MESFETs, requires that As-outdiffusion during high-temperature annealing be suppressed, because As vacancy creates more implanted Si acceptors, decreasing channel conductance. A refractory metal, WSiN, that effectively suppressing As-outdiffusion has been applied in an n/sup +/-self-aligned ion-implantation MESFET technology (SAINT-GEN.II), and the performance of the fabricated FETs experimentally evaluated. The device structure studied had a 10-keV implanted shallow channel with a buried p-layer and an Au-coated WSiN gate. A 630 mS/mm maximum transconductance at gate voltage of 0.6 V and 510 mS/V-mm K-value at threshold voltage of -0.14 V were obtained. A 920 mS/mm intrinsic transconductance was estimated from source resistance of 0.51 Omega -mm. The gate resistance was as small as 3 mu Omega -cm. A cutoff frequency as high as 96 GHz was obtained by extrapolating the current gain of 0.5 to 25.5 GHz at the correct 6 dB/octave. The effective saturation velocity is estimated at 1.8*10/sup 7/ cm/s. This represents an 80% improvement of velocity overshoot compared to long-gate MESFETs. The characteristics of a 23-stage ring oscillator using direct-coupled FET logic (DCFL) circuits with a propagation delay time of 6.7 ps/gate have also been investigated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 630-mS/mm GaAs MESFET with Au/WSiN refractory metal gate

GaAs MESFET's with a gate length as low as 0.2 mu m have been successfully fabricated with Au/WSiN refractory metal gate n/sup +/-self-aligned ion-implantation technology. A very thin channel layer with high carrier concentration was realized with 10-keV ion implantation of Si and rapid thermal annealing. Low-energy implantation of the n/sup +/-contact regions was examined to reduce substrate leakage current. The 0.2- mu m gate-length devices exhibited a maximum transconductance of 630 mS/mm and an intrinsic transconductance of 920 mS/mm at a threshold voltage of -0.14 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

GaAs/AlGaAs inversion channel devices for an integrated opto-electronic technology

Optoelectronic integrated circuits based on devices having an inversion channel (electrons) induced at a heterointerface by a charge sheet of donors placed at the heterointerface have been investigated. These devices include the HFET, a heterojunction analog to the MOSFET; the HFED, a three-terminal lateral photodetector; the BICFET, a bipolar transistor in which the inversion channel acts as an induced base to eliminate charge storage; and the DOES, a three- or four-terminal optical/electrical switching device. The intrinsic compatibility of these devices was demonstrated by fabricating a single device structure on a GaAs/AlGaAs MBE (molecular-beam epitaxy)-grown wafer. Devices were processed using a mesa technology with refractory gates, self-aligned ion implantation and high-temperature RTA (rapid thermal annealing) cycles. The measured characteristics of the devices, obtained without optimization of the material growth, the device structural design, or the fabrication, indicate that the inversion channel technology has a unique potential for optoelectronic integration.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Self-aligned modulation-doped (Al,Ga)As/GaAs field-effect transistors

The first modulation-doped (Al,Ga)As/GaAs field-effect transistors (MODFET's) have been fabricated using a self-aligned ion-implantation process. Measured extrinsic transconductances of 190 mS/mm were achieved at 300 K with source resistances of 1 Ω.mm. The highest currents yet reported for such device structures, in excess of 350 mA/mm, were obtained. A value of the maximum two-dimensional electron gas concentration of nearly 1.2 × 1012cm-2was obtained from an analysis of the FET drain current-voltage characteristics using the charge-control model. These results hold promise for the practical fabrication of very high speed integrated circuits based on MODFET's, using a completely planar self-aligned ion-implantation process.