Self-aligned GaAs MESFET Research Articles

A two-dimensional analytical model for the gate–source and gate–drain capacitances of ion-implanted short-channel GaAs metal-semiconductor-field effect transistor under dark and illuminated conditions

This paper presents an analytical model for the internal capacitances of short-channel ion-implanted GaAs MESFETs under dark and illuminated conditions. The device structure considered in this study is a normally-on self-aligned GaAs MESFET with indium tin oxide (ITO) as the Schottky metal for the gate electrode of the device. The gate area of the device is illuminated by an optical radiation of 0.87 μm from an external source which is coupled into the device through the semitransparent ITO metal at Schottky-gate to modulate the electrical and microwave characteristics of the device. The nonanalytic Gaussian doping profile commonly considered for the channel doping of an ion-implanted GaAs MESFET has been replaced by an analytic Gaussianlike function for the simplicity of the present model. The two-dimensional (2D) potential distribution obtained by solving the 2D Poisson’s equation by including the effect of photo-generated carriers due to the incident optical radiation has been utilized to model the depletion region width below the gate of the short-channel GaAs MESFETs. The depletion width model has then been used to model the internal gate-source and gate-drain capacitances of the device operating under both the linear and saturation regions. The effect of illumination on the Schottky junction at the gate of the MESFET has been modeled by considering an induced photo-voltage developed across the junction that is superimposed on the applied gate bias voltage. The proposed model has been verified by comparing the theoretically predicted results with simulated data obtained by using the commercially available ATLASTM 2D device simulator.

V-band monolithic low-noise amplifiers using ion-implanted n/sup +/-self-aligned GaAs MESFETs

V-band monolithic low-noise amplifiers (LNAs) were successfully fabricated using a manufacturable GaAs MESFET process. Ion-implanted n/sup +/-self-aligned GaAs MESFETs, which are used to make digital ICs, were employed. A fabricated single-stage LNA with a 0.13 μm Au/WSiN gate demonstrated a noise figure of 5 dB at 60 GHz with an associated gain of 7 dB. A two-stage LNA achieved a noise figure of 6 dB at 60 GHz with an associated gain of 14 dB. This is the first demonstration of ion-implanted n/sup +/-self-aligned GaAs MESFETs for millimeter-wave monolithic integrated circuits (MIMICs). The results are among the best ever reported for V-band GaAs-MESFET amplifiers.

A large-signal model of self-aligned gate GaAs FET's for high-efficiency power-amplifier design

We propose a large-signal model that can simulate the power-added efficiency of p-pocket self-aligned gate GaAs MESFET's. This model includes a new drain current model and a gate bias-dependent RF output resistance to express the drain conductance and its frequency dispersion at each gate bias. In addition, gate-source and gate-drain capacitances are modeled by functions of two variables of gate and drain biases so as to fit the measured values of ion implanted channels. The simulated power-added efficiency agreed with the measured value with a maximum error of 5%. The intermodulation distortion was also simulated and the maximum difference between the simulated and measured results was reduced to one-fifth of the results simulated by the conventional model. Practical applications were demonstrated by the load-pull simulation and the /spl pi//4 shift QPSK-modulated signal simulation.

Electrical and chemical characterization of W/sub 1-x-y/Si/sub x/N/sub y/ (0≤x≤0.42, 0≤y≤0.30) Schottky diodes for self-aligned gate GaAs MESFETs

WSiN Schottky diodes on GaAs have been electrically and chemically characterized for atomic silicon and nitrogen; compositions of 0 to 42% and 0 to 28%, respectively. It is found that the main cause for Schottky diode degradation, after high temperature annealing, is the out-diffusion of As from GaAs. For films with atomic nitrogen composition of /spl ges/5%, As outdiffusion is eliminated as long as the atomic Si composition is /spl les/40%. WN films (5% nitrogen) were applied to the fabrication of self-aligned gate lightly doped drain MESFET's with buried P layer. A maximum transconductance, g/sub m/, of 370 mS/mm, f/sub T/ of 33 GHz, and DCFL inverter delay of 29 ps are measured for a 0.5 /spl mu/m gate technology. >

High-temperature stability of refractory-metal VLSI GaAs MESFETs

Commercially available, self-aligned VLSI GaAs MESFETs, with tungsten-based refractory-metal Schottky gates, nickel-based refractory-metal ohmic contacts, and aluminum interconnection metallization, have been thermally cycled and shown to be stable after 3 h at temperatures up to 500/spl deg/C. Both partially processed and fully processed wafers were found to be stable with no significant change occurring in either Schottky gate or ohmic contact properties. An increase in the channel resistance component of the series resistance is believed to be responsible for I/sub DS/ and g/sub m/ degradation above 500/spl deg/C. The fact that commercially available, gold-free VLSI GaAs MESFETs are able to withstand such thermal cycles has very important consequences for monolithic optoelectronic integrated circuit (OEIC) fabrication because it means that it may now be feasible to grow photonic device heterostructures epitaxially on MESFET VLSI wafers; process them into lasers, modulators, and/or detectors; and interconnect them with the electronics to produce VLSI-density OEICs. >

Characterization of double pulse-doped channel GaAs MESFETs

The fabrication and characterization of a double pulse-doped (DPD) GaAs MESFET grown by organometallic vapor phase epitaxy (OMVPE) are reported. The electron mobility of a DPD structure with a carrier concentration of 3*10/sup 18//cm/sup 3/ was 2000 cm/sup 2//V-s, which is about 20% higher than that of a pulse-doped (PD) structure. Implementing the DPD structure instead of the conventional PD structure as a GaAs MESFET channel, the drain breakdown voltage, current gain cutoff frequency, and maximum stable gain (MSG) increase. The maximum transconductance of 265 mS/mm at a drain current density of 600 mA/mm, a current gain cutoff frequency of 40 GHz, and an MSG of 11 dB at 18 GHz were obtained for a 0.3 mu m n/sup +/ self-aligned DPD GaAs MESFET. >

High microwave and ultra-low noise performance of fully ion-implanted GaAs MESFETs with Au/WSiN T-shaped gate

Fully ion-implanted n/sup +/ self-aligned GaAs MESFETs with high microwave and ultra-low-noise performance have been fabricated. T-shaped gate structures composed of Au/WSiN are employed to reduce gate resistance effectively. A very thin and high-quality channel with high carrier concentration can be formed by adopting the optimum annealing temperature for the channel, and the channel surface suffers almost no damage by using ECR plasma RIE for gate formation. GaAs MESFETs with a gate length as short as 0.35 mu m demonstrated a maximum oscillation frequency of 76 GHz. At an operating frequency of 18 GHz, a minimum noise figure of 0.81 dB with an associated gain of 7.7 dB is obtained. A K/sub f/ factor of 1.4 estimated by Fukui's noise figure equation, which is comparable to those of AlGaAs/GaAs HEMTs with the same geometry, reveals that the quality of the channel is very high. >

8 Gb/s 8:1 multiplexer and 1:8 demultiplexer IC's using GaAs DCFL circuit

High-speed 8:1 multiplexer and 1:8 demultiplexer ICs composed of GaAs direct-coupled FET logic (DCFL) have been designed and fabricated. The ICs were designed with a tree-type architecture and using memory-cell-type flip-flops (MCFFs). Self-aligned GaAs MESFETs with a gate length of 0.5 mu m were used in these ICs. The propagation delay time of the DCFL inverter was 19.0 ps/gate. Both ICs operated up to 8 Gb/s with power dissipations of 1.5 W for the multiplexer and 1.9 W for the demultiplexer at a single power supply voltage of 2.0 V. These ICs are applicable for multigigabit lightwave communication systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A self-aligned GaAs MESFET process with WSi gates for analog and digital applications

A GaAs MESFET fabrication process based on self-aligned WSi gates with gatelengths down to 0.5 μm is described. A buried p-layer is employed to suppress short-channel effects. The shallow FET channels are connected to the deeper implants of the ohmic source and drain contacts by means of an intermediate-dose “lightly-doped drain” (LDD) implant. Owing to a planarization concept which allows the use of a low-resistance Au overlayer on top of the high resistivity WSi gates, the process yields FETs with excellent high-frequency performance. This is proved by transit frequencies ƒ t exceeding 30 GHz, maximum frequencies of oscillation ƒ max of typically 100 GHz, and a noise figure NF min of 1.0 dB at 12 GHz (nominal gatelength 0.5 μm). FETs with three different threshold voltages are fabricated. All three types of transistors have transconductances of 300 mS/mm or above. This combination of properties makes the technology suitable for the realization of digital as well as microwave circuits.

Effects of neutral buried p-layer on high-frequency performance of GaAs MESFETs

Fully ion-implanted n/sup +/ self-aligned GaAs MESFETs with Au/WSiN refractory metal gates have been fabricated by adopting neutral buried p-layers formed by 50-keV Be-implantation. S-parameter measurements and equivalent circuit fittings are discussed. When the Be dose is increased from 2*10/sup 12/ cm/sup -2/ to 4*10/sup 12/ cm/sup -2/, the maximum value of the cutoff frequency with a 0.2- mu m gate falls off from 108 to 78 GHz. This is because a neutral buried player makes the intrinsic gate-source capacitance increase markedly, while its influence on gate-drain capacitance and gate-source fringing capacitance is negligible. The maximum oscillation frequency recovers, however, due primarily to the drain conductance suppression by the higher-concentration buried p-layer. An equivalent value of over 130 GHz has been obtained for both 0.2- mu m-gate GaAs MESFETs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

DC to 10-GHz mixer and amplifier GaAs IC's for coherent optical heterodyne receiver

The authors describe a number of design techniques that are effective for enhancing sensitivity and bandwidth. A Gilbert-cell circuit with a single-to-balance conversion input buffer and a peaking circuit are adopted for the mixer. In addition, a wideband amplifier is proposed that adopts a novel multiple-feedback cascode FET amplifier configuration with an LC input matching network. Finally, a novel interconnection technique is proposed that improves impedance matching between ICs and the package over a wide frequency range up to 10 GHz. These ICs were fabricated using a 0.2- mu m gate self-aligned GaAs MESFET process. These techniques could enable a highly sensitive multigigabit-per-second coherent optical heterodyne receiver to be implemented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Two-dimensional simulation of orientation effects in self-aligned GaAs MESFETs

The stress-induced orientation effects in self-aligned GaAs MESFETs were studied using a two-dimensional analysis. Devices oriented along different crystal directions, with different gate lengths, and under different stress conditions were studied. It was found that the piezoelectric effect caused by the surface stress plays a very important role in the device characteristics of short-channel self-aligned MESFETs. Structure parameters such as lateral spreading of N/sup +/ ions and p-type impurity concentration in the substrate were found to have great influence on the short-channel effect as well as the orientation effect. The short-channel effects can be suppressed and the device performance improved if the devices are oriented in the right direction and the structure of the devices and the thickness of the surface dielectric layer are properly chosen.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Characterisation of CoSi2/- and TiSi2/n-GaAs Schottky barriers

The heights of CoSi2/- and TiSi2/n-GaAs Schottky barriers are determined, by various methods, to be 0.77 and 0.64 eV respectively. These values are discussed in view of the recently developed Schottky barrier theories such as the advanced unified defect model and the effective workfunction model. The thermal stability of these contacts is investigated and it is found that the CoSi2/n-GaAs barrier height remains reasonably stable up to 600 degrees C for 10 min anneals and up to 750 degrees C for 1 min anneals. Under oxygen-free conditions and/or for shorter anneal times, this limit value may probably be increased. Consequently, CoSi2 may be an interesting contact material for high-temperature applications such as self-aligned GaAs MESFET fabrication.

High K-value LDD GaAs MESFET's with SiF/sub 3/-implanted shallow channels

High K-value self-aligned GaAs MESFETs with a reduced short-channel effect that were developed using both shallow SiF/sub 3/-implanted channels annealed with a WSiN refractory metal cap and a lightly doped drain (LDD) structure are discussed. The 0.5- mu m-gate device has a maximum transconductance of 360 mS/mm and a K-value of 504 mS/Vmm with a threshold voltage of 60 mV. The threshold voltage shift was only 90 mV when the gate length was reduced from 2.0 to 0.5 mu m. In addition, more precise control of the threshold voltage was obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A novel cap-annealing technique using a WN/sub x/ film as a capsulant in the refractory gate self-aligned GaAs MESFET fabrication process

A novel cap-annealing technique for n/sup +/ implanted layers in GaAs MESFET's was investigated from the viewpoint of thermal stress relaxation. In this technique, the same metal as the gate's-tungsten nitride (WN/sub x/) was used for an underlayer of a double-layer annealing cap. FET parameters V/sub th/, K-value, and N/sub g/ showed behavior in the short-channel region just as if the short-channel effects were suppressed. >

Amorphous WSi0.45 Metallization for Self-Aligned GaAs MESFETs

ABSTRACTCrystallization temperature (Tc) of amorphous WSix films on GaAs was studied as a function of the Si/W ratio. The highest Tc of 875°C for a 20 min anneal was obtained for co-sputtered WSMi films with the Si/W ratio of 0.45 (31 at.% Si). The WSi0.45 films remained amorphous following implant activation anneal and served as a barrier to Ga and As outdiffusion. Pitting of GaAs under the contact was also prevented. The WSi0.45 composition corresponds to the eutectic point between the W and W5Si3 phases, which was explained by the strong glass-forming tendency of eutectic alloys. Amorpous WSi0.45 films formed stable Schottky contacts to n-GaAs and produced minimum reduction of carrier concentration in the substrate. Therefore, the Si/W ratio of 0.45 is suggested as optimal for the WSix refractory gate metallization in self-aligned GaAs MESFErs.

Arsine Ambient Rapid Thermal Annealing

ABSTRACTWe have constructed a multiple wafer arsine ambient rapid thermal anneal (RTA) system and have applied it to the fabrication of high-performance refractory-gate self-aligned GaAs MESFETs. This has allowed us to take advantage of some of the features of rapid thermal annealing for these devices (reduced dopant movement and gate-channel interaction) without the difficulties of capped RTA (decapping problems, cap thermal mismatch stress driven dopant movement and gate-channel interaction) or the uncertain As loss characteristics of uncapped or proximity RTA. The anneal system uses a cylindrical furnace with a graphite boat heated by tungsten lamps with a 60 KW maximum power input. This allows heating rates in excess of 100°C/sec for up to four, two-inch wafers per run with a controlled arsine ambient of 0–20 Torr in an inert gas carrier. Closed loop temperature control is accomplished using a 5 μm wavelength optical pyrometer. The system has been designed to collect the As cracked from AsH, in a downstream trap and essentially no As is deposited in the wafer load area.Using arsine ambient RTA to anneal 15 KV 20Si+ self-aligning implants for GaAs MESFETs with MOCVD grown channels (30 nm, 1.7 × 1018/cm3), we have been able to fabricate enhancementmode self-aligned MESFETs with gm/gd &gt; 20 and extrinsic k-factor as large as 765 mS/V-mm for 0.15 μm gate length.

Orientation and ion-implanted transverse effects in self-aligned GaAs MESFET's

The orientation dependence of the threshold voltage and device transconductance of ion-implanted GaAs FET's has been investigated and modeled. The threshold voltages of the devices along the [011] and [01 \bar{1} ] directions are different when the gate length is short (≤ 3 µm). Experimental results and theoretical calculations show that this is primarily due to the strain in the active channel, induced by the dielectric overlayer. For the short self-aligned gate structure, the lateral spread of the ion-implanted n+layer is important as well. When these two effects are taken into account, calculated results agree well with the experimental data for standard self-aligned gate structures, and self-aligned structures with a sidewall or T-gate, fabricated using lamp- or furnace-annealing processes. This model also allows us to simulate the threshold voltage and transconductance dependence on the annealing time for different device parameters (such as gate length and channel doping)and process variables (i.e., sidewall or T-gate dimensions and impurity diffusion constant). We also calculated the gate length dependence of the transconductance for devices fabricated using a sidewall process. Results of this calculation are compared with the experimental data for different sidewall thicknesses.

A simple self-aligned GaAs MESFET using polyimide

A simple self-aligned gate process for fabricating gallium arsenide MESFET is described which uses a polyimide layer. The process is like the SAINT process rather than the refractory gate processes in that the gate is not in place during post-implantation annealing.

Characterization of WNx/GaAs Schottky Contacts Formed by Reactive RF Sputtering

The structural and electrical characterization of WNx/GaAs Schottky contacts formed by a reactive rf sputtering in a mixed nitrogen-argon gas atmosphere was performed under various fabricating conditions to establish a Schottky gate for a self-aligned GaAs MESFET. The characteristics of a WNx film and a WNx/GaAs contact greatly depend on the relative nitrogen gas partial pressure γ, rf sputtering power P0, and annealing temperature TA. We determined the optimum values of γ, P0, and TA in order to obtain an excellent thermally stable WNx/GaAs Schottky contact for a self-aligned gate, with a typical barrier height φBOI of about 0.94 eV and an ideality factor n of ∼1.1.