Second-order Loop Research Articles

Chaos and bifurcation in a third-order phase locked loop

The chaos induced in a new type of phase locked loop (PLL) having a second-order loop filter is investigated. The system under consideration is modeled as a third-order autonomous system with sinusoidal phase detector characteristics. The modern of nonlinear theory such as bifurcation and chaos is applied to a third-order of PLL. A method is developed to quantitatively study the type of bifurcations that occur in this type of PLL’s. The study showed that PLL experiencing a Hopf bifurcation point as well as chaotic behaviour. The method of multiple scales is used to find the normal form near the Hopf bifurcation point. The point is found to be supercritical one.

A 1.5 V Current-Mode CMOS RMS-to-DC Converter

A very low voltage, current-mode CMOS RMS-to-DC converter is presented. It is fully designed using MOS Translinear techniques. More specifically, its main building blocks are a squarer/divider and a geometric-mean cell which are obtained by using simple second-order MOS Translinear loops in a folded configuration, leading to a very regular and compact implementation. A novel biasing technique is employed for such loops, allowing them to operate at supply voltages as low as 1.5 V. Experimental results for a prototype IC demonstrating the correct operation of the circuit are included.

Continuous time quadrature band-pass ΔΣ modulator with input mixers

A continuous time quadrature band-pass ΔΣ modulator preceded by input mixers is presented. Complex band-pass ΔΣ modulators provide better performance than band-pass ΔΣ modulators in digitising complex signals due to more efficient noise shaping (Yantzi et al., 1997). Continuous time implementation of the second-order ΔΣ noise shaping loop filter is preferred to a switched capacitor structure (van der Zwan and Dijkmans, 1996). Through the integration of mixers in the AD converter, RF input signals in the range 0.3–1.6 GHz can be down-converted to a digital I and Q output stream at a clock rate of 128 MHz. It is designed as a front-end for a low power receiver with a 2 MHz IF bandwidth centred around 4 MHz and attains a signal-to-noise ratio higher than 60 dB. The ΔΣ ADC and mixer are integrated in a 0.25 μm CMOS technology and consume 14 mW from a 2 V supply

Phase tracking: what do we gain from optimality? Particle filtering versus phase-locked loops

This paper studies the problem of tracking a Brownian phase with linear drift observed to within one digital modulation and one additive white Gaussian noise. This problem is of great importance as it models the problem of carrier synchronization in digital communications. The ultimate performances achievable for this problem are evaluated and are compared to the performances of three solutions of the problem. The optimal filter cannot be explicitly calculated and one goal of the paper is to implement it using recent sequential Monte-Carlo techniques known as particle filtering. This approach is compared to more traditional loops such as the Costas loop and the decision feedback loop. Moreover, since the phase has a linear drift, the loops considered are second-order loops. To make fair comparisons, we exploit all the known information to put the loops in their best configurations (optimal step sizes of the loops). We show that asymptotically, the loops and the particle filter are equivalent in terms of mean square error. However, using Monte-Carlo simulations we show that the particle filter outperforms the loops when considering the mean acquisition time (convergence rate), and we argue that the particle filter is also better than the loops when dealing with the important problem of mean time between cycle slips.

Versatile voltage-mode active-only biquad with lossless and lossy integrator loop

This paper presents a realization of a voltage-mode active-only biquad using operational amplifiers (OAs) and operational transconductance amplifiers (OTAs). The circuit configuration is obtained from a second-order integrator loop structure with lossless and lossy integrators. The proposed circuit can realize low-pass, band-pass, high-pass, band-stop and all-pass transfer functions by a suitable choice of input and output terminals. The circuit characteristics can be electronically tuned through adjustment of the transconductance gains of the OTAs. An example is given, together with simulated results by PSPICE. The circuit configuration is very suitable for implementation in both bipolar and CMOS technologies.

Analysis of Reset Control Systems Consisting of a FORE and Second-Order Loop1

Reset controllers consist of two parts—a linear compensator and a reset element. The linear compensator is designed, in the usual ways, to meet all closed-loop performance specifications while relaxing the overshoot constraint. Then, the reset element is chosen to meet this remaining step-response specification. In this paper, we consider the case when such linear compensation results in a second-order (loop) transfer function and where a first-order reset element (FORE) is employed. We analyze the closed-loop reset control system addressing performance issues such as stability, steady-state response, and transient performance.

A time-delay digital tanlock loop

We propose a nonuniform sampling digital tanlock loop (DTL) that utilizes a constant time-delay unit instead of the constant 90/spl deg/ phase shifter The new structure reduces the complexity of implementation and avoids many of the practical problems associated with the digital Hilbert transformer like the approximations and frequency limitations. The time-delay digital tanlock loop (TDTL) preserves the most important features of the conventional DTL (CDTL), such as reduced sensitivity to the variation of the signal power. It also introduces improvement over the first-order CDTL under suitable choice of the circuit parameters. The first- and second-order loops are analyzed for locking conditions and steady-state phase error.

Near-optimal PLL design for decision-feedback carrier and timing recovery

A new design method is presented for the design of PLL loop filters for carrier recovery, bit timing, or other synchronization loops given the phase noise spectrum and noise level. Unlike the conventional designs, our design incorporates a possible large decision delay and S-curve slope uncertainty. Large decision delays frequently exist in modern receivers due to, for example, a convolutional decoder or an equalizer. The new design also applies to coherent optical communications where delay in the loop limits the laser linewidth. We provide an easy-to-use complete design procedure for second-order loops. We also introduce a design procedure for higher order loops for near-optimal performance. We show that using the traditional second-order loop is suboptimal when there is a delay in the loop, and also shows large improvements, either in the amount of allowed delay, or the phase error variance in the presence of delay.

Real-time fringe pattern demodulation with a second-order digital phase-locked loop

The use of a second-order digital phase-locked loop (DPLL) to demodulate fringe patterns is presented. The second-order DPLL has better tracking ability and more noise immunity than the first-order loop. Consequently, the second-order DPLL is capable of demodulating a wider range of fringe patterns than the first-order DPLL. A basic analysis of the first- and the second-order loops is given, and a performance comparison between the first- and the second-order DPLL's in analyzing fringe patterns is presented. The implementation of the second-order loop in real time on a commercial parallel image processing system is described. Fringe patterns are grabbed and processed, and the resultant phase maps are displayed concurrently.

Phase-jitter dynamics of digital phase-locked loops: Part II

For pt.I see ibid., vol.46, pp.545-58 (1999). In Part I, we examined the unwanted phase jitter that occurs in digital phase-locked loops due to frequency quantization in a number-controlled oscillator. In the treatment of the second-order loop that made up the bulk of that work, we concentrated on the case of a sinusoidal input whose frequency, normalized to the quantization increment, is rational with a low denominator, but not an integer. In this paper we extend that analysis to handle all input frequencies. We will study in two-dimensional state space the dynamics of the map modeling the second order loop, and examine the location and nature of the steady-state behavior of the system. The analysis adds to the insights into digital phase locked loops produced by our previous work, and also reveals properties of interest to students of nonlinear dynamics. We will see in particular that the jitter width significantly increases close to the low-denominator rational frequencies.

Non-autonomous second-order chaotic circuit with comparator

A novel non-autonomous nonlinear oscillator is suggested. The oscillator contains the integrator based second-order RC resonance loop, a comparator employed as a nonlinear device, and a buffer. When externally forced with periodic signal Asin(/spl omega//sub d/f), it exhibits a chaotic response in the certain bands of A and /spl omega//sub d/ parameters.

Design of MOS-translinear Multiplier/Dividers in Analog VLSI

A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-μm CMOS process, are provided in order to verify the correctness of the proposed approach.

Reducing the PLL noise bandwidth by a digital split-loop

The advantages of the split-loop technique for analog phase-locked loops with a time delay are well known. In this paper, it will be shown that the digital counterpart of the split-loop offers an additional advantage, since the first oscillator can already convert the incoming signal down into the baseband. If this signal is used for the demodulation, the noise bandwidth of the loop is reduced significantly without changing the acquisition and tracking ranges. The resulting noise bandwidth is calculated and compared to a conventional digital high-gain second-order loop. Furthermore, the effect on the BER performance for DQPSK modulation is simulated.

Shilnikov orbits in an autonomous third-order chaotic phase-locked loop

In this work we investigate the Shilnikov homoclinic bifurcation in a new type of phase-locked loop (PLL) having a second-order loop filter. This system can be represented as a third-order autonomous system with piecewise-linear characteristics. By using piecewise-linear analysis, bifurcation equations for many types of homoclinic orbits are derived. Solving these equations gives many Shilnikov-type homoclinic orbits. We present bifurcation diagrams for the homoclinic orbits in the gain (K/sub 0/) versus detuning (/spl Delta//spl omega/) plane. Finally, we demonstrate the role of the homoclinic orbits in the global bifurcation of attractors both by computer simulation and experiments,.

Performance of digital code tracking loops for direct-sequence spread-spectrum signals in mobile radio channels

The performance of first- and second-order non-coherent digital delay lock loops (DDLL) for direct-sequence spread-spectrum (DS-SS) signals is investigated in the mobile radio environment. The mobile radio channel is first characterized by Rayleigh fading and Doppler shift. A closed-form expression for the timing error transition probability density function of the Chapman-Kolmogorov (C-K) equation is proposed. The probability density function of the steady-state timing error for the first- and second-order DDLL is obtained by solving the C-K equation numerically, and the results are confirmed by computer simulations. Furthermore, the mean time to lose lock (MTLL) of the first-order loop is evaluated, and some numerical results and simulation results are reported. Finally, the steady-state timing error and MTLL of the first-order loop for DS-SS signals in the log-normal fading environment are also presented, and the results are compared with those of Rayleigh and AWGN channels.

An automatic gain control architecture for SONET OC-3 VLSI

This work presents a synchronized feedback-type automatic gain control (AGC) architecture for SONET (synchronous optical network) OC-3 system which is suitable for scaled BJT or CMOS VLSI implementation. In this architecture, a second-order loop is utilized instead of a conventional loop, and a convenient methodology is presented for calculating the parameters of the AGC. Simulation results using micromodels in the HSPICE environment indicate that for a 20 dB dynamic range of input 77.76 MHz sinusoidal signal, the architecture yields an 80 kHz loop bandwidth and a constant 1 V/sub pp/ output magnitude.

Stack filter phase lock loops

The basic design of a general purpose digital phase lock loop is improved upon by incorporating a stack filter into the feedback path of the loop. The addition of a stack filter provides enhanced performance in the presence of impulsive noise while providing the same steady-state performance of a conventional digital phase lock loop. Both first- and second-order loops benefit from the addition of stack filters. The particular case of using a median filter is examined in detail. In addition, a linear regression model is used in conjuction with the absolute error criterion to provide robust estimates of phase and frequency. The resulting loop structure incorporates median and weighted median filters in its feedback path.

Analysis of a charge-pump PLL: a new model

A new model for the analysis of a second-order charge-pump phase-locked loop (PLL) is described. This model uses a set of difference equations in two well-chosen state variables. It allows one to model exactly the transient behavior of the PLL, even if the loop is out of lock. Theoretical stability and overload limits are determined. A continuous-time approximation is derived. Its validity is verified by simulation examples.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On optimal AGC structure for direct sequence spread spectrum PN-code tracking

The performance of various AGC configurations, namely presync, postsync and an adaptive (optimal) AGC are analyzed at and above the threshold for a coherent pseudonoise (PN) second-order code tracking loop (delay lock loop, DLL) used in direct sequence spread spectrum systems. At and near the threshold the criterion of performance is chosen to be the mean time to lose lock (MTLL). Applying a recently presented method, analytic expressions for the loop performance are given, and the threshold degradation caused by Doppler rate is derived. Above the threshold, the "worst case" steady state tracking error is chosen as the loop index of performance. The performance and structure of the "globally-optimal" AGC (at and above the threshold region) is derived, and a simplified, practical and still close to optimum adaptive AGC is presented. This configuration can easily be realized by digitally controlling the AGC parameters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Comparison between first-order and second-order optical phase-lock loops

A comparison between the performance of modified first-order and second-order optical phase-lock loops (OPLL's) is made, revealing that the modified first-order loop offers better performance when long loop delay time is present and a wide bandwidth loop filter is used. The introduction of a 10 dB gain margin from the critical gain can be used to keep the damping close to that expected when the delay time is negligible. If OPLL design is optimized for this gain margin and 5 MHz linewidth lasers are used, the increase in the phase-error variance with delay time is 54 rad <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /μs for a modified first-order and 80 rad <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /μs for a second-order loop, confirming that modified first-order loops are less sensitive to loop delay.