Second-order Loop Research Articles

A Novel FLL-Assisted PLL With Fuzzy Control for TC-OFDM Carrier Signal Tracking

The time and code division-orthogonal frequency-division multiplexing (TC-OFDM) signal is a promising wireless positioning signal, which multiplexes the China mobile multimedia broadcasting signal and pseudorandom noise codes in the same frequency band. The drastic change of carrier-to-noise ratio can increase carrier tracking error of the TC-OFDM receiver and may lead to the loss of lock. To address this problem, a novel frequency-lock loop (FLL)-assisted phase-lock loop (PLL) with fuzzy control is proposed, and the effect of signal strength on the carrier tracking loop is analyzed. The proposed algorithm uses the outputs of the phase and frequency discriminator as measured residuals of the Kalman filter (KF), and a KF-based second-order FLL-assisted three-order PLL carrier tracking loop is designed. Moreover, fuzzy control is applied to the designed loop. It can automatically switch between pure KF-based PLL, pure KF-based FLL, and KF-based FLL-assisted PLL, and automatically adjust the noise bandwidth. Simulation and experimental results show that, compared with the existing carrier tracking algorithms, the proposed algorithm can effectively avoid the divergence of the tracking loop and improve the robustness of the TC-OFDM receiver.

Parallel Inhibitory and Excitatory Trigemino-Facial Feedback Circuitry for Reflexive Vibrissa Movement

Animals employ active touch to optimize the acuity of their tactile sensors. Prior experimental results and models lead to the hypothesis that sensory inputs are used in a recurrent manner to tune the position of the sensors. A combination of electrophysiology, intersectional genetic viral labeling and manipulation, and classical tracing allowed us to identify second-order sensorimotor loops that control vibrissa movements by rodents. Facial motoneurons that drive intrinsic muscles to protract the vibrissae receive a short latency inhibitory input, followed by synaptic excitation, from neurons located in the oralis division of the trigeminal sensory complex. In contrast, motoneurons that retract the mystacial pad and indirectly retract the vibrissae receive only excitatory input from interpolaris cellsthat further project to the thalamus. Silencing this feedback alters retraction. The observed pull-push circuit at the lowest-level sensorimotor loop provides a mechanism for the rapid modulation ofvibrissa touch during exploration of peri-personal space.

A monolithic K-band phase-locked loop for microwave radar application**Project supported by the National High-Tech Research and Development Program of China (No. 2013AA014101).

A monolithic K-band phase-locked loop (PLL) for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-controlled oscillator (VCO) achieves a tuning range of 18.4 to 23.3 GHz and reduced phase noise. Two cascaded current-mode logic (CML) divide-by-two frequency prescalers are implemented to bridge the frequency gap, in which inductor peaking technique is used in the first stage to further boost allowable input frequency. Six-stage TSPC divider chain is used to provide programmable division ratio from 64 to 127, and a second-order passive loop filter with 825 kHz bandwidth is also integrated on-chip to minimize required external components. The proposed PLL needs only approximately 18.2 μs settling time, and achieves a wide tuning range from 18.4 to 23.3 GHz, with a typical output power of −0.84 dBm and phase noise of −91.92 dBc/Hz @ 1 MHz. The chip is implemented in TSMC 65 nm CMOS process, and occupies an area of 0.56 mm2 without pads under a 1.2 V single voltage supply.

On the Stability of Charge-Pump Phase-Locked Loops

This paper employs a time-variant model to determine the exact small-signal loop transmission of second-order charge-pump phased-locked loops. The model predicts that a loop bandwidth of close to half the input frequency can be achieved. The large-signal behavior is also analyzed and two modes of oscillation are identified. The results are confirmed by means of circuit simulations.

A DPLL Method Applied to Clock Steering

Several closed-loop control methods have dealt with clock steering problems, but parameters for these methods are not easy to choose. In this paper, we propose a new clock steering method, which uses a second-order type-2 digital phase-locked loop (DPLL) equivalent to a two-state Kalman filter with a delay. We derive the approximate expressions of the steady-state Kalman gains, which are equivalent to the DPLL gains. Then, we derive the transfer functions of the approximate DPLL. A brief and effective approach to choosing a parameter is also proposed. Simulation results show that the performance of the time steering error and the frequency stability is quite desirable, and can meet the requirements of generating a local representation of coordinated universal time or a global navigation satellite system time.

5.2 mW 61 dB SNDR 15 MHz Bandwidth CT ΔΣModulator Using Single Operational Amplifier and Single Feedback DAC

We propose an architecture that reduces the power consumption and active area of such a modulator through a reduction in the number of active components and a simplification of the topology. The proposed architecture reduces the power consumption and active area by reducing the number of active components and simplifying the modulator topology. A novel second-order loop filter that uses a single operational amplifier resonator reduces the number of active elements and enhances the controllability of the transfer function. A trapezoidal-shape half-delayed return-to-zero feedback DAC eliminates the loop-delay compensation circuitry and improves pulse-delay sensitivity. These simple features of the modulator allow higher frequency operation and more design flexibility. Implemented in a 130 nm CMOS technology, the prototype modulator occupies an active area of 0.098 mm2 and consumes 5.23 mW power from a 1.2 V supply. It achieves a dynamic range of 62 dB and a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz. The figure-of-merit of the modulator is 191 fJ/conversion-step.

A 300-mV ΔΣ Modulator Using a Gain-Enhanced, Inverter-Based Amplifier for Medical Implant Devices

An ultra-low-voltage low-power switched-capacitor (SC) delta-sigma (ΔΣ) modulator running at a supply voltage as low as 300 mV is presented for biomedical implant devices, e.g., cardiac pacemakers. To reduce the supply voltage, an inverter-based amplifier is used in the integrators, whose DC gain and gain-bandwidth (GBW) are boosted by a simple current-mirror output stage. The full input-feedforward loop topology offers low integrators internal swing, supporting ultra-low-voltage operation. To demonstrate the concept, a second-order loop topology was chosen. The entire modulator operates reliably against process, voltage and temperature (PVT) variations from a 300 mV ± 10% supply voltage only, while the switches are driven by a charge pump clock boosting scheme. Designed in a 65 nm CMOS technology and clocked at 256 kHz, the simulation results show that the modulator can achieve a 64.4 dB signal-to-noise ratio (SNR) and a 60.7 dB signal-to-noise and distortion ratio (SNDR) over a 1.0 kHz signal bandwidth while consuming 0.85 μW of power.

English

This paper presents the analysis and simulation of second-order charge pump phase-locked loop by applying the phase step at the entrance and calculates the fast lock and transient time and the effects of loop parameters such as capacitor, resistor, loo filter current, control voltage oscillator at the at the fast lock investigated and plotted in the diagram at transition time. All simulation was performed by matlab software.

Stability analysis of optical phase-locked loop in the presence of non-negligible loop propagation delay

The impact of loop-delay on the phase margin of first- and second-order optical phase-locked loop is analyzed. Analytical expressions of the phase margin for first- and second-order optical phase-locked loop with two different loop filter configurations are presented. It is found that to achieve practical phase margin on the order of 30 – 60° with damping factor ξ=1, the normalized loop propagation delay ωnτ (where, ωn is the loop natural frequency and τ is the loop propagation delay) must be kept with in the range 0.37 – 0.15 and 0.25 – 0.10 for active low-pass and modified first-order loop filter, respectively. Also, the relative stability of modified optical phase-locked loop having an additional arrangement of phase modulation is analyzed and the effect of external phase control on the phase margin is reported in the presence of non-negligible loop propagation delay.

On the use of tracking loops for low-complexity multi-path channel estimation in OFDM systems

This paper treats pilot aided multi-path channel estimation with tracking loops for OFDM systems under slow to moderate fading conditions. Recent works have presented theoretical results for the tuning of second-order and third-order tracking loops in the particular context of Jakes׳s Doppler spectrum channel. The method for getting the loop coefficients resorted either to the use of a given constraint, which made the obtained coefficients sub-optimal, or was obtained in part by simulations. Here, we perform a global optimization of the coefficients without constraints to get the optimal coefficients, and analytical formulas are provided. One remarkable result of this optimization is that only the natural frequency depends on the transmission parameters, i.e., the channel Doppler spectrum, the power delay profile, and the noise variance. Consequently, only one parameter has to be tuned. Moreover, asymptotic performance is formulated in a more general way as a function of the 2rth moments of the Doppler spectrum (r is the loop order). Hence, all our derivations are usable for any Doppler spectrum and are not specific to Jakes׳s Doppler spectrum. A complete table sums up for the three orders of the theoretical results of the optimal coefficients together with the asymptotic performance. The performance is also compared with that of the asymptotic Kalman filter.

Tunable second-order, birefringent interferometric filter for dynamic chirp management

A tunable second-order birefringent interferometric filter for minimizing signal degradation due to chirping in modulated lasers is proposed and demonstrated. Compared with commonly used filters with standard Gaussian and super-Gaussian filter profiles, a high-order loop mirror filter of similar bandwidth has a much sharper filtering slope. This provides more effective, specific filtering of desired components of a signal’s spectrum, minimizing signal power loss experienced during filtering. The steep filtering slope also provides significant improvement in transmission performance even with a change in data rate. Thus, the same filter can be reused for different bit rates. Furthermore, the tuning capability of the loop mirror filter enables good transmission performance when a variation in signal wavelength is present. Moreover, the unique, periodic filter profile potentially enables chirp management for multiple channels at different wavelengths. We experimentally verify the chirp management performance of the second-order birefringent loop mirror filter. Improvements to the transmission performance of both directly modulated lasers and electro-absorption modulated lasers at different data rates are achieved.

Single op‐amp second‐order loop filter for continuous‐time delta–sigma modulators

A second-order loop filter (LF) that uses a single op-amp resonator is presented for continuous-time delta–sigma modulators. The proposed technique improves the power and area efficiency of the LF and enhances the controllability of the transfer function and the resonating condition by providing a new RC network. A second-order modulator has been designed to confirm the effectiveness of the proposed scheme. Implemented in a 130 nm CMOS, the prototype modulator occupies an active area of 0.098 mm2 and consumes 5.23 mW power from a 1.2 V supply. It achieves a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz.

A modified code tracking loop based on dual structure

A modified code tracking loop for tracking the pseudo-random noise code in direct sequence spread spectrum signal is proposed. The modified loop differs from the typical through imposing a dual structure which incorporates a coarse loop with large loop parameters and an accurate loop with small loop parameters. The expression of the convergence time for the second-order delay-locked loop (DLL) is derived to measure the time of the convergence process. Two concepts, accuracy improvement and time improvement are defined to exhibit the performance enhancement of the modified loop. Simulation results show that the proposed method can realize a better trade-off between tracking accuracy and convergence time in the whole simulated carrier-to-noise ratio range. Also, the robustness of the modified loop is verified through eliminating the second convergence process which is regarded as the worst issue in the parameter-switching DLL.

Mathematical model of the phase-locked loop with a current detector

The mathematical model of the pulses phase-locked loop (PLL) with a frequency-phase detector and a current pump, which is represented as a set of difference and transcendental equations and relies on the dynamics of the given deterministic system (in the general case, an arbitrary-order loop filter) described by an automation with a finite number of components and combined differential equations, is examined. An algorithm describing the operation of the in-lock indicator of the given PLL is proposed. The particular cases of the first- and second-order loop filters are discussed. PLL simulation is performed under transient conditions.

BER Performance of Coherent Optical Communications Systems Employing Monolithic Tunable Lasers With Excess Phase Noise

We analyze the bit error rate (BER) performance of optical coherent communication systems employing multi-section monolithic tunable lasers with large excess phase noise. The BER of the coherent system utilizing a second-order decision-directed digital phase-locked loop (DD-PLL) for phase tracking was computed numerically. Experimental results have also been demonstrated with a 16-quadratic-amplitude modulation coherent system deploying a sampled-grating distributed Bragg reflector laser at 16 Gbaud that confirms the performance of the second-order DD-PLL in tracking the excess phase noise.

A RE-CONFIGURABLE ARCHITECTURE FOR SWITCHED CAPACITOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION

A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope.

A 81-dB Dynamic Range 16-MHz Bandwidth <formula formulatype="inline"><tex Notation="TeX">$\Delta\Sigma$</tex></formula> Modulator Using Background Calibration

A fourth-order discrete-time delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. It combines low-complexity circuits and digital calibrations to achieve high speed and high performance. The DSM is a cascade of two second-order loops. It has a sampling rate of 1.1 GHz and an input bandwidth of 16.67 MHz with an oversampling ratio of 33. It uses high-speed opamps with a dc gain of only 10. Two different types of digital calibrations are used. We first employ the integrator leakage calibration to correct the poles of the integrators. We then apply the noise leakage calibration to minimize the leaking quantization noise from the first loop. The noise leakage calibration also relaxes the component-matching requirements. Both calibrations can operate in the background without interrupting the normal DSM operation. The chip's measured signal-to-noise-and-distortion ratio and dynamic range are 74.32 and 81 dB, respectively. The chip consumes 94 mW from a 1 -V supply. The active area is 0.33 × 0.58 mm2.

Low-voltage reduced complexity cells for MOS translinear loops

A novel bias scheme for realizing low-voltage second-order translinear loops is introduced in this paper. The provided design examples include current geometric-mean, squarer/divider, and multiplier/divider cells. The performed comparison shows that the derived analog signal processing blocks offer reduced circuit complexity and improved performance, compared with the corresponding already published counterparts.

Stability Analysis of Bang-Bang Phase-Locked Loops for Clock and Data Recovery Systems

Bang-bang phase detector-based phase-locked loops (PLLs) with first- and second-order analog loop filters (LFs) are considered. Discrete-time (DT) models are presented for the bang-bang PLLs (BPLLs) in the presence of loop delays. The DT models show that the delay introduces an additional pole at in the DT open-loop transfer function. The pole is of multiple order proportional to the delay, indicating that the system is prone to be unstable. Stability analysis of the BPLLs is conducted to derive stability conditions, taking advantage of the radius of curvature technique to facilitate numerical calculations involved. It is shown that the stability conditions depend on the LF parameters, the loop delay, and the update time of the BPLLs.

Analytical Computation of Mean Time to Lose Lock for Langevin Delay-Locked Loops

This paper presents a novel method for the analytical mean time to lose lock (MTLL) computation of coherent second-order Langevin delay-locked loops (DLLs). Analytical MTLL computation is a key task for DLLs, since the computational complexity of numerical MTLL simulations is far too high in many operating ranges of the second-order Langevin DLLs. To obtain the crucial MTLL values analytically without simulations, we rewrite the Langevin stochastic differential equation (SDE) as a vector-valued Ornstein-Uhlenbeck (OU) SDE. It includes a Gaussian noise term, which yields as a solution of the vector-valued OU SDE a time-variant Gaussian distribution. Thus, the complementary error function yields the loss of lock probability and thereby the MTLL. If we replace the complementary error functions by suitable exponential approximations, we obtain a simple MTLL expression with an exponential function as dominant term. The simple exponential MTLL expression yields the optimum loop parameters corresponding to the maximum MTLL. Simulation results confirm that the optimum loop parameters corresponding to our analytical MTLL computation method and to the simplified exponential approximation coincide. Besides the crucial analytical MTLL results, the OU random processes yield additionally the likewise crucial analytical jitter results.