Schottky Barrier Gate Research Articles

Schottky-barrier field-effect transistors of 3C-SiC

Schottky-barrier field-effect transistors have been fabricated first from 3C-type SiC. Al-doped p-type and nondoped n-type 3C-SiC epilayers were successively grown on p-type Si substrates by chemical vapor deposition. Au and Al electrodes were used for Schottky-barrier gate contacts and ohmic (source and drain) contacts for n-type SiC. Transistor operation was observed for the first time for the field-effect transistors of 3C-SiC.

GaAs/Ga0.47In0.53As lattice-mismatched Schottky barrier gates: Influence of misfit dislocations on reverse leakage currents

Epitaxial GaAs has been grown on Ga0.47In0.53As by molecular beam epitaxy to form a lattice-mismatched Schottky barrier gate for field-effect transistor applications. The study of cross-sectional transmission electron microscopy shows that the misfit dislocations accommodating the 3.7% lattice mismatch between these two materials are confined in a GaAs interfacial layer of 300–400-Å thickness. As a result of significant reduction in dislocation densities, Schottky barrier gates made on a sample having a 960-Å-thick GaAs layer exhibit reverse leakage currents two orders of magnitude lower than those made on a sample with a 580-Å-thick GaAs layer. This approach looks promising for fabricating Ga0.47In0.53As field-effect transistors for optoelectronic integration as well as high-speed logic applications.

Schottky-barrier mobility profiling measurements with gate-current corrections

The Schottky-barrier gate of a field-effect transistor (FET) provides an ideal means of mobility profiling by the geometric-magnetoresistance method. This technique has advantages over the more common capacitance-conductance method, because of a near independence of parasitic resistances. However, present models do not take account of finite gate current, which is an appreciable problem in forward bias. We develop a model which properly includes gate current corrections as well as parasitic resistances and apply this model to GaAs MESFETs, even in cases for which the gate current is on the order of the source-drain current. The allowance of forward bias makes possible accurate mobility profiles much closer to the surface than before.

Temperature dependence of FET properties for Cr-doped and LEC semi-insulating GaAs substrates

The temperature dependence of carrier concentration and mobility profiles is measured on Schottky-barrier gate FET's formed by Si implantation into intentionally Cr-doped Czochralski-grown semi-insulating GaAs substrates and LEC semi-insulating GaAs substrates. The effective depth of the channel implant is at least 100 nm shallower for Cr-doped substrates than it is for LEC substrates. Carrier mobilities are higher for LEC substrates; at low temperature, mobility is higher at the channel-substrate interface than it is nearer the surface. Devices on both types of substrates show free-carrier trapping effects between 160 and 225 K. For LEC substrates, traps are on the channel side of the active channel-substrate interface. For Cr-doped substrates, observation of traps depends on biasing the FET beyond pinchoff; traps are on the substrate side of the channel-substrate interface.

Amorphous-Silicon gate GaAs FET's

Silicon-germanium-boron ternary amorphous alloy has been applied to GaAs FET as a gate contact material. A good Schottky contact with a barrier height as large as 0.94 V has been realized. Schottky-barrier gate GaAs FET's fabricated using the amorphous film as a gate contact layer exhibit excellent normally off FET characteristics of a large saturated drain curent, which has never been attained by conventional GaAs MESFET's.

An enhancement mode Schottky barrier gate charge-coupled device on a high electron mobility transistor structure

An enhancement mode charge-coupled device (CCD) was fabricated for the first time on a selectively doped n-GaAlAs/p−-GaAs heterojunction structure. A dramatic improvement in charge-transfer efficiency (CTE) was observed as the CCD is cooled from 300 to 77 °K. This improvement is attributed to the increase in low field electron mobility of the two-dimensional electron gas at low temperature. Charge capacity was also found to increase upon cooling. The cause is not well understood. An optimized structure for high-speed CCD is proposed.

Modulation-doped AlGaAs/GaAs heterostructure charge coupled devices

The advantages of the modulation-doped heterostructure over conventional materials structures for high speed CCD applications are outlined. In addition, the first demonstration of charge transfer in a modulation-doped AlGaAs/GaAs heterojunction is reported. A ten cell, three phase Schottky barrier gate CCD was fabricated using this structure and operated as a shift register. The details of the device fabrication and characterization are presented.

Normally-on and normally-off camel diode gate GaAs field effect transistors for large scale integration

Normally-off and normally-on camel gate GaAs field effect transistors have been fabricated from structures grown by molecular beam epitaxy. These new devices use a camel diode gate formed from n+ and p+ layers instead of a Schottky barrier gate as used in metal-semiconductor field effect transistors. The camel diode gate provides these devices with several advantages over metal-semiconductor field effect transistors, including elimination of the metallurgical difficulties of the metal-semiconductor contact, relatively easy adjustment of the built-in voltage, and the potential for improved reliability in adverse environments and under conditions of high power dissipation. Fabrication of these devices does not require precision etching, making them compatible with large scale integrated circuit technology. Fabricated devices have yielded transconductances of 80 ms/mm in long channel (3 μm gate length) normally-on and normally-off field effect transistors and of 120 ms/mm in short channel (1 μm gate length) normally-on field effect transistors. Significantly improved gate-drain breakdown voltages and, in devices with AlxGa1−xAs buffer layers, excellent saturation characteristics have been observed. A simple theory providing analytical expressions describing the performance of normally-on and normally-off camel gate field effect transistors has been developed and good agreement with experiment has been obtained.

A novel camel diode gate GaAs FET

A novel device utilizing the "camel diode" in place of a Schottky barrier gate has been demonstrated in GaAs grown by molecular beam epitaxy (MBE). The devices have a 7.5 µm channel length, 3 µm gate length, and a 280 µm gate width. The layers from which the devices are fabricated consist of a 0.15 µm GaAs layer doped to a level of 1.5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> to form the channel, and a 100 Å p+GaAs and a 400 Å n+ region to form the gate. Because of the long gate length, the electron velocity does not reach saturation, thus a transconductance of 80 mS/mm is obtained. A simple theory describing the device operation has also been developed.

Measurement of fluctuations affecting domain formation in transferred-electron logic devices using picosecond optical pulses

Picosecond optical pulses have been used to bias the gate region of a transferred-electron logic device to the vicinity of the threshold for domain formation. Single domains with rise and fall times of less than 50 ps are produced when the device is illuminated between the cathode and Schottky-barrier gate electrodes. The probability of domain generation is found to vary with optical intensity and applied bias voltage. Fitting a model of the effects of thermal carrier density fluctuations to these data yields a value for the rms fluctuating electric field component affecting domain formation of 123±14 V/cm in the devices studied.

Materials options for field-effect transistors

The evolution of monolithic high-speed digital and analog microwave field-effect transistor (FET) technologies is linked inextricably to synthesis, control, and understanding of the properties of the semiconducting binary, ternary, and quaternary III–V compounds. It is also linked to the application and use of ion implantation as a pivotal corollary process. Selection of a Schottky barrier, insulated-gated or heterojunction gate technology defines, in part, the options available in terms of the fundamental surface and interfacial properties of these compounds. Others concern electron transport processes under surface depletion, inversion and accumulation regimes, and the solution of metallurgical problems involved in the formation of ohmic and blocking contacts, the free carrier concentration and mobility profiles, and their stability as a function of process variables used to make such FET.

Continuously clocked 1 GHz GaAs CCD

The continuously clocked operation of a buried channel, Schottky-barrier gate GaAs CCD is described at clock frequencies in excess of 1 GHz. A charge transfer efficiency of >0.9999 per transfer is measured at low frequency and 0.994 per transfer at 1 GHz. It is postulated that the high frequency transfer efficiency is a limitation of the equipment.

Degradation of GaAs MESFETS in 18 megohm-cm H2O

Rinsing GaAs MESFETs under illumination in 18 megohm-cm H <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O is shown to rapidly degrade the dc characteristics of the device. H <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O etches a trough around the Schottky barrier gate electrode with an etch rate of at least 22 Å/min. Formation of the trough significantly increases the parasitic resistances of the MESFET.

Low-power gigabit logic by GaAs SSFL

Experimental results on improved GaAs Schottky-barrier coupled Schottky-barrier gate FET logic (SSFL) are reported. A 13-stage ring oscillator, gate dimensions 1.2×20 μm2, showed tpd=55 ps/gate at P=3.5 mW/gate. Also, a divide-by-two circuit was confirmed, starting normal operation from a single initialisation pulse.

Schottky-barrier coupled Schottky-barrier gate GaAs FET logic

First accounts of the experimental details of Schottky-barrier gate GaAs FET logic circuits that use a Schottky barrier for interstage level shifting are described. Tpd and power consumption of an inverter in an 11-stage ring oscillator showed 120 ps and 12 mW, respectively, with FET gate dimensions of 3×50 μm2.

Speed-power property of GaAs Schottky-barrier coupled Schottky-barrier gate FET logic

Results from computer simulation of a GaAs Schottky-barrier coupled Schottky-barrier gate FET logic inverter of different values of Vp are reported. It is shown that the inverter of gate dimensions 1 × 10 μm−2, Vp = −1 V, and fan-out of one has tpd = 17 ps and P = 1 mW, and that still lower power consumption is possible with smaller |Vp|. Problems associated with small |Vp| are also discussed.

Problems and prospects of compound semiconductor field-effect transistors

The application of binary, ternary, and quaternary semiconducting III– V compounds for high frequency field-effect transistors (FETs) and microwave integrated circuits (ICs) presents hitherto unavailable options and challenging problems which arise from the inherent bulk and surface properties of these materials and of the interfaces between them and metal or dielectric overlayers. Although the depletion-mode (normally-on) Schottky barrier gate GaAs transistor is the older and, at this stage, more advanced technology, alternative approaches based primarily on insulated gate FETs and other materials such as InP, InxGa1−xAs, and InxGa1−xAsyP1−y have been demonstrated to have important advantages for enhancement type (normally-off) as well as depletion- and inversion-mode insulated gate FETs, a potential high frequency analog of the lower frequency silicon MOS technology. The problems and prospects of such devices and structures as well as those of a variety of Schottky barrier gate and heterojunction gate transistors will be discussed in terms of their surface and interface properties.

GaAs and related heterojunction charge-coupled devices

A Schottky-barrier gate GaAs charge-coupled device (CCD) technology is described. Experimental devices fabricated in this technology have operated with charge transfer efficiency >0.999/transfer and-have operated at clock frequency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f_{cl} = 500</tex> MHz. Implications of this technology in high-speed signal processing and in visible and near-infrared imaging are discussed.

A 500-MHz GaAs charge-coupled device

The higher electron mobility in GaAs relative to silicon makes it possible to design an ultra-high-Speed charge-coupled device. A buried-channel Schottky barrier gate GaAs charge-coupled device (CCD) is described which has been operated at up to 500 MHz clock frequency. The transit-time-limited upper clock frequency in this device is predicted to exceed 5 GHz.

Reduced Geometry GaAs CCD for High Speed Signal Processing

A Schottky barrier gate GaAs CCD is described with high transfer efficiency (>0.999/transfer) and ultra-high speed (fcl.∼500 MHz) operation. Predictions for maximum achievable clock frequency are made, and possible signal processing applications are discussed.