Scan Flip-flops Research Articles

Access-in-turn test architecture for low-power test application

ABSTRACTThis paper presents a novel access-in-turn test architecture (AIT-TA) for testing of very large scale integrated (VLSI) designs. In the proposed scheme, each scan cell in a chain receives test data from shift-in line in turn while pushing its test response to the shift-out line. It solves the power problem of conventional scan architecture to a great extent and suppresses significantly the switching activity during shift and capture operation with acceptable hardware overhead. Thus, it can help to implement the test at much higher operation frequencies resulting shorter test application time. The proposed test approach enhances the architecture of conventional scan flip-flops and backward compatible with existing test pattern generation and simulation techniques. Experimental results obtained for some larger ISCAS’89 and ITC’99 benchmark circuits illustrate effectiveness of the proposed low-power test application scheme.

バウンダリスキャンテスト機構を用いたはんだ接合部の電気検査法とその組込型検査回路

バウンダリスキャンテスト機構を用いたはんだ接合部の電気検査法とその組込型検査回路

New Design of Scan Flip-Flop to Increase Speed and Reduce Power Consumption

In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented, in which short circuit current is controlled. Switching activity is decreased to reduce the consumed power of the scan flip-flop. Also, the total number of transistors through the path from input to the output is reduced and so the delay of the proposed scan flip-flop is decreased. Simulation results show 12% and 29% reduction in power consumption and delay of the proposed scan flip-flop, respectively. The results are given by comparison of our work with other scan flip-flops at 50% data switching activity.

MTJ-Based State Retentive Flip-Flop With Enhanced-Scan Capability to Sustain Sudden Power Failure

We present two non-volatile flip-flops (NVFFs) that incorporate magnetic tunnel junctions (MTJ) to ensure fast data storage and restoration from intentional and unintentional power outages. The proposed designs also facilitate enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The proposed NVFF eliminates additional write drivers, and can operate at up to 2 GHz at 1.1 V, with 0.55 pJ of energy consumption in 22 nm predictive technology. We also address the issue of write asymmetry of MTJ through careful transistor upsizing to achieve near uniform write latency. A data-dependent power gating technique is proposed to mitigate the high static current during retention and back-to-back writing of the identical input data. The proposed gated NVFF achieves several orders of magnitude energy saving at the expense of 1.56X area compared to a standard enhanced scan flip-flop.

Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification

A manufacture-ready layout is vulnerable to misappropriation when it is either fabricated as a chip in a fabrication facility, or reused in a system-on-chip house. We propose an intellectual property protection (IPP) scheme IPP_MRL for protection of m anufacture- r eady l ayout against unauthorized reuse and inclusion of Trojans. The IPP_MRL inserts watermarks in the layout according to designer’s signature with an effect of tuning the delays at selected scan flip-flops. Certain dummy fills are reoriented in the neighborhood of selected net segments and it causes fine tuning of delay; certain other selected net segments are resized for coarse change in delay. The IPP_MRL not only verifies the watermark in the layout, but also captures its effect as delay fault-induced responses from the packaged chips, fabricated from the watermarked layout, by applying a faster test clock. Due to the controlled effect of watermarking on delay, responses are resilient against process and temperature variation, but capable of detecting hardware Trojan. The method is adaptive to device aging. The results for ISCAS’85 and ISCAS’89 benchmark circuits show that the overhead of watermarking on circuit delay is less than 0.05% and the probability of true false or false true can be at most $\sim 10^{-6}$ .

A Novel Scan Architecture for Low Power Scan-Based Testing

Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introduce spurious switching activities in the combinational logic. In this paper, we propose a novel area-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and combinational part during shift mode. In the proposed gating scan structure, conventional master/slave scan flip-flop has been modified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in combinational logic during shift mode. The new gating scan cells also mitigate the number of transitions during shift and capture cycles. Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power during capture cycle. Simulation results have shown that the proposed gating scan cell saves 28.17% total average power compared to conventional scan cell that has no gating logic and up to 44.79% compared to one of the most common existing gating architectures.

Techniques for Low Power and Area Optimized VLSI Testing using Novel Scan Flip-Flop

consumption of any circuit is high during test mode than its normal mode of functioning. Different techniques are proposed to reduce the test power. This paper presents the consolidated research work carried to reduce the test power. Usually the power dissipation is due to the sequential and combinational elements presents in the circuit. In this paper we proposed different methodologies and they are at cell level optimization to reduce test power. The structure of the scan flip-flop is modified to reduce the power due to sequential elements and gating techniques are proposed to reduce power duo to combinational elements. The proposed methodologies are implemented on the different ISCAS benchmark circuit and the experimental results were observed. These experimental results showed that our proposed methods reduced the switching power by 44.58-61.97%including the proposed gating technique, area by 30-45% and the test time by 50%.

Reuse-Based Optimization for Prebond and Post-Bond Testing of 3-D-Stacked ICs

Three-dimensional (3-D) stacking of integrated circuits (ICs) using through-silicon-vias (TSVs) is a promising integration platform for next-generation ICs. Since TSVs are not fully accessible prior to bonding, it is difficult to test the combinational logic between scan flip-flops and TSVs at a prebond stage. In order to increase testability, it has been advocated that wrapper cells (WC) be added at both ends of a TSV. However, a drawback of WC is that they incur area overhead and lead to higher latency and performance degradation on functional paths. Prior work proposed the reuse of scan cells to achieve high testability, thereby reducing the number of WC that need to be inserted; however, practical timing considerations were overlooked and the number of inserted WC was still high. We show that the general problem of minimizing the WC is equivalent to the graph-theoretic minimum clique-partitioning problem, and is therefore NP-hard. We adopt efficient heuristic methods to solve the problem and describe a timing-guided and layout-aware solution. We evaluate the heuristic methods using an exact solution technique based on integer linear programming. We also present design-for-test optimization technique to leverage the reuse-based method during post-bond testing. Results are presented for 3-D-stack implementations of the ITC'99 and the OpenCore benchmark circuits.

Utilizing Circuit Structure for Scan Chain Diagnosis

Scan chain diagnosis has become a critical issue to yield loss in modern technology. In this paper, we present a scan chain partitioning algorithm and a scan chain reordering algorithm to improve scan chain fault diagnosis resolution. In our scan chain partition algorithm, we take into consideration not only logic dependency but also the controllability between scan flip-flops. After the partition step, the ordering of scan cells is performed to decrease the range of suspect faulty scan cells by a bipartite matching reordering algorithm. The experimental results show that our method can reduce the number of suspect scan cells from 378-31 to at most 3 for most cases of ITC'99 benchmarks.

Optimal Hamming Distance Model for Crypto Cores against Side Channel Threats

Microelectronic crypto devices contain intellectual property like secret data to be protected against side channel attack. Scan chain based attacks come under the category of side channel attack where the hackers attack a scan path through observing and comparing the relationship between intermediate hamming distances values for different test vector patterns. Hence our novel hamming model should overcome the scan based attack and should not give any correlation relationship in hamming distance by providing the similar intermediate values for all test vector patterns which are obtained through an optimal way of inserting Optimal Scan Flip Flop (OSFF) randomly to the scan path chain. Implementation of our proposed integrated circuits is written in Verilog and synthesised with XILINX Spartan III FPGA. The report is compared with Robust Scan Flip Flop (RFSS) hamming model to estimate the overhead of component minimized in OSFF.

The Time Dilation Technique for Timing Error Tolerance

Timing error tolerance is of great importance in nanometer technology integrated circuits. In this paper, the Time Dilation design technique is proposed that provides concurrent error detection and correction in the field of application and also supports off-line manufacturing scan testing. By utilizing a new scan Flip-Flop, the Time Dilation technique is capable to detect and correct multiple errors at the minimum penalty of one clock cycle delay. The silicon area overhead and the power consumption are substantially reduced, as compared to the Razor design approach, since no additional memory elements are required. At the same time, the proposed technique introduces only negligible performance degradation since no extra circuitry is inserted in the critical paths of a design.

Flip–flop selection for partial enhance scan chain using DTESFF for high transition delay fault coverage

In nanometric technologies, testing of delay faults in the integrated circuits is becoming mandatory during manufacturing test. Delay fault testing involves two test vectors. Scan based designs is used for delay fault testing with architectural limitations of traditional scan limits the two pattern delay tests that can be applied to a design which results in degraded delay test coverage. Transition delay fault (TDF) coverage improves appreciably by the use of enhanced scan design as it solves the problem by supporting arbitrary delay test vector pairs at the cost of high area overhead. It also needs fast hold signal which is analogous to scan enable signal as in case of LOS testing. Delay testable enhanced scan flip–flop (DTESFF) has been proposed as a low cost DFT technique to achieve high TDF coverage using enhanced scan design without the need of fast hold signal. In this work, a partial DTESFF scheme augments few scan flip–flops with the DTESFF design by choosing scan flip–flops carefully. It attains most of the TDF coverage advantages of a full DTESFF design with reduced area overhead. Significant improvement in TDF coverage for partial enhance scan using DTESFF has been seen on ISCAS’ 89 benchmark circuits.

Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints

This brief addresses the problem of scan-chain ordering under a limited number of through-silicon vias (TSVs), and proposes a fast two-stage algorithm to compute a final order of scan flip-flops. To enable 3-D optimization, a greedy algorithm, multiple fragment heuristic, is modified and combined with a dynamic closest-pair data structure, FastPair, to derive a good initial solution in stage one. Stage two initiates two local refinement techniques, 3-D planarization and 3-D relaxation, to reduce the wire (and/or power) cost and to relax the number of TSVs in use to meet TSV constraints, respectively. Experimental results show that the proposed algorithm results in comparable performance (in terms of wire cost only, power cost only, and both wire-and-power cost) to a genetic-algorithm method but runs two-order faster, which makes it practical for TSV-constrained scan-chain ordering for 3-D-IC designs.

Novel design of combinational and sequential logical structures in quantum dot cellular automata

Abstract Quantum dot cellular automata (QCA) is a emerging nanotechnology that promises smaller size and lower power consumption, with faster speed compared to the transistor-based technology. In this paper, we have proposed novel 8-into-3 bit simple encoder, 4-into-2 bit priority encoder, scan flip-flop, and pseudo-random bit sequence generator designs in QCA. These circuits are useful components for the design of many logical and functional circuits. Simulation results of the proposed QCA circuits are obtained by using the QCA designer tool. The correctness of the proposed circuits is hence confirmed.

Scan to Nonscan Conversion via Test Cube Analysis

Increasing complexity of integrated circuits has forced the industry to abandon partial scan, which necessitates a computationally demanding and unaffordable sequential automatic test pattern generation (ATPG), and to instead adopt full scan, despite its costs. In this paper, we propose a partial scan scheme driven by a computationally efficient test cube analysis. We tackle the challenges associated with the identification of the conditions to restore the controllability and observability compromised due to partial scan, and with the formulation of these conditions in terms of test cube operations. Upon the identification of a maximal-sized set of scan flip-flops that are converted to nonscan, a simple postprocessing of the test cubes helps compute the values to be loaded into the scan flip-flops, eliminating the need to rerun ATPG, while at the same time ensuring the quality of full scan. We further enhance this framework through techniques that process the test data before and after the application of the proposed test cube analysis-driven partial scan technique, in order to enlarge the size of the nonscan flip-flop set. The proposed scheme combines the simplicity of the conventional ATPG flow with the area, performance, test time, and test power reduction benefits of partial scan. The proposed test cube analysis-driven partial scan scheme is orthogonal and thus fully compatible with other test cost-reduction techniques, such as test data compression and test power reduction, which can be applied in conjunction.

Elimination of output gating performance overhead for critical paths in scan test

Excessive switching activity in test mode results in higher power dissipation than normal mode of operation and becoming a serious issue, in order to avoid reliability problems. Scanning of test vectors in test mode causes unnecessary switching in combinational block which can be reduced by gating methods. Gating the outputs of scan cells is a recently proposed very efficient low power test technique, which reduces the scan shift power significantly. However, the output gating techniques impacts the performance severely. In this paper, we propose a modified transistor level design of a scan flip-flop for critical paths, which eliminates the unnecessary switching in combinational circuit during shift phase of a scan-based test, without the impact on performance as in earlier scan flip-flop output gating schemes (Khatri and Ganeshan, 2008). The new scan flop design not only eliminates the performance overhead of output gating but also improves the performance of the scan flop by 32.84% (Khatri and Ganeshan, 2008) and 11.5% (Yang et al., 2008). The new flip-flop disables the output and uses an alternate path for shifting the test vectors. This approach have area overhead of six extra transistors but improves the overall performance of scan flip-flop, so this approach is better suited for critical paths. This also allows us to increase the shift frequency in designs where shift power dissipation puts upper bound on the frequency, and hence reduces test application time.

Performance evaluation of delay testable enhanced scan flip-flop

Delay faults are regularly encountered in nanometric regime that’s why it is very important to detect these faults during the manufacturing test. Testing of delay fault requires two test vectors. In general delay faults are tested using scan-based designs. The second test vector is generated in scan either by broadside test (launch of capture test) or by skewed load test (launch-on-shift). Broadside test is preferred over skewed load test approach in designs because it is implemented by system clock for scan operations while skewed load delay test requires fast scan enable signal which is not supported by most of designs but skewed load delay test provides better transition delay fault coverage with fewer test patterns compared to broadside delay test. For maximum detection of delay faults it is essential that vectors in the pair should be independent. Due to structural limitation of scan independent test vector can’t be applied to the design, which results in degradation of delay test coverage. However this can be accomplished by the use of enhance scan flip-flop which presents the application of independent delay test vector pair at the cost of high area overhead and also requires fast hold signal, similar to scan enable signal in case of skewed load testing. This paper presents a new enhanced scan flip-flop design implemented with slow hold signal and we also discussed the performance penalty caused by the delay testable enhance scan flip-flop. Experimental results shows improvement in transition delay fault coverage on ISCAS 89 benchmark circuit with this method.

Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing

Test data compression is a much more difficult problem for launch-on-capture (LOC) delay testing, because test data for LOC delay testing is much more than that of stuck-at fault testing, and LOC delay fault test generation in the two-frame circuit model can specify many more inputs. A new scan architecture is proposed to compress test stimulus data, compact test responses, and reduce test application time for LOC delay fault testing. The new scan architecture merges a number of scan flip-flops into the same group, where all scan flip-flops in the same group are assigned the same values for all test pairs. Sufficient conditions are presented for including any pair of scan flip-flops into the same group for LOC transition, non-robust path delay, and robust path delay fault testing. Test data for LOC delay testing based on the new scan architecture can be compressed significantly. Test application time can also be reduced greatly. Sufficient conditions are presented to construct a test response compactor for LOC transition, non-robust, and robust path delay fault testing. Folded scan forest and test response compactor are constructed for further test data compression. Sufficient experimental results are presented to show the effectiveness of the method.

A Yield and Reliability Improvement Methodology Based on Logic Redundant Repair with a Repairable Scan Flip-Flop Designed by Push Rule

We propose a yield improvement methodology which repairs a faulty chip due to logic defect by using a repairable scan flip-flop (R-SFF). Our methodology improves area penalty, which is a large issue for logic repair technology in actual products, by using repair grouping and a redundant cell insertion algorithm and by pushing the design rule for the repairable area of R-SFF. Additionally, compared with the conventional method, we reduce the number of wire connections around redundant cells by improving the replacement method of the faulty cell by the redundant cell. The proposed methodology reduces the total area penalty caused by the logic redundant repair to 3.6% and improves the yield, that is the number of good chips on a wafer, by 4.7% when the defect density is 1.0[1/cm^2]. Furthermore, we propose the strategy to repair the in-field failures due to latent defect for the chip whose repair function had not been used in the shipment test.

A Resilient Authentication and Trojan Detection Technique for Hard IP

A manufacture-ready design layout of a chip is vulnerable to authentication threats and infection with trojan horse in its fabrication facility or in a SoC house. The existing countermeasures are sensitive to process variation. We propose a layout watermarking scheme through reorientation of few dummy fills in the interconnect layer and resizing of few net segments. Layout watermarking is so performed that it has a controlled delay effect on the active paths leading to certain scan flip-flops chosen judicially. This delay effect can be captured as delay fault induced responses from the packaged chip while tested with a faster clock and a particular test vector pair, but the difference of post-marking delay with respect to the test clock period remains more than the effect of process variation. Results on overhead of watermarking and its robustness for ISCAS’85 benchmark circuits are encouraging.