A Resilient Authentication and Trojan Detection Technique for Hard IP

Abstract

A manufacture-ready design layout of a chip is vulnerable to authentication threats and infection with trojan horse in its fabrication facility or in a SoC house. The existing countermeasures are sensitive to process variation. We propose a layout watermarking scheme through reorientation of few dummy fills in the interconnect layer and resizing of few net segments. Layout watermarking is so performed that it has a controlled delay effect on the active paths leading to certain scan flip-flops chosen judicially. This delay effect can be captured as delay fault induced responses from the packaged chip while tested with a faster clock and a particular test vector pair, but the difference of post-marking delay with respect to the test clock period remains more than the effect of process variation. Results on overhead of watermarking and its robustness for ISCAS’85 benchmark circuits are encouraging.