Equivalent Oxide Thickness Scaling Research Articles

Effect of Al doping on structural and electrical properties of HfO2/ZrO2 layered structures for high-k applications

ZrO2 films with ultrathin Al2O3 layers have effectively contributed to the miniaturization of dynamic random access memory (DRAM) capacitors for many years. However, as memory devices continue to shrink, higher dielectric constants are required to maintain cell capacitance. To address this challenge, research has explored the use of tetragonal HfO2 layers, which theoretically possess a higher dielectric constant than ZrO2, as dielectrics. However, the thermodynamically stable phase of HfO2 is monoclinic with a lower dielectric constant, necessitating a phase transition to the tetragonal form for DRAM capacitor applications. Although attempts have been made to induce this phase transition to achieve high dielectric constants by applying an HfO2/ZrO2 layered structure or doping HfO2 with elements such as Zr, Al, and Si, significant challenges remain in completely eliminating the monoclinic phase or implementing a pure tetragonal phase of HfO2. In this study, we systematically investigated the crystallinity changes and improved the electrical properties of HfO2/ZrO2 layered structures with Al doping in the HfO2 layers. Our findings demonstrate that optimizing the partitioning of the ZrO2 and HfO2 layers, combined with Al doping, effectively achieves equivalent oxide thickness scaling.

Analysis and EOT Scaling on Top‐ and Double‐Gate 2D CVD‐Grown Monolayer MoS2 FETs

Abstract2D layered semiconductors have attracted considerable attention for beyond‐Si complementary metal‐oxide‐semiconductor (CMOS) technologies. They can be prepared into ultrathin channel materials toward ultrascaled device architectures, including double‐gate field‐effect‐transistors (DGFETs). This work presents an experimental analysis of DGFETs constructed from chemical vapor deposition (CVD)‐grown monolayer (1L) molybdenum disulfide (MoS2) with atomic layer deposition (ALD) of hafnium oxide (HfO2) high‐k gate dielectrics (top and bottom). This extends beyond previous studies of DGFETs based mostly on exfoliated (few‐nm thick) MoS2 flakes, and advances toward large‐area wafer‐scale processing. Here, significant improvements in performance are obtained with DGFETs (i.e., improvements in ON/OFF ratio, ON‐state current, sub‐threshold swing, etc.) compared to single top‐gate FETs. In addition to multi‐gate device architectures (e.g., DGFETs), the scaling of the equivalent oxide thickness (EOT) is crucial toward improved electrostatics required for next‐generation transistors. However, the impact of EOT scaling on the characteristics of CVD‐grown MoS2 DGFETs remains largely unexplored. Thus, this work studies the impact of EOT scaling on subthreshold swing (SS) and gate hysteresis using current–voltage (I–V) measurements with varying sweep rates. The experimental analysis and results elucidate the basic mechanisms responsible for improvements in CVD‐grown 1L‐MoS2 DGFETs compared to standard top‐gate FETs.

Responsivity Enhancement of Wafer‐Bonded In0.53Ga0.47As Photo‐Field‐Effect Transistor on Si Substrate via Equivalent Oxide Thickness Scaling

A high‐responsivity photo‐field‐effect transistor (photo‐FET) with a metal‐oxide‐semiconductor (MOS) structure is a promising technology for low‐intensity light detection with its high gain and low operation voltage. To enhance their responsivity, the equivalent oxide thickness (EOT) scaling is one of the effective solutions, which is a common technology to improve the electrical properties of MOSFETs using higher‐k insulators. Herein, the EOT scaling effect on the optoelectrical characteristics of photo‐FETs using Al2O3 and Al2O3/HfO2 gate stacks is investigated. Thanks to the EOT scaling effect introducing Al2O3/HfO2, only the transconductance of the photo‐FET is enhanced without any significant change in the photovoltaic effect and cavity effect. As a result, its responsivity is improved by up to 1.7 times. The results give a basic strategy of the EOT scaling effect for photo‐FETs; thus, the EOT scaling with a higher‐k insulator is a powerful solution for the high‐performance InGaAs photo‐FET requiring high responsivity in the short‐wavelength infrared range.

Subthreshold model of asymmetric GAA junctionless FETs with scaled equivalent oxide thickness

A comprehensive subthreshold model of asymmetric gate all around (GAA) junctionless (JL) FETs with scaled equivalent oxide thickness is developed in the work. The perimeter weighted sum approach is implemented to model the channel potential and threshold voltage of the device. Further, a novelty in the perimeter weighted approach is proposed to model subthreshold slope of the device. With the proposed novelty appended, the perimeter weighted approach can present a complete subthreshold solution of three dimensional multi-gate devices. Silicon dioxide, Silicon nitride, and stack of Hafnium oxide with interfacial Silicon dioxide are implied as gate dielectric to study the scaling of equivalent oxide thickness of the device in sub-1nm domain. The device characteristics for asymmetric GAA structure imparted due to the dielectric thickness asymmetry have been studied. The numerical results are compared with 3D Sentaurus TCAD device simulation outputs for variation in device parameters.

Impact of post metallization annealing (PMA) on the electrical properties of Ge nMOSFETs with ZrO2 dielectric

In this paper, impacts of post metallization annealing (PMA) temperatures on interfacial and electrical properties of Ge n-channel metal–oxidesemiconductor field-effect transistors (nMOSFETs) with ZrO2/Al2O3/GeOx/Ge gate stacks employing post-oxidation passivation are systematically evaluated. The interface trap density (Dit) and slow trap density (ΔNst) of the Ge gate stacks gradually increase with the annealing temperature increasing from 350 °C to 500 °C. Besides, the gate stacks with PMA at 400 °C exhibit higher permittivity, indicating the potential utilization in equivalent oxide thickness (EOT) scaling of gate stacks. By evaluating the electrical properties of the Ge nMOSFETs with different PMA conditions, it is found that the contact resistance and channel resistance of nMOSFETs are also strongly affected by the PMA process due to the formation of NiGe alloy and the mobility enhancement by the improved gate stack, indicating the optimization of PMA process is critical for the performance improvement of Ge nMOSFETs with ZrO2-based high-κ dielectric.

Impacts of Equivalent Oxide Thickness Scaling of TiN/Y₂O₃ Gate Stacks With Trimethylaluminum Treatment on SiGe MOS Interface Properties

Ultrathin equivalent oxide thickness (EOT) scaling of TiN/Y2O3 /SiGe gate stacks using a trimethylaluminum (TMA) treatment was studied. In comparison to previously reported high-k/SiGe MOS interfaces utilizing various Ge contents, we obtained an EOT scaling down to 1 nm with ultralow interface trap densities ( $\text{D}_{\text {it}}$ ). In addition, the impact of EOT scaling on the SiGe MOS interface properties has been investigated. We found the stress-induced degradation at the SiGe interface from constant gate biasing can be suppressed by scaling the thickness of Y2O3.

High Field Temperature-Independent Field-Effect Mobility of Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors: Understanding the Importance of Equivalent-Oxide-Thickness Downscaling

We investigate the temperature dependence of field-effect mobility (μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) on amorphous indium-gallium- zinc oxide (α-IGZO) thin-film transistors (TFTs) having 10-nm-thick HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . Thanks for the downscaling of the equivalent oxide thickness (EOT), we observe, for the first time, a temperature-independent μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> at a high field or high carrier concentration (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">carrier</sub> ) regime and a strong temperature dependent μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> at a low field or low Ncarrier regime. The observation highlights the importance of EOT downscaling to enhance N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">carrier</sub> and facilitate the Fermi level (EF) to approach and even exceed the potential barriers' peak (EM), leading to a high and temperature-independent μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> at high N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">carrier</sub> . N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">carrier</sub> at which E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> = E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> is extracted to be ~6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> . A detailed study of the relationship between EOT scaling and the gate bias voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) at which EF equals to E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> is performed. α-IGZO TFTs with an ultra scaled gate dielectric are capable of alleviating the negative effects from the potential barriers at low VGS and could enable low power applications with high performance. Besides, a weak temperature-dependent subthreshold swing (SS) of α-IGZO TFT was observed and explained.

Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0.53Ga0.47As Tri-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistors with Al2O3/HfO2 for Low-Power Logic Applications

We created tri-gate sub-100 nm In0.53Ga0.47As metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with a bi-layer Al2O3/HfO2 gate stack and investigated the scaling effects on equivalent-oxide-thickness (EOT) and fin-width (Wfin) at gate lengths of sub-100 nm. For Lg = 60 nm In0.53Ga0.47As tri-gate MOSFETs, EOT and Wfin scaling were effective for improving electrostatic immunities such as subthreshold swing and drain-induced-barrier-lowering. Reliability characterization for In0.53Ga0.47As Tri-Gate MOSFETs using constant-voltage-stress (CVS) at 300K demonstrates slightly worse VT degradation compared to planar InGaAs MOSFET with the same gate stack and EOT. This is due to the effects of both of the etched fin’s sidewall interfaces.

Scaling the Equivalent Oxide Thickness by Employing a TiO2 Thin Film on a ZrO2–Al2O3‐Based Dielectric for Further Scaling of Dynamic Random Access Memory

A metal–insulator–metal (MIM) capacitor consisting of TiN and ZrO2/Al2O3/TiO2 (ZAT) as electrodes and dielectric layer, respectively, is demonstrated for the development of next‐generation dynamic random access memory. The TiO2 layer deposited on ZrO2–Al2O3 exhibits a highly crystallized structure with an anatase phase and a dielectric constant of 40, resulting in a significant capacitance density enhancement compared with the conventional ZrO2/Al2O3/ZrO2 (ZAZ) film. The leakage current of the ZAT film can be controlled to a level comparable with that of the ZAZ film, and the carrier conduction mechanism is dominated by the thermionic emission mechanism. Consequently, a minimum equivalent oxide thickness scaling by ≈14% can be achieved by employing ZAT, compared with the conventional ZAZ.

Simulation study of gated nanowire InAs/Si Hetero p channel TFET and effects of interface trap

The impact of EOT (Equivalent Oxide Thickness) scaling, diameter scaling, and interface traps on the performance of gated InAs/Si Hetero pTFET (Tunneling field effect transistor) is investigated. EOT scaling improves SS (SubthresholdSwing) below the thermal limit and on current moderately. Diameter scaling decreases on current and marginally improves SS. The simulation study validates that the transfer characteristics of pTFET in subthreshold region are completely dominated by thermionic emission of holes and TAT (Trap Assisted Tunneling). This in turn blocks SS to attain < 60 mV/dec. Furthermore, Si/Oxide interface traps minimize the electrostatic gate coupling with channel region additionally deteriorates SS. Interface trap density with different values denotes that sub 2.3kBT/q SS can only be realized for interface trap densities Dit< 1 × 1011 cm−2eV−1 at both InAs/Si and Si/Oxide. Hence this reaffirms the experimental data, that the prerequisite of Dit< 1 × 1012 cm−2eV−1 for InAs/Si nanowire p-TFET.

Effect of increasing gate capacitance on the performance of a p-MoS2/HfS2 van der Waals heterostructure tunneling field-effect transistor

We propose a p-MoS2/HfS2 van der Waals (vdW) heterostructure tunneling field-effect transistor (TFET) with a type-II band alignment for future power-efficient electronics. The differences in temperature dependence between p-MoS2/HfS2 TFET and HfS2 metal-oxide-semiconductor field-effect transistor showed that the turn-on current of p-MoS2/HfS2 TFET originated from band-to-band tunneling. To suppress the impact of interface traps, reduce the subthreshold swing (SS), and increase the gate capacitance, the 25 nm Al2O3 gate dielectric was replaced with a 15 nm HfO2 layer. Additionally, a buried Ni back-gate structure was introduced to reduce the area of overlap between the gate, contact electrodes, and gate leakage along with the scaling of equivalent oxide thickness. Subsequently, enlargement of gate capacitance by three times led to the reduction of SS from 700 to 300 mV dec−1, which verified that increasing the gate capacitance suppressed the impact of interface traps and improved gate controllability in the vdW heterostructure TFET.

Comprehensive Study and Design of High-k/SiGe Gate Stacks with Interface-Engineering by Ozone Oxidation

The influence of the ozone oxidation conditions on the interfacial and electrical properties of high-k/SiGe gate stacks was investigated by using a step-by-step fabrication procedure. The relationship between the electrical characteristics and the corresponding interfacial chemical structures revealed that a long oxidation time was necessary to obtain a high-quality interlayer (IL), whereas adverse in terms of interface state density (Dit) and equivalent oxide thickness (EOT) scaling. This conclusion suggested us to employ a post-high-k-deposition oxidation (post-O) method to fabricate high-k/IL/SiGe gate stacks, in which the ozone oxidation was carried out after the deposition of the high-k layer. Compared with the step-by-step method, the post-O method could realize an ultrathin IL over a long oxidation time, owing to the reduced oxidation rate. Consequently, a well-balanced high-k/IL/SiGe gate stack with an ultrathin Ge-free IL of 0.26 nm, low gate leakage at VFB-1 of 6 × 10−4 A/cm2, and Dit as low as 2.2 × 1012 eV−1cm−2 was obtained.

(Invited) Interface Control of Advanced Electronic Devices - High-k/Metal Gate System and Magnetic Tunneling Junction

With the scaling of electronic devices, interface control of the constituent materials has become more and more important. Several key issues and related topics are taken up and reviewed with respect to logic and memory devices. The key issues are interface control in high-k/metal gate system for logic application and magnetic tunneling junction for memory application. High-k/Metal Gate System [1] In accordance with the requirement of CMOS scaling, replacement of thermally grown SiO2 gate dielectric with other dielectric materials with higher dielectric constant (k) has become imperative to reduce the equivalent oxide thickness (EOT) to achieve higher drivability of FET. Key factors on Hf-based high-k/metal gate (HK/MG) CMOS technology based on conventional gate first process for low operational power application are overviewed. Work-function (WF) tuning derived from ionic property of high-k material, process cost, EOT scaling with low gate leakage current are issues to be overcome. Among them, the key issue is how to control the atomic distribution in the Hf-based HK/MG system, which is absolutely requisite for WF tuning and EOT scaling. Interpretation of effective work-function (WF): For conventional gate first process, due to the interfacial reaction, the Fermi level is pinned and the WF increases with decreasing the EOT. In addition to this, due to the fixed charge in the high-k dielectric, the WF is also modulated, hence the effective WF (eWF) changes. The effect of the fixed charge is rather complicated due to an oxygen vacancy behavior in HK. Consequently, the eWF results in the “roll-off” behavior caused by the (+) charge induced by the oxygen vacancy. When the oxygen increases, i.e., (-) charge increases in the HK, the obtained WF tends to roll-up. In contrast, it tends to roll-off for more (+) charge induced by oxygen vacancy, Vo 2+in the HK. Formation process of Hf-based high-k (HK): Generally, HK is deposited by metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD), however, HK dielectric formation by oxidizing a preliminarily sputtered metallic-Hf is reasonable approach for fabricating the HK gate stack in a very pure form with less water content across the wafer. And in a very important thing, by controlling the oxidation time, this process can provide precise thickness control of the interfacial layer (IL) including “zero IL” with excellent uniformity. Magnetic Tunneling Junction A magnetic tunnel junction (MTJ) for spin-transfer-torque (STT) switching is a promising building block of non-volatile working memory embedded in very large scale integrated circuits (VLSIs) because of its potential to reduce a power consumption by replacing the conventional volatile cache memories. Among many materials, a CoFeB/MgO/CoFeB stack structure has attracted much attention as a candidate of MTJ embedded in VLSIs because of its high tunnel magnetoresistance (TMR) ratio caused by a perpendicular magnetic easy axis. And what is better, this MTJ has a potential for high integration into VLSIs down to a junction size of 1X nm regime. To improve the MTJ performance, crystal structure of the CoFeB/MgO interface is a crucial issue as well as B behavior during the process treatment. Redox reaction: As an example of the interfacial reaction, a redox reaction was observed at the surface of Ta/CoFeB/MgO/CoFeB MTJ stack after annealing up to 400℃ for 1 h in vacuum, by angle-resolved X-ray photoelectron spectroscopy (XPS). For 1nm-thick tantalum capping layer of the as-deposited stack sample, both the tantalum layer and the surface of the CoFeB layer underneath the tantalum layer were naturally oxidized. By comparison of the Co 2p and Fe 2p spectra with respect to as-deposited and annealed samples, reduction of the naturally oxidized cobalt and iron atoms was found to occur at the surface of the CoFeB layer. This reduction reaction was more significant at higher annealing temperature. Oxidized cobalt and iron were found to be reduced by boron atoms that diffused toward the surface of the top CoFeB layer. By means of naturally oxidized surface of the CoFeB layer formed on SiO2, the redox reaction behavior after annealing was confirmed by angle-resolved XPS analysis[2]. This redox reaction is thermodynamically reasonable according to the Ellingham diagram. (This work is supported by Industrial Affiliation on the STT-MRAM program in CIES Consortium and ACCEL project under JST.) [1] M. Niwa (2013), Chapter 4, High Permittivity Gate Dielectric Materials, Edited by S. Karr, Springer Series in Advanced Microelectronics 43 , pp. 191-234. [2] S. Sato et al., Appl. Phys. Lett. 196, 142407 (2015).

(Invited) High-K Evolution: Subnanometer EOT Challenges and Future Perspectives for Scaling

The use of high-k (HiK) dielectrics has enabled further downsizing of CMOS devices, towards the nanoscale range. However, the gate oxide scaling, in the sense of equivalent oxide thickness (EOT), has already lost its momentum. In the subnanometer EOT, or for a couple nanometer physical thickness, most HiK materials fail to maintain their superior electrical properties. In addition, the related interface layers (HiK/silicon substrate and HiK/metal gate) are not directly scalable. They limit the smallest achievable EOT and govern some of the device properties such as channel mobility, subthreshold conduction, etc. This work highlights the major challenges coming across with the EOT scaling in the subnanometer range. Some future perspectives such as the use of alternative gate electrode materials and crystalline HiK for interface control will also be discussed.

High Mobility High-Ge-Content SiGe PMOSFETs Using Al2O3/HfO2 Stacks With &lt;italic&gt;In-Situ&lt;/italic&gt; O3 Treatment

We developed an Al2O3/HfO2 bi-layer gate dielectric with an in-situ O3 treatment for interface state density (Dit) and gate leakage current density (Jg) reductions on SiGe channels. We observed Ge-content dependent equivalent oxide thickness (EOT) scaling and EOT 0.44 nm was achieved with an MOS capacitor with a Si0.05Ge0.95 substrate. The O3 treatment enabled application to non-planar device structures and we demonstrated five orders of magnitude lower off currents (IOFF), a sub-threshold slope of 68 mV/decade, and a very high hole mobility of 457 cm $^{2}\text{V}^{\mathrm {-1}}\text{s}^{\mathrm {-1}}$ at an inversion carrier density (Ninv) of $1\times 10^{13}$ cm $^{\mathrm {-2}}$ for asymmetrically strained SiGe PMOSFETs with Ge% of 65%–70%.

Investigation on Passivation Mechanism of Ge Surface By GeOx

The passivation machenism of Ge surface by germanium suboxide GeO­x is investigated. The interface state density (Dit) measured from low temperature conduction method is found to decrease with increasing the GeOx thickness (0.26-1.06 nm). The X-ray photoelectron spectroscopy (XPS) is employed to demonstrate the interfacial structure of GeOx/Ge with different GeOx thicknesses. And the XPS results show that Ge3+ oxide component is responsible to the decrease of the Dit due to the effective passivation of Ge dangling bonds. Therefore, the formation of Ge3+ component is the dominant key to achieve low Dit for Ge gate stacks. Our work confirms that the same physical mechanism determines the Ge surface passivation by the GeOx regardless of the oxidation methods to grow the GeOx interfacial layer. As a result, to explore a growth process that can realize sufficient Ge3+ component in the GeOx interlayer as thin as possible is important to achieve both equivalent oxide thickness scaling and superior interfacial property simultaneously. This conclusion is helpful to engineer the optimization of the Ge gate stacks. Figure 1

Prospects of High-Ge-Content Strained SiGe for Advanced FinFET Generations

High Ge content SiGe FETs have recently drawn significant attention as a candidate for p-MOSFETs due to their enhanced transport and reliability properties and compatibility with bulk or SOI substrates. In addition, compared to strained pure germanium, they can offer reduced off-state tunneling leakage due to their relatively larger bandgap. Utilization of high Ge content SiGe in a FinFET architecture by direct epitaxial growth is quite challenging due to epitaxial critical thickness constraints, resulting in high levels of defectivity which may be detrimental to the device functionality and performance. In this paper, we review our recent progress on high Ge content SiGe FinFETs with Ge content over 60%. In particular, gate stack, passivation and equivalent oxide thickness scaling are major factors in achieving high quality devices based on high Ge content SiGe. We present our results based on a Si-cap-free FinFET surface passivation to achieve excellent sub-threshold swings for both gate first and replacement high-K and metal gate integration flows. In addition, various device aspects such as transport and mobility, S/D and junction, off-state drain leakage current and short channel performance are discussed.

(Invited) TmSiO As a CMOS-Compatible High-k Dielectric

High-k/metal gate stacks have been a core enabler of CMOS technology for almost a decade, allowing sub-nm equivalent oxide thickness (EOT) while keeping the gate leakage current density at acceptable levels [1]. State-of-the-art high-k/metal gate stacks employ a Hf-based high-k dielectric (typically HfO2) deposited on top of a thin interfacial layer (IL), which usually consists of chemical oxide (SiOx) and whose presence is crucial in order to guarantee the overall electrical quality of the gate stack [2]. It has indeed been shown that a thinner IL, while desirable from the point of view of EOT scaling, leads to problematic degradations in channel mobility [3], threshold voltage control [4], and device reliability [5]. Further scaling of high-k/metal gate stacks has been a central subject in recent research, and is usually addressed by replacing HfO2 with a higher-k material and/or by replacing SiOx with a high-k IL. The latter strategy is especially interesting, since the IL contributes ~1/2 of the total EOT of a scaled gate stack and since there are viable options to replace SiOx with a dielectric exhibiting significantly higher dielectric constant (~3x), whereas the same is not true for higher-k dielectrics. Lanthanide silicates have especially been shown to provide controllable thickness of the IL in the sub-nm regime and device-grade interface state density, rendering them extremely interesting as a potential replacement for SiOx IL [6]. Careful consideration of the material properties from the point of view of achieving controllable and reproducible formation of a sub-nm interfacial layer has led to the identification of thulium silicate (TmSiO) as a promising candidate IL for sub-10nm CMOS nodes. A straightforward process flow, compatible with industry-standard gate-first and gate-last integration schemes, has been demonstrated for integration of TmSiO in a high-k/metal gate stack, achieving EOT of the IL of 0.25±0.15 nm and interface state density ~1·1011 cm-2eV-1 [7]. Integration of TmSiO in Hf-based gate stacks has also been shown to be compatible with threshold voltage control techniques commonly used in gate-first and gate-last integration schemes [8], and gate-last MOSFETs achieving sub-nm EOT, 10 year device reliability and higher mobility than state-of-the-art SiOx/HfO2 devices have been demonstrated [9-10]. Replacing the SiOx IL with TmSiO can be especially advantageous in terms of channel mobility and device reliability, since both device properties have been shown to degrade strongly with decreasing IL thickness. Reliability in TmSiO/HfO2 MOSFETs has been investigated from the point of view of time-dependent dielectric breakdown (TDDB) and bias temperature instability (BTI), achieving expected lifetimes of 10 years for both nFETs and pFETs at EOT~0.8 nm and gate voltage ~1V (compatible with supply voltage in sub-10nm CMOS nodes). The effect of TmSiO on channel mobility has been analyzed by measuring electron mobility at high temperature and after constant voltage stress and comparing the observed trends with published data on SiOx/HfO2 devices, with the conclusion that replacing the SiOx IL with TmSiO can improve mobility by 20% at high effective field due to reduced remote phonon scattering. In this talk, the main advantages and challenges in the adoption of TmSiO as interfacial layer in scaled CMOS technology nodes will be addressed. [1] K. Mistry et al., IEDM Tech. Dig., pp. 247–250, 2007. [2] T. Ando, Materials, vol. 5, no. 3, pp. 478–500, 2012. [3] L.-Å. Ragnarsson et al., Int. Symp. VLSI Technol. Syst. Appl., 2011. [4] T. Ando et al., IEEE Electron Device Lett., vol. 34, no. 6, pp. 729–731, 2013. [5] E. Cartier et al., IEDM Tech. Dig., pp. 441–444, 2011. [6] T. Kawanago et al., IEEE Trans. Electron Devices, vol. 59, no. 2, pp. 269–276, 2012. [7] E. Dentoni Litta et al., IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3271–3276, 2013. [8] E. Dentoni Litta et al., Solid-State Electron., vol. 108, pp. 24-29, 2015. [9] E. Dentoni Litta et al., IEEE Trans. Electron Devices, vol. 62, no. 3, pp. 934–939, 2015. [10] E. Dentoni Litta et al., IEEE J. Electron Devices Soc., vol. 3, no. 5, pp. 397–404, 2015.

Investigation on the dominant key to achieve superior Ge surface passivation by GeOx based on the ozone oxidation

The dominant key to achieve superior Ge surface passivation by GeOx interfacial layer is investigated based on ozone oxidation. The interface state density (Dit) measured from low temperature conduction method is found to decrease with increasing the GeOx thickness (0.26–1.06nm). The X-ray photoelectron spectroscopy (XPS) is employed to demonstrate the interfacial structure of GeOx/Ge with different GeOx thicknesses. And the XPS results show that Ge3+ oxide component is responsible to the decrease of the Dit due to the effective passivation of Ge dangling bonds. Therefore, the formation of Ge3+ component is the dominant key to achieve low Dit for Ge gate stacks. Our work confirms that the same physical mechanism determines the Ge surface passivation by the GeOx regardless of the oxidation methods to grow the GeOx interfacial layer. As a result, to explore a growth process that can realize sufficient Ge3+ component in the GeOx interlayer as thin as possible is important to achieve both equivalent oxide thickness scaling and superior interfacial property simultaneously. This conclusion is helpful to engineer the optimization of the Ge gate stacks.

Silicon surface passivation using thin HfO2 films by atomic layer deposition

Hafnium oxide (HfO2) is a potential material for equivalent oxide thickness (EOT) scaling in microelectronics; however, its surface passivation properties particularly on silicon are not well explored. This paper reports investigation on passivation properties of thermally deposited thin HfO2 films by atomic layer deposition system (ALD) on silicon surface. As-deposited pristine film (∼8nm) shows better passivation with <100cm/s surface recombination velocity (SRV) vis-à-vis thicker films. Further improvement in passivation quality is achieved with annealing at 400°C for 10min where the SRV reduces to ∼20cm/s. Conductance measurements show that the interface defect density (Dit) increases with film thickness whereas its value decreases after annealing. XRR data corroborate with the observations made by FTIR and SRV data.