CMOS Technology Scaling Research Articles

Benchmarking Silicon FinFET With the Carbon Nanotube and 2D-FETs for Advanced Node CMOS Logic Application

In this article, the performance of silicon FinFET is compared with carbon nanotube (CNT-FET) and 2-D field-effect transistors (2D-FETs) for the upcoming node CMOS logic application. Based on the experimental results, a 17-stage ring oscillator (RO) circuit is implemented using the compact models to analyze the stage-delay and energy-delay performances. A tightly positioned 20- and 10-nm channel-length-based CNT-FET enhances I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> and also increases the leakage currents significantly. Due to poor electrostatic control and increased gate leakage, the CNT-FET and 2D-FET provide lowered I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> and a limited ac performance. Thus, targeting an off-state current, the FinFET delivers more than three times higher drive current, as well as five times better energy-delay performances in comparison to the CNT-FET and 2D-FET. On the other hand, scaled organic FETs are yet far away to compare with FinFET technology. Hence, the silicon-based (3-D) FETs are leading in all the devices (2-D, 1-D, and 0-D) for scaling next-generation CMOS technology.

SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks

With the continuous scaling of CMOS technology, which has now reached the 3 nm node at production level, static power begins to dominate the power consumption of nanometer CMOS integrated circuits. A novel class of security attacks to cryptographic circuits which exploit the correlation between the static power and the secret keys was introduced more than ten years ago, and, since then, several successful key recovery experiments have been reported. These results clearly demonstrate that attacks exploiting static power (AESP) represent a serious threat for cryptographic systems implemented in nanometer CMOS technologies. In this work, we analyze the effectiveness of the Standard Cell Delay-based Precharge Logic (SC-DDPL) style in counteracting static power side-channel attacks. Experimental results on an FPGA implementation of a compact PRESENT crypto-core show that the SC-DDPL implementation allows a great improvement of all the security metrics with respect to the standard CMOS implementation and other state-of-the-art countermeasures such as WDDL and MDPL.

Unified RTN and BTI statistical compact modeling from a defect-centric perspective

In nowadays deeply scaled CMOS technologies, time-dependent variability effects have become important concerns for analog and digital circuit design. Transistor parameter shifts caused by Bias Temperature Instability and Random Telegraph Noise phenomena can lead to deviations of the circuit performance or even to its fatal failure. In this scenario extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at near threshold, nominal and accelerated aging conditions. Statistical modelling of RTN and BTI combined effects covering the full voltage range is presented. The results of this work suppose a complete modelling approach of BTI and RTN that can be applied in a wide range of voltages for reliability predictions.

(Invited) Random Network Structure of Materials Developing Next Generation AI Devices for Autonomous Robotics

1. IntroductionIn recent years, the superior computational power of deep learning based on software has been widely recognized, and the practical applications of artificial intelligence are rapidly expanding. On the other hand, the hardware for replacing to such artificial intelligence (AI) algorithms is facing the physical limits of scaling in silicon CMOS technology, and performance improvement is expected to hit the ceiling. For this reason, there is a growing interest in hardware technologies that physically implement artificial neural networks (ANNs), neuromorphic or brainmorphic information processing systems, and the applications (hereafter referred as AI systems in this paper), as well as new materials and devices. A critical difference between the presently required device functionality and that in conventional computational systems is the use of dynamics. By cleverly using nanomaterials' nonlinearity and network structure, devices that spontaneously generate pulses, noise, and other physical phenomena are expected to be realized to utilize for the AI hardware. These devices will enable drastically lower power consumption and higher integration of AI systems. In the learning process of ANNs, it is necessary to constantly change and store the weights of the weighted sum (sum-of-products) part. In our research center, we have been working on materials that can complement CMOS for AI systems by using molecules and nanocarbon materials, and further, we are trying to apply them to autonomous AI robots. This paper introduces these nanomaterials and networks’ formation as devices, the key points of the devices’ functionalization, application to robots, and other recent research results.2. Formation and Control of NanomaterialsOrganic and inorganic nanosized molecules can be synthesized to form structures by the current development of synthesis technology; a great variety of molecules can be realized and controlled for a high potential to use as neuromorphic devices. In order to elicit electronic functionalities, it is necessary to transfer electrons to and from the molecules, which is a redox reaction from a chemical point of view. Stable Carbon-based materials that have a close Fermi level to the molecules may be more suitable than metallic electrodes. We have connected nanoparticles of organic molecules to single-walled carbon nanotubes (SWNTs) to control the electrical properties of the nanoscale [1].3. Results obtained from Random NetworksWe formed a random network consisting of SWNTs and POMs and found that it generates neuron-like pulses when a high voltage is applied (Fig. 1, left) [2]. This enabled us to control noise and pulses generation. Such dynamic signal generation is attributed to the multiple discharges of POM molecules. Reservoir computing simulations also showed that this system could be used for time series memory [2].In this study, we applied a sinusoidal signal to an SWNT/Por-POM random network using porphyrin-gradient sandwich POM (Por-POM), which is more redox-sensitive, and the Lissajous plot of the output signal from one of the multiple electrodes plotted against the input signal showed nonlinear switching behavior. A memory state was generated due to the reversible redox of Por-POM, and the input signal was highly interacted with the reservoir system. The interaction can be also checked by the changing of the Lissajous plot shape from linear to elliptical, which indicate the characteristics obtained from current and past inputs through the echo state network. The dynamics are also confirmed by the higher harmonic generation (HHG) from the FFT analysis, and NARMA-2 task which considers states up to a two-step delay. The NARMA-2 task successfully generated signals that predictably follow the target waveform using a linear regression model. These results indicate that the nonlinearity of SWNT/Por-POM and memory integrity are important factors for reservoir operation. We also used Ag/Ag2S core-shell nanoparticles (NP) as a reservoir device (Fig.1, right) to obtain similar results with SWNT/Por-POM.As mentioned above, large power consumption during the sum-of-products operation in the weighted addition part has been a problem in AI systems. While, by using reservoir computing devices consist of random networks of SWNT/POM, core-shell nanoparticles, nanowires, etc., it is expected that the sum-of-products operation can reduce power consumption. Voice recognition and robot-hand grabbing stuff recognition [3] was conducted by the reservoir devices. Details will be presented at the presentation.Refs. [1] H. Tanaka et al., Adv. Mat. 18, 1411 (2006). [2] H. Tanaka et al., Nat. Commun. 9, 2693 (2018). The article was selected as the most read 50 articles published in Nat. Commun. in 2018 (Physics). [3] Kyutech won the RoboCup world series of Domestic Standard Platform League by TOYOTA HSR in 2017 and 2018. The same robot is used for the demonstration. Figure 1

(Invited) Characterization of Doping and Activation Processes Using Differential Hall Effect Metrology (DHEM)

As advanced CMOS technology scaling goes beyond 7nm node, contact resistivity becomes an important factor influencing device performance. Approaches to reduce contact resistivity involve advanced doping techniques that yield very high degree of dopant activation at the semiconductor layers comprising the source and drain regions. These approaches include in-situ heavily doped epi layers and ion implantation followed by advanced annealing techniques. Irrespective of the approach used in wafer processing, accurate analysis of dopant activation within the top few nanometers of the surface is critical to understanding the effectiveness of such processes on improving contact resistivity. Similarly, correlation of mobility depth profile to defectivity in the layers helps one to understand how process variables may affect the ultimate electrical properties.Differential Hall Effect Metrology (DHEM) is the only method that can provide mobility and active dopant depth profiles through semiconductor layers at sub-nm resolution. The method employs electrochemical means of reducing the electrically active thickness of a semiconductor film and determining the sheet resistance and mobility of the thinned down layer using Van der Pauw/Hall effect type measurements [1].In this work we characterized an ion implantation/annealing process cycle using DHEM and TEM studies. The sample was a p-type Si wafer ion implanted with P (10keV, 2E15cm-2). After implantation, the wafer was coated with positive photoresist, exposed, and developed in order to define a cross-shaped Van der Pauw structure. After formation of the DHEM test patterns using dry etching, wafer pieces were processed by rapid thermal anneal (RTA) at 750 ºC, 850 ºC, and 950ºC in nitrogen ambient for 30 seconds. After annealing, samples were subjected to a negative photoresist process in order to open contact windows. After the exposure and development, native oxide was removed from the contact windows and metallic contacts were evaporated. Depth profiles of resistivity, mobility, and carrier concentration were measured by DHEM using an ALPro™ 50 electrical profiling tool.Fig. 1 shows the cross-sectional TEM images of the P ion implanted samples after annealing at (a) 750ºC, (b) 850ºC, and (c) 950ºC. As can be seen in Fig 1(a) the end of range (EOR) defects are located at approximately 26-30 nm from the surface in this sample. The 750ºC RTA process did not adequately resolve these defects. However, it is clear from the TEMs that defects at the original location of the a-Si/c-Si interface decreased gradually when the samples were annealed at increasing RTA temperatures (see Fig. 1(b−c)), when crystallinity of the ion implanted top layer also improved.The depth profiles of active carrier concentration after RTA process are given in Fig.2(a). Three regions can be discussed in these depth profiles. Region 1 is within 15nm of the surface, region 2 is at around 20-30 nm depth, and region 3 is at depths at or larger than 40nm. As can be seen in this figure, higher and higher RTA temperatures result in diffusion of P impurities deeper, and dopant activation at region 3 gets higher and higher as the anneal temperature is increased from 750ºC to 950ºC. As for the region 1, we observe a small decrease in carrier concentration values with higher temperature (from about 3.77E+20 #/cm3 to about 2.95E+20 #/cm3) as the overall active dopant profile becomes more uniform due to diffusion.Figure 2(b) shows the mobility depth profiles of the three samples discussed with reference to Fig. 1 and Fig. 2(a). It is obvious from this figure that the mobility profile is relatively flat within the implantation region (<30nm). Notably the mobility value for the RTA 750ºC sample dips at a depth in the range of 25-30 nm, where Fig. 1(a) shows extensive EOR defectivity. Therefore, the correlation with deteriorated mobility at that region is excellent. It is also clear from the mobility data that as the annealing temperature is raised to 850ºC and then to 950ºC this dip in mobility disappears, suggesting reduction in defects through higher temperature annealing. Deeper region (>40nm) mobility reduces with increasing temperatures because of increased carrier scattering mechanisms as more of the dopant is activated deeper at the elevated temperatures.Through this work we have demonstrated how DHEM technique can be utilized to correlate electrical and physical data obtained from samples subjected to doping processes. At the present time we are extending this work to ultra shallow junction structures and these results will be presented at the conference.

Statistical threshold voltage shifts caused by BTI and HCI at nominal and accelerated conditions

In nowadays deeply scaled CMOS technologies, time-zero and time-dependent variability effects have become important concerns for analog and digital circuit design. For instance, transistor parameter shifts caused by Bias Temperature Instability and Hot-Carrier Injection phenomena can lead to progressive deviations of the circuit performance or even to its catastrophic failure. In this scenario, and to understand the effects of these variability sources, an extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models and simulation tools needed to achieve reliable integrated circuits. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at nominal and accelerated aging conditions. To this end, a versatile transistor array chip and a flexible measurement setup have been used to reduce the required testing time to attainable values.

Design of Multiple Node Upset Tolerant Latch in 32 nm CMOS Technology

<p indent=0mm>With continuous scaling of CMOS technology, single event multi-node upset induced by charge sharing effect has become an important factor affecting chip reliability. This paper proposed a novel multi-node upset (MNU) tolerant latch design: LPMNUHL. Based on DICE latch, where single node upset is resilient, the latch builds a mechanism of triple modular redundancy and uses a voter as output. The proposed latch is tolerant to multi-node upset and votes the correct output logic value. What’s more, there is no high impedance state in the latch and soft errors of the internal nodes can be blocked successfully. The latch can not only tolerance triple node upset completely, but also tolerance 90.30% of quadruple node upset. Due to the use of a high-speed transmission path, the clock-gating technology and a clock-gating voter, the proposed latch is low power. In <sc>32 nm</sc> CMOS technology, extensive SPICE simulation results demonstrate that compared with the previous latches, the proposed latch has an average delay reduction of 40.16%, an average power reduction of 44.96%, an average power delay product reduction of 65.40%, and an area reduction of 34.60%. Moreover, the proposed latch is not sensitive to temperature and voltage variations.

Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater

Transistor threshold voltage (Vt) scaling causes higher power consumption by increasing the subthreshold leakage and short-circuit currents in CMOS circuits. Leakage currents are significant contributors to the overall power consumption of digital systems-on-chip as threshold voltage, channel length, and gate oxide thickness are reduced with CMOS technology scaling. A new dual-pullup/dual-pulldown (DPU/DPD) repeater is proposed in this paper for higher energy efficiency in low-voltage and low-frequency applications. The standby mode leakage power consumption is reduced by 59.11% with the proposed clock tree as compared to the conventional 3 level H-tree operating with a power supply voltage of 1.0V in a 45 nm CMOS technology. The short-circuit currents are suppressed by selectively employing high-Vt transistors in the repeaters. The clock network with the proposed buffer lowers the active mode energy consumption by up to 24.91% as compared to a conventional clock tree under equal silicon area constraint. Post layout results reveal that the statistical spread of clock skew in the DPU/DPD H-tree is also 20.60% lower than the conventional H-tree network.

Optimal soft error mitigation in wireless communication using approximate logic circuits

The development of in chip manufacturing processes has enhanced energy-efficient nano-electronic and high-performance devices in daily activities. In recent times, CMOS technology scaling has recognized several transistors in large-scale VLSI chips to support performance. However, these innovations have also frequently increased the impact of Soft-Error (SE) reliability concerns in computing architectures for Wireless Communications systems. Thus, this paper proposes an energy-efficient probability-based approximation method to significantly enhance SE mitigation using approximate logic circuits. Firstly, the dynamic-based probability performance indicates that the mandatory assignment (MA) function achieves an accurate detection result of P(E)−0.130 better than the other functions. Then, to realize a quality SE detection and overcome SEs with multiple identities which leads to wrong SE detection at the vulnerable zones, the investigation sets a detection limit at 95% and 98%, respectively. However, it is observed that the higher the detection limit, the better measurement of precision for SE that occurred. Hence, the measurement of precision with 98% of detection limit outperforms significantly as compared with other detection limits. Further, an efficient algorithm is designed to maximize system performance. The results confirm the robustness of the proposed method and a more reliable performance as compared to other existing techniques.

A low‐power 10‐bit CCP‐based pipelined ADC using a multi‐level variable current source MDAC and an ultra‐low‐power double‐tail dynamic latch

SummaryIn this paper, a low‐power 10‐bit 15‐MS/s opamp‐less pipelined analog‐to‐digital converter (ADC) has been proposed. The circuit is comprised of eight 1.5‐bit/stage MDACs and a 2‐bit backend flash ADC. Each 1.5‐bit/stage structure comprises a CCP‐based MDAC which uses a modified multilevel variable‐current‐source (ML‐VCS) scheme. The modified ML‐VCS CCP structure facilitates its usage in a pipeline ADC structure. Also, the proposed ML‐VCS structure improves the speed behavior as well as the power consumption of a 1.5‐bit/stage CCP‐based MDAC structure. In order to further reduce power consumption, an ultra‐low‐power low‐delay double‐tail dynamic latch has been offered which features high‐speed operation. The suggested ADC is simulated using 180‐nm scaled CMOS technology with a 2‐Vp‐p differential full‐scale input voltage. Hspice simulation results show that the ADC exhibits an SNDR of 60‐dB, an ENOB of 9.67 bits, and the FOM of 0.546 PJ/Conv.step at a Nyquist‐rate input frequency. According to the results, the proposed 10‐bit ADC consumes only 6.7‐mW under a 1.8‐V supply voltage.

Understanding ambipolar transport in MoS2 field effect transistors: the substrate is the key

2D materials offer a pathway for further scaling of CMOS technology. However, for this to become a reality, both n-MOS and p-MOS should be realized, ideally with the same (standard) material. In the specific case of MoS2 field effect transistors (FETs), ambipolar transport is seldom reported, primarily due to the phenomenon of Fermi level pinning (FLP). In this study we identify the possible sources of FLP in MoS2 FETs and resolve them individually. A novel contact transfer technique is used to transfer contacts on top of MoS2 flake devices that results in a significant increase in the hole branch of the transfer characteristics as compared to conventionally fabricated contacts. We hypothesize that the pinning not only comes from the contact-MoS2 interface, but also from the MoS2-substrate interface. We confirm this by shifting to an hBN substrate which leads to a 10 fold increase in the hole current compared to the SiO2 substrate. Furthermore, we analyse MoS2 FETs of different channel thickness on three different substrates, SiO2, hBN and Al2O3, by correlating the p-branch I ON/I OFF to the position of oxide defect band in these substrates. FLP from the oxide is reduced in the case of Al2O3 which enables us to observe ambipolar transport in a bilayer MoS2 FET. These results highlight that MoS2 is indeed an ambipolar material, and the absence of ambipolar transport in MoS2 FETs is strongly correlated to its dielectric environment and processing conditions.

Trade‐Off Between Data Retention and Switching Speed in Resistive Switching ReRAM Devices

AbstractMemristive switching devices are promising for future data storage and neuromorphic computing applications to overcome the scaling and power dissipation limits of classical CMOS technology. Many groups have engineered bilayer oxide structures to enhance the switching performance especially in terms of retention and device reliability. Here, introducing retention enhancement oxide layers into the memristive stack is shown to result in a reduction of the switching speed not only by changing the voltage and temperature distribution in the cell, but also by influencing the rate‐limiting‐step of the switching kinetics. In particular, it is demonstrated that by introducing a retention enhancement layer into resistive switching SrTiO3 devices, the kinetics are no longer determined by the interface exchange reaction between switching oxide and active electrode, but depend on the oxygen ion migration in the additional interface layer. Thus, the oxygen migration barrier in the additional layer determines the switching speed. This trade‐off between retention and switching speed is of general importance for rational engineering of memristive devices.

Improved Air Spacer for Highly Scaled CMOS Technology

We report an improved air spacer (AS) integration scheme to overcome problems with the conventional AS process. The new scheme is fully compatible with other emerging CMOS technology elements such as self-aligned contact (SAC) and contact over active gate (COAG). Using a fan-out3 (FO3) ring oscillator (RO) on a 10-nm FinFET platform, we experimentally demonstrate that the new AS provides 15% reduction in the effective capacitance ( ${C}_{{\text {eff}}}{)}$ . Such a ${C}_{{\text {eff}}}$ reduction translates to 21% performance gain at the constant power (iso-power) or 36% power reduction at the constant performance (iso-speed). The benefits provided by AS exceed the benefits of a full CMOS node scaling from 7 to 5 nm. Clearly, AS is a viable technological element for continuing CMOS scaling.

(Invited) On the Potential of Lateral BJTs and SiGe HBTs in Advanced CMOS Technologies

The potential of lateral bipolar transistors, based on Horizontal Current Bipolar Transistor (HCBT), in scaled CMOS technologies are examined by TCAD simulations. Thorough and consistent simulations show that SiGe HCBT can achieve fT /fmax of 358/490 GHz outperforming standard vertical-current HBT with fT /fmax of 348/423 GHz, assuming the same intrinsic transistor doping profile. By optimizing the extrinsic base shape and width, the characteristics of SiGe HCBT can be further improved. SiGe HCBTs in bulk silicon substrates result in better performance comparing to the transistors in SOI substrates.

Wireline communication: the backbone of data transfer

This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed.

Performance Analysis of CMOS Technology

The project titled “Performance Evaluation of CMOS Technology” is a research conducted to provide students with guidelines about what to invest their time in the field of VLSI & ULSI technology and enlighten them about various parameters of Scaling of CMOS technology which is the most used IC technology in the world. This report also studies the range of scaling of MOSFET and its limits. The performance of a device relies highly on the performance of the IC and Transistors used in its circuit hardware. CMOS which is the abbreviation of Complementary Metal Oxide Semiconductor is a technology used to design Integrated Circuits. The Complementary prefix to MOS that refers to MOSFET signifies the use of complementary semiconductors that is NMOS and PMOS. These two MOS technologies work together to form a wide array of gates and Integrated Circuits. This research provides students various results on the unreliability of Student Version Simulation software in designing new generation hardware and how power dynamics of highly scaled technology cannot be verified using such tools.

(Invited) Dielectric Science on Today's Devices

Device scaling in CMOS technology has approached to 10nm range and below. The gate dielectric, being the critical constraint, has evolved significantly and requires constant quality improvements in order to keep the proper functioning of the transistors and memory devices. While the transistor has transformed from a planar device to a three-dimensional device to a gate all around device, several new devices such as ferroelectric FETs and negative capacitance FETs have emerged to be integrated into standard CMOS technology. Additionally, many forms of memory devices such as resistive random-access memory (ReRAM) devices and ferroelectric RAM devices are being investigated for possible implementation of artificial intelligence hardware. All these devices use high dielectric constant (high-k) materials in some form or other. The electrical performance in these devices depends on the dielectric deposition process, precise selection of deposition parameters, pre-deposition surface treatments and subsequent thermal budget. In this work we describe the evolution of dielectric science in nanoelectronics.For logic devices, once the thickness of SiO2 reached the onset of direct tunneling region (<1.5 nm) high-k insulators were introduced to suppress the direct-tunneling leakage current. Because of thermal stability, HfO2-based high-k dielectrics were selected to replace SiO2. To resolve issues like mobility degradation, threshold voltage control and Fermi-level pinning, HfO2-based high-k gate dielectrics was introduced with an interfacial SiO2 layer on silicon devices. Subsequently, higher-k dielectrics are required for transistors performance enhancement to keep up with the scaling without reducing the physical dielectric thickness. It was achieved by controlling the structural phase of HfO2 by doping HfO2 with various metal oxides including ZrO2 as cubic, or tetragonal phase that provides higher-k than amorphous or monoclinic phase. By considering the interface reaction kinetics and thermal budget various atomic layer deposition (ALD) schemes were identified to get a stable dielectric with a robust interface. We will discuss the deposition of Hf1-xZrxO2 or HfAlOx on both silicon and germanium, a higher mobility channel material. The reliability characterization of these dialectics based on dielectric-semiconductor interface will also be discussed.In ReRAM devices, the resistance change, achieved in a dielectric material between two metal terminals by applying a voltage, is promising for further scaling of memory devices. The switching mechanism in transition metal oxides like HfO2 is, while evolving, based on similar mechanism to soft breakdown, where a conducting filament path is formed due to oxygen vacancy transition/formation. The process is reversed by rupturing the filament. Various dielectric stacks are currently being studied for ReRAM applications. Additionally, ferroelectric characteristics of HfZrO films also derived significant attention recently. Some of the current trends in memory devices involving high-k dielectrics will be discussed.

Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor With Monolithically Integrated ReRAM

The slowdown of the CMOS technology scaling, and the trade-off between efficiency and flexibility have fueled the exploration into novel architectures with emerging post-CMOS technology [e.g., resistive-RAM (RRAM)]. In this article, a nonvolatile fully programmable processing-in-memory (PIM) processor named Liquid Silicon is demonstrated, which combines the superior programmability of general-purpose computing devices [e.g., field-programmable gate array (FPGA)] and the high efficiency of domain-specific accelerators. Besides the general computing applications, Liquid Silicon is particularly well suited for artificial intelligence (AI)/machine learning and big data applications, which not only poses high computational/memory demand but also evolves rapidly. To fabricate the Liquid Silicon chip, the HfO2 RRAM is monolithically integrated on top of the commercial 130 nm CMOS. Our measurement confirms that Liquid Silicon chip can operate reliably at a low voltage of 650 mV. It achieves 60.9 TOPS/W in performing neural network (NN) inferences, and 480 GOPS/W in performing content-based similarity search (a key big data application) at a nominal voltage supply of 1.2 V, showing $3\times $ and $100\times $ improvement over the state-of-the-art domain-specific CMOS-/RRAM-based accelerators. In addition, it outperforms the latest nonvolatile FPGA in energy efficiency by $3\times $ in general computing applications.

Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects

CMOS technology scaling has reached its limit at the 22 nm technology node due to several factors including Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE). In order to continue the miniaturization process via technology down-scaling while preserving system reliability and performance, Fin Field-Effect Transistors (FinFETs) arise as an alternative to CMOS transistors. In parallel, Static Random-Access Memories (SRAMs) increasingly occupy great part of Systems-on-Chips’ (SoCs) silicon area, making their reliability an important issue. SRAMs are designed to reach densities at the limit of the manufacturing process, making this component susceptible to manufacturing defects, including the resistive ones. Such defects may cause dynamic faults during the circuits’ lifetime, an important cause of test escape. Thus, the identification of the proper faulty behavior taking different operating conditions into account is considered crucial to guarantee the development of more suitable test methodologies. In this context, a comparison between the behavior of a 22 nm CMOS-based and a 20 nm FinFET-based SRAM in the presence of resistive defects is carried out considering different power supply voltages. In more detail, the behavior of defective cells operating under different power supply voltages has been investigated performing SPICE simulations. Results show that the power supply voltage plays an important role in the faulty behavior of both CMOS- and FinFET-based SRAM cells in the presence of resistive defects but demonstrate to be more expressive when considering the FinFET-based memories. Studying different operating temperatures, the results show an expressively higher occurrence of dynamic faults in FinFET-based SRAMs when compared to CMOS technology.

A Compact Calibration Model for Linearizing CMOS Sample-and-Hold Circuits

Intermediate-Frequency (IF) sampling demands stringent tracking bandwidth and linearity performance of analog-to-digital converters (ADCs), dictating high supply voltages and bipolar devices to implement the front-end buffer/sampler. As quantizers are nowadays almost exclusively realized in scaled CMOS technology, the integration of the high-voltage bipolar front-end and the low-voltage CMOS quantizer becomes a challenging task as cost, complexity, and power consumption are important competitive metrics for vendors. In this brief, we present a compact calibration model to linearize the sample-and-hold (S/H) circuits realized in low-cost CMOS technology for IF-sampling applications. Simulation and experimental results show that a spurious-free dynamic range (SFDR) close to 100 dB can be achieved using the proposed technique.