Scalar Point Multiplication Research Articles

High-performance elliptic curve cryptoprocessors over $$\varvec{GF(2^{m})}$$ G F ( 2 m ) on Koblitz curves

Efficient computation of the finite field arithmetic is required for elliptic curve cryptography over $$G\!F\!(2^{m})$$GF(2m). In order to achieve the above, this paper presents the design of high-performance cryptoprocessors over $$G\!F\!(2^{163})$$GF(2163) and $$G\!F\!(2^{233})$$GF(2233) using finite field multipliers with digit-level processing. The arithmetic operations were implemented in hardware using Gaussian normal bases representation and the scalar point multiplication kP was performed on Koblitz curves using window-$$\tau $$?NAF algorithm with w = 2, 4 and 8. The cryptoprocessors were designed using VHDL description, synthesized on the FPGA Stratix-V using Quartus II 13.0, and verified using ModelSIM and Matlab. The simulation results show that the cryptoprocessors present a very good performance using low area. In this case, the processing times for calculating the scalar point multiplication over $$G\!F\!(2^{163})$$GF(2163) and $$G\!F\!(2^{233})$$GF(2233) for w = 2, 4 and 8 were 9.1, 6.7 and 5.1, and 12.9, 9.5 and 6.8 $$\upmu $$μs, respectively.

PF-ID-2PAKA: Pairing Free Identity-Based Two-Party Authenticated Key Agreement Protocol for Wireless Sensor Networks

To ensure secure communication between any two entities, authenticated key agreement protocol is the primary step and current research has a lot of contribution in this direction. In this paper, we propose a Pairing Free Identity-based Two-Party Authenticated Key Agreement protocol and gather the implementation results for Wireless Sensor Networks on MICAz mote by using Relic-toolkit cryptographic library. The proposed protocol is efficient as it does not use any pairing operation and only uses three scalar point multiplications. The security of the protocol has been proved secure using strongest security model for identity-based key agreement protocol presented by Liang et al.

Efficient and anonymous two-factor user authentication in wireless sensor networks: achieving user anonymity with lightweight sensor computation.

A smart-card-based user authentication scheme for wireless sensor networks (hereafter referred to as a SCA-WSN scheme) is designed to ensure that only users who possess both a smart card and the corresponding password are allowed to gain access to sensor data and their transmissions. Despite many research efforts in recent years, it remains a challenging task to design an efficient SCA-WSN scheme that achieves user anonymity. The majority of published SCA-WSN schemes use only lightweight cryptographic techniques (rather than public-key cryptographic techniques) for the sake of efficiency, and have been demonstrated to suffer from the inability to provide user anonymity. Some schemes employ elliptic curve cryptography for better security but require sensors with strict resource constraints to perform computationally expensive scalar-point multiplications; despite the increased computational requirements, these schemes do not provide user anonymity. In this paper, we present a new SCA-WSN scheme that not only achieves user anonymity but also is efficient in terms of the computation loads for sensors. Our scheme employs elliptic curve cryptography but restricts its use only to anonymous user-to-gateway authentication, thereby allowing sensors to perform only lightweight cryptographic operations. Our scheme also enjoys provable security in a formal model extended from the widely accepted Bellare-Pointcheval-Rogaway (2000) model to capture the user anonymity property and various SCA-WSN specific attacks (e.g., stolen smart card attacks, node capture attacks, privileged insider attacks, and stolen verifier attacks).

A High Performance FPGA Implementation of 256-bit Elliptic Curve Cryptography Processor Over GF(<i>p</i>)

Field Programmable Gate Array (FPGA) implementation of Elliptic Curve Cryptography (ECC) over GF(p) is commonly not fast enough to meet the request of high-performance applications. There are three critical factors to determine the performance of ECC processor over GF(p): multiplication structure, modular multiplication algorithm, and scalar point multiplication scheduling. This work proposes a novel multiplication structure which is a two-stage pipeline on the basis of Karatsuba-Ofman algorithm. With the proposed multiplication structure, we design a 256-bit modular multiplier based on Improved Barret Modular Multiplication algorithm. Upon the modular multiplier, we finish the scalar point multiplication scheduling and implement a high-performance ECC processor on FPGA. Compared with the previous modular multipliers, our modular multiplier reduces the 256-bit modular multiplication time by 28% at least. Synthesis result on Altera Stratix II shows that our ECC processor can complete a 256-bit ECC scalar point multiplication in 0.51ms, which is at least 1.3 times faster than the currently reported FPGA ECC processors over GF(p).

Design of an Elliptic Curve Cryptography processor for RFID tag chips.

Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip.

Efficient Algorithm for Tate Pairing of Composite Order

Boneh et al. proposed the new idea of pairing-based cryptography by using the composite order group instead of prime order group. Recently, many cryptographic schemes using pairings of composite order group were proposed. Miller's algorithm is used to compute pairings, and the time of computing the pairings depends on the cost of calculating the Miller loop. As a method of speeding up calculations of the pairings of prime order, the number of iterations of the Miller loop can be reduced by choosing a prime order of low Hamming weight. However, it is difficult to choose a particular composite order that can speed up the pairings of composite order. Kobayashi et al. proposed an efficient algorithm for computing Miller's algorithm by using a window method, called Window Miller's algorithm. We can compute scalar multiplication of points on elliptic curves by using a window hybrid binary-ternary form (w-HBTF). In this paper, we propose a Miller's algorithm that uses w-HBTF to compute Tate pairing efficiently. This algorithm needs a precomputation both of the points on an elliptic curve and rational functions. The proposed algorithm was implemented in Java on a PC and compared with Window Miller's Algorithm in terms of the time and memory needed to make their precomputed tables. We used the supersingular elliptic curve y2=x3+x with embedding degree 2 and a composite order of size of 2048-bit. We denote w as window width. The proposed algorithm with w=6=2·3 was about 12.9% faster than Window Miller's Algorithm with w=2 although the memory size of these algorithms is the same. Moreover, the proposed algorithm with w=162=2·34 was about 12.2% faster than Window Miller's algorithm with w=7.

Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over ${\rm GF}(2^{163})$

A new and highly efficient architecture for elliptic curve scalar point multiplication is presented. To achieve the maximum architectural and timing improvements, we reorganize and reorder the critical path of the Lopez-Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical paths. The results we obtained show that with G=55 our proposed design is able to compute scalar multiplication over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">163</sup> ) in 9.6 μs with the maximum achievable frequency of 250 MHz on Xilinx Virtex-4 (XC4VLX200), where G is the digit size of the underlying digit-serial finite-field multiplier. Another implementation variant for less resource consumption is also proposed; with G=33, the design performs the same operation in 11.6 μs at 263 MHz on the same platform. The results of synthesis show that, in the first implementation, 17 929 slices or 20% of the chip area is occupied, which makes it suitable for speed-critical cryptographic applications, while in the second implementation 14203 slices or 16% of the chip area is utilized, which makes it suitable for applications that may require speed-area tradeoff.

Fast Elliptic Curve Point Multiplication Algorithm Optimization

Scalar point multiplication operation on elliptic curve is the most expensive part of the elliptic curve cryptosystem, also has always been the hot spot of the research. Recoding the positive integer and reducing the amount of inversion in the operation are the two main ideas. In this article, we use the balanced ternary form to recode the positive integer, at the same time, improve the part of calculation way of, reducing the amount of inversion, decreasing operation cost, and improving operation efficiency

An Efficient Verifiably Encrypted Signature from Weil Pairing

A verifiably encrypted signature (VES) is a kind of very useful signature in online optimistic contract signing protocols. VES enables fair exchange between participants in signing protocols, which can allow the verifier to test that a given ciphertext is the encryption of a signature on a given message. In this paper, a novel efficient VES scheme which makes use of Weil pairing is proposed. The proposed signature scheme can provide good security properties such as validity, unforgeability, and opacity. We analyze the security and efficiency of the proposed scheme. Compared with the previous schemes, the proposed VES schemes is more efficient in terms of computational cost. In particular, the total computational cost of the three important phases of VES signing, VES verification, and adjudication in our scheme is decreased by at least 4M, where M indicates a scalar point multiplication. In addition, the signature size in our scheme is reduced to half of the size used in the previous schemes.

Elliptic Curve Cryptography in Securing Networks by Mobile Authentication

This paper proposes an enhanced authentication model, which is suitable for low-power mobile devices. It uses an Extended Password Key Exchange Protocols (2) and elliptic-curve-cryptosystem based trust delegation mechanism to generate a delegation pass code for mobile station authentication, and it can effectively defend all known attacks to mobile networks including the denial-of-service attack. Moreover, the mobile station only needs to receive one message and send one message to authenticate itself to a visitor's location register, and the model only requires a single elliptic-curve scalar point multiplication on a mobile device. Therefore, this model enjoys both computation efficiency and communication efficiency as compared to known mobile authentication models.

AN EFFICIENT AND SECURE STRONG DESIGNATED VERIFIER SIGNATURE SCHEME WITHOUT BILINEAR PAIRINGS

In literature, several strong designated verifier signature (SDVS) schemes have been devised using elliptic curve bilinear pairing and map-topoint (MTP) hash function. The bilinear pairing requires a super-singular elliptic curve group having large number of elements and the relative computation cost of it is approximately two to three times higher than that of elliptic curve point multiplication, which indicates that bilinear pairing is an expensive operation. Moreover, the MTP function, which maps a user identity into an elliptic curve point, is more expensive than an elliptic curve scalar point multiplication. Hence, the SDVS schemes from bilinear pairing and MTP hash function are not efficient in real environments. Thus, a cost-efficient SDVS scheme using elliptic curve cryptography with pairingfree operation is proposed in this paper that instead of MTP hash function uses a general cryptographic hash function. The security analysis shows that our scheme is secure in the random oracle model with the hardness assumption of CDH problem. In addition, the formal security validation of the proposed scheme is done using AVISPA tool (Automated Validation of Internet Security Protocols and Applications) that demonstrated that our scheme is unforgeable against passive and active attacks. Our scheme also satisfies the different properties of an SDVS scheme including strongness, source hiding, non-transferability and unforgeability. The comparison of our scheme with others are given, which shows that it outperforms in terms of security, computation cost and bandwidth requirement.

High performance MAC unit for DSP and cryptographic applications

Multiplication and addition are the basic arithmetic operation used in Digital Signal Processing (DSP) for coefficient multiplication, scalar point multiplication in Elliptic Curve Cryptography (ECC) and in other fields. Multiplications are basically a shift and add operation. However, there are many different variations on how to do it. Some are more suitable to implement on FPGA than others. However time complexities and hardware complexities are the major issues in designing a multiplier unit. There are different multiplication algorithms in current technology. Hardware complexities in some design are more than time complexities whereas in some other design time complexities are more. However there must be a tradeoff between these two types of methodology. This paper will discuss a brief idea how a tradeoff can be achieved. Experimental results that have discussed here and the architecture based on the proposed algorithm shows it's novelty. Applications of the proposed algorithm on DSP and ECC have been dealt here clearly.

Elliptic Curve Cryptography in Securing Networks by Mobile Authentication

This paper proposes an enhanced authentication model, which is suitable for low-power mobile devices. It uses an Extended Password Key Exchange Protocols and elliptic-curve-cryptosystem based trust delegation mechanism to generate a delegation pass code for mobile station authentication, and it can effectively defend all known attacks to mobile networks including the denial-of-service attack. Moreover, the mobile station only needs to receive one message and send one message to authenticate itself to a visitor’s location register, and the model only requires a single elliptic-curve scalar point multiplication on a mobile device. Therefore, this model enjoys both computation efficiency and communication efficiency as compared to known mobile authentication models.

Low-Latency Elliptic Curve Scalar Multiplication

This paper presents a low-latency algorithm designed for parallel computer architectures to compute the scalar multiplication of elliptic curve points based on approaches from cryptographic side-channel analysis. A graphics processing unit implementation using a standardized elliptic curve over a 224-bit prime field, complying with the new 112-bit security level, computes the scalar multiplication in 1.9 ms on the NVIDIA GTX 500 architecture family. The presented methods and implementation considerations can be applied to any parallel 32-bit architecture.

Design of a high performance Binary Edwards Curve based processor secured against side channel analysis

Elliptic curve cryptography (ECC) is in prime focus in the domain of public-key cryptography (PKC) due to its advantage over RSA with smaller bit requirement. Still, this curve has some major issues in terms of unifiedness and completeness. In 2007, Edwards curve has proved to be the answer to such deficiencies with its unified addition law. This curve has been recently extended to Binary Edwards Curves (BEC), due to efficiency of implementation in GF(2m) fields and to harvest the advantages of a unified and complete scalar point multiplication on the family of BEC. In spite of achieving the unification, it introduces more challenges to the designer to reduce the computation time and trade-off the area in efficient way. A noble architecture of a BEC processor is proposed in this work in GF(2233). We further analyze the work in terms of simple power analysis. Through experimentations, we show that the naive implementation can reveal some important information about the secret key. Finally, we conclude the work with suitable modifications to prevent such side-channel attacks.

An Efficient and Provably-secure Digital signature Scheme based on Elliptic Curve Bilinear Pairings

We proposed an efficient and secure digital signature scheme using elliptic curve cryptography (ECC) and bilinear pairings in this paper. The proposed scheme employs the general cryptographic hash function (i.e., SHA-1) instead of map-to-point function, because the map-to-point is a cost-intensive operation and it is usually implemented as a probabilistic algorithm. Further, our scheme is computationally efficient as one bilinear paring and three elliptic curve scalar point multiplication operations are executed for signature generation and verification, and thus the scheme requires much lesser computation cost than other related schemes. In addition, in the random oracle model, our scheme is proven to be existential unforgeable against the adaptive chosen message and identity attacks (EUF-CMA) based on a variation of the collusion attack algorithm with ktraitors (k-CAA3) problem.

Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications

We present an elliptic curve cryptographic (ECC) processor, capable of parallel and serial operation modes, with the unified architecture for both prime field and binary field cryptosystems, featuring comprehensive cryptographic functions to fulfill realistic security applications. An advanced field inversion method and the scheduler-controlled datapath are integrated into the processor to provide high-throughput and energy-adaptive security computing with power-performance trade off. Using 130-nm CMOS technology, the fabricated chip measures 4.97 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with the core area of 1.35 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A 160-bit point scalar multiplication with coordinate conversion can be done in 385 μ s at 141 MHz with core power of 80.4 mW over <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GF</i> ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> ) and in 272 μs at 158 MHz with 79.6 mW over <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GF</i> (2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ). The comparison of throughput, area, power, and energy consumption among different ECC designs justifies that our high-throughput processor chip provides power- and energy-efficient implementation with the flexibility of dual-field ECC.

Fast Reconfigurable Elliptic Curve Cryptography Acceleration for GF(2 m ) on 32 bit Processors

This paper focuses on the design and implementation of a fast reconfigurable method for elliptic curve cryptography acceleration in GF(2 m ). The main contribution of this paper is comparing different reconfigurable modular multiplication methods and modular reduction methods for software implementation on Intel IA-32 processors, optimizing point arithmetic to reduce the number of expensive reduction operations through a novel reduction sharing technique, and measuring performance for scalar point multiplication in GF(2 m ) on Intel IA-32 processors. This paper determined that systematic reduction is best for fields defined with trinomials or pentanomials; however, for fields defined with reduction polynomials with large Hamming weight Barrett reduction is best. In GF(2571) for Intel P4 2.8 GHz processor, long multiplication with systematic reduction was 2.18 and 2.26 times faster than long multiplication with Barrett or Montgomery reduction. This paper determined that Montgomery Invariant scalar point multiplication with Systematic reduction in Projective coordinates was the fastest method for single scalar point multiplication for the NIST fields from GF(2163) to GF(2571). For single scalar point multiplication on a reconfigurable elliptic curve cryptography accelerator, we were able to achieve ~6.1 times speedup using reconfigurable reduction methods with long multiplication, Montgomery's MSB Invariant method in projective coordinates, and systematic reduction. Further extensions were made to implement fast reconfigurable elliptic curve cryptography for repeated scalar point multiplication on the same base point. We also show that for L?>?20 the LSB invariant method combined with affine doubling precomputation outperforms the LSB invariant method combined with Lopez-Dahab doubling precomputation for all reconfigurable reduction polynomial techniques in GF(2571) for Intel IA-32 processors. For L?=?1000, the LSB invariant scalar point multiplication method was 13.78 to 34.32% faster than using the fastest Montgomery Invariant scalar point multiplication method on Intel IA-32 processors.

A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography

This brief presents a high-throughput dual-field elliptic-curve-cryptography (ECC) processor that features all ECC functions with the programmable field and curve parameters over both the prime and binary fields. The proposed architecture is parallel and scalable. Using 0.13-mum CMOS technology, the core size of the processor is 1.44 mm2 . The measured results show that our ECC processor can perform one 160-bit point scalar multiplication with coordinate conversion over the prime field in 608 mus at 121 MHz with only 70.0 mW and the binary field in 372 mus at 146 MHz with 82.1 mW. The ECC processor chip outperforms other ECC hardware designs in terms of functionality, scalability, performance, cost effectiveness, and power consumption. In addition, the system analysis shows that our design is very efficient, compared with the software implementation for realistic security applications.

Parallel crypto-devices for GF( p) elliptic curve multiplication resistant against side channel attacks

All elliptic curve cryptographic schemes are based on scalar multiplication of points, and hence its faster computation signifies faster operation. This paper proposes two different parallelization techniques to speedup the GF( p) elliptic curve multiplication in affine coordinates and the corresponding architectures. The proposed implementations are capable of resisting different side channel attacks based on time and power analysis. The 160, 192, 224 and 256 bits implementations of both the architectures have been synthesized and simulated for both FPGA and 0.13 μ CMOS ASIC. The final designs have been prototyped on a Xilinx Virtex-4 xc4vlx200-12ff1513 FPGA board and performance analyzes carried out. The experimental result and performance comparison show better throughput of the proposed implementations as compared to existing reported architectures.