Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications

Abstract

We present an elliptic curve cryptographic (ECC) processor, capable of parallel and serial operation modes, with the unified architecture for both prime field and binary field cryptosystems, featuring comprehensive cryptographic functions to fulfill realistic security applications. An advanced field inversion method and the scheduler-controlled datapath are integrated into the processor to provide high-throughput and energy-adaptive security computing with power-performance trade off. Using 130-nm CMOS technology, the fabricated chip measures 4.97 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with the core area of 1.35 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A 160-bit point scalar multiplication with coordinate conversion can be done in 385 μ s at 141 MHz with core power of 80.4 mW over <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GF</i> ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> ) and in 272 μs at 158 MHz with 79.6 mW over <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GF</i> (2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ). The comparison of throughput, area, power, and energy consumption among different ECC designs justifies that our high-throughput processor chip provides power- and energy-efficient implementation with the flexibility of dual-field ECC.