Area Savings Research Articles

Area-Time Efficient FAST Corner Detector Using Data-Path Transposition

Corner detection plays an essential role in many computer vision applications, e.g., object recognition, motion analysis, and stereo matching. In this brief, we present a novel data-path transposition strategy for the hardware design of the FAST corner detector. The proposed design transposes the data-path of the conventional architecture to enable partial evaluation of multiple corners in a pipelined manner, which reduces the size of the window buffer. Further area savings were achieved by combining the operations for computing the corner scores and determining the member vectors. We show that the proposed design on 180-nm CMOS technology leads to about 22% reduction in the critical path delay and lesser area compared to the previously reported architecture, without a notable difference in energy consumption.

High Performance Static Segment On-Chip Memory for Image Processing Applications

The performance of the processor core depends on the configuration parameters and utilization of on-chip memory in multimedia applications such as image, video and audio processing. The design of the on-chip memory architecture is critical for power and area efficient design without compromising quality in data-intensive computing applications. This paper proposes a design of high speed, area, and energy efficient Static Segment On-Chip (SSOC) memory for error-tolerant applications. In this static segment method, n-bit data array is reduced by m-bit data array for significant value of input data to achieve balanced design metrics at the cost of accuracy. The proposed m-bit static segmentation algorithm is implemented and verified in Single Port Static Random Access Memory (SP SRAM) architecture for the approximate computing applications. From the overall simulation results, the proposed 4-bit SSOC SP SRAM design provides 49.02% area savings, 50.62% power reduction and 16.92% speed improvement at the cost of 0.64% Peak Signal to Noise Ratio (PSNR) and exhibits same visual quality in comparison with the existing 8-bit conventional on-chip SP SRAM design in the image processing applications.

Walking through the Energy-Error Pareto Frontier of Approximate Multipliers

In this article, we target approximate computing for arithmetic circuits, focusing on the most complex and power-hungry units: hardware multipliers. Driven by the lack of a clear solution on the energy-error efficiency of existing approximate multiplication techniques, we present a new, efficient, and easily applied approximation design, as well as explore the current state-of-the-art design space. We show that the proposed approximation scheme can be equally applied at design time to enable synthesis of customized approximate multiplier circuits and at runtime to support dynamic approximation tuning scenarios. We achieve significant gains-up to 69-percent energy and 64-percent area savings with respect to accurate designs-by proposing hybrid approximation performed by two independent techniques that reduce both the depth (through perforation) and the width (through rounding) of the partial products accumulation tree. The corresponding runtime approximation solution delivers energy gains of up to 47 percent, introducing negligible area. More importantly, we show that design solutions configured through the proposed approach form the Pareto frontier of the energy-error space when considering direct quantitative comparisons with existing state of the art.

Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications

Spintronic memories are one of the most promising candidates as a universal memory. Although they offer superior energy efficiency over the conventional memories, benefiting from approximate computing approach, some novel techniques can be applied to lower the power consumption even further. In this brief, we propose a progressive scaling scheme for spin-transfer torque random access memory (STT-RAM) arrays, by which the power consumption is reduced at the expense of small quality degradation. According to the proposed approach, access transistors in STT-RAM cells are scaled based on an optimized scaling factor, where least significant bits and most significant bits come with different bit error rates in the data word. Simulation results show that the proposed approach provides 36.7% write power dissipation and 25% die area savings, respectively, while negligible quality degradation is observed based on mean structural similarity index.

Evaluation of the Impact of Water Management Technologies on Water Savings in the Lower Chenab Canal Command Area, Indus River Basin

Traditional irrigation practices, low crop productivity, unlevelled fields, water losses taking place during conveyance and application phases, as well as low irrigation efficiencies are the main problems of the common farmers in Pakistan. These problems are more noticeable in the command area of Lower Chenab Canal (LCC), which is the main portion of the Indus Basin Project in Pakistan. To overcome these problems, different water management technologies such as precision land levelling (PLL), bed planting, drip irrigation systems, and watercourse improvement were introduced to farmers to increase water savings and crop yields in the area of five distributaries—Khurrianwala, Shahkot, Mungi, Khikhi, Killianwala and Dijkot—during the cropping seasons of 2008 to 2015. The use of drip irrigation resulted in savings of water and fertilizer and increased the crop yields by 30–40%. Three watercourses, one on each site of 1200 m in length, were lined, which resulted in improved conveyance efficiency of 15–20%. If wheat, rice and cotton in the command area of LCC are sown on precisely levelled fields and on beds, then about 2768.1 million m3 and 3699.3 million m3 of irrigation water can be saved. These results show the potential of water-efficient technologies for saving water as well as increasing crop yields.

New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications

Shifting an input data by variable amounts is commonly found in arithmetic operations, data encoding and bit-indexing. Although some shift amounts along the entire shift range are not required, the typical realization by a full-range logarithm shifter requires full implementation and therefore suffers from complexity and power overhead. In this paper, the notion of sporadic logarithmic shifter (SLS) is introduced for the first time, and a new design methodology is proposed for its optimization. By reusing parts of existing substructure of conventional logarithmic shifter or post-multiplexing the hardwired shifts, contagious subranges of desirable shift amounts are successively realized. Synthesis results on 8-bit and 16-bit SLSs show average application-specified integrated circuit area and power savings of up to 73.24% and 63.90%, respectively, over conventional logarithmic shifters. In addition, by applying the proposed SLSs to the discrete cosine transform (DCT) architecture, at least 47.5% area savings and 2.9% power savings can be achieved over two constant multipliers-based DCT architectures reported in the literature.

Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection

Soft errors produced by radiation events can cause malfunctions in modern day electronics. To preserve the system functionality, its elements must be protected against the effects of these events. Two of the possible techniques usually employed to implement fault tolerant registers are triple modular redundancy (TMR) and single error correcting (SEC) codes. However, the use of these techniques increases circuit area, timing, and power consumption to different extents. In this paper, we study the influence of each of these approaches on the circuit when they are implemented in application-specific integrated circuits and, based on the results, present some guidelines to choose between both of them depending on the design requirements. Additionally, we present a new low power fault tolerant technique destined for registers in which a subset of bits have a lower switching activity than the rest. This approach is based on the idea of combining TMR and SEC codes within a register to implement a hybrid protection that can exploit the strengths of each of the techniques. Our results show that the use of this technique achieves both power and area savings with respect to TMR in most cases, whereas it achieves large power savings with respect to SEC codes at the cost of increasing the area overhead.

Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time Applications

The semiconductor industry is strategically focusing on automotive markets, and significant investment is targeted to addressing these markets. Runtime better-than-worst-case designs like Razor lead to massive timing errors upon breaching the critical operating point and have significant area overheads. As we scale to higher-reliability automotive and industrial markets we need alternative techniques that will allow full extraction of the power benefits without sacrificing reliability. The proposed method utilizes positive slack available in the pipeline stages and re-distributes it to the preceding critical logic stage using Slack Balancing Flip-Flops (SBFFs). We use opportunistic under designing to get rid of the area, power and error correction overheads associated with the speculative hardware of runtime techniques. The proposed logic reshaping results in 12 percent and eight percent power and area savings respectively compared to the worst-case design approach. Compared to runtime better-than-worst-case designs, we get 51 percent and 10 percent power and area savings, respectively. In addition, the timing budgeting and timing correction using opportunistic slack eliminate critical operating point behavior, metastability issues and hold buffer overheads encountered in existing runtime resilience techniques.

Majority Voting-Based Reduced Precision Redundancy Adders

Fault-tolerant systems are usually implemented with triple modular redundancy (TMR)-based protection techniques which has a huge area and power overhead. Previous works have shown that this overhead can be improved by using reduced precision redundancy (RPR)-based approaches for intrinsically precision-tolerant applications like image and video processing. The error detection and steering logic required in the RPR schemes utilize subtraction and comparisons which are more complex hardware operations than TMR voting. This overhead is affordable for complex hardware structures, for example, finite impulse response filters, but for simple structures like adders, it can be significant. In this letter, it is shown that combining the traditional TMR voting with the RPR brings up considerable savings in area and power budget when applied to very-large-scale integration adder circuits.

Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers

Approximate computing forms a design alternative that exploits the intrinsic error resilience of various applications and produces energy-efficient circuits with small accuracy loss. In this paper, we propose an approximate hybrid high radix encoding for generating the partial products in signed multiplications that encodes the most significant bits with the accurate radix-4 encoding and the least significant bits with an approximate higher radix encoding. The approximations are performed by rounding the high radix values to their nearest power of two. The proposed technique can be configured to achieve the desired energy-accuracy tradeoffs. Compared with the accurate radix-4 multiplier, the proposed multipliers deliver up to 56% energy and 55% area savings, when operating at the same frequency, while the imposed error is bounded by a Gaussian distribution with near-zero average. Moreover, the proposed multipliers are compared with state-of-the-art inexact multipliers, outperforming them by up to 40% in energy consumption, for similar error values. Finally, we demonstrate the scalability of our technique.

Efficient Coding Architectures for Reed–Solomon and Low-Density Parity-Check Decoders for Magnetic and Other Data Storage Systems

High-performance error correction codes are used in high-density data storage devices to overcome noise and channel impairments. In this paper, we develop novel and efficient decoding architectures for Reed-Solomon (RS) and low-density parity-check (LDPC) codes that are used in almost all data storage devices. First, we present a high-speed low-latency hard-decision-based pipelined RS decoder architecture that computes the error locator polynomial in exactly 2t clock cycles without parallelism. The RS decoder is a two-stage pipelined engine operating at the least latency possible, thereby, significantly reducing the size of the delay buffer. The RS decoder is implemented using Cadence tools and Kintex-7 field programmable gate array (FPGA). The technology-scaled normalized throughput of the pipelined RS decoder is almost two times compared with the existing decoders. The overall processing latency is reduced by almost 80% compared with the existing designs. Second, we design a high-throughput LDPC decoder using layered and non-layered min-sum algorithm based on non-uniform quantization (NUQ) on an FPGA kit. Unlike the standard state-of-the-art uniform quantization used in virtually all decoder circuits, our NUQ technique: 1) achieves a slight performance improvement of similar to 0.1 dB in the signal-to-noise ratio using equal number of bits and 2) yields 20% area savings (using 1 bit less) for the block RAMs used for storing intermediate check node and variable node messages.

Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters

Finite-impulse response filters are widely used in digital signal processing applications. Prodigious research in the past two decades has substantially reduced the implementation cost of the multiple constant multiplication blocks. Further area and power consumption savings are stagnated by the structural adders and registers in the tap delay-and-accumulate line, which unfortunately dominate the overall hardware cost of FIR filter and are difficult to minimize by existing resource sharing approaches. Retiming or relocating the structural adders and registers can improve merely the throughput. To close the area-power efficiency gap, we reformulate the filter coefficient synthesis problem to explore the design space for the tap delay-and accumulate line by bisecting at some tap position. An efficient Genetic Algorithm is proposed to solve this integer programming problem at quadratic computational complexity by refining the search space for finding an optimized solution to fulfill the frequency response specifications. Field programmable gate array and application specific integrated circuit logic synthesis results from twelve benchmark filter specifications showed that the average area and power consumptions of the solutions generated by our proposed algorithm have been reduced by up to 26.8% and 27.5% respectively, in comparison with the solutions obtained by existing design methods.

Low Cost Convolutional Neural Network Accelerator Based on Bi-Directional Filtering and Bit-Width Reduction

This paper presents a low-area and energy-efficient hardware accelerator for the convolutional neural networks (CNNs). Based on the multiply-accumulate-based architecture, three design techniques are proposed to reduce the hardware cost of the convolutional computations. First, to reduce the computational cost of convolutions, an adaptive bit-width reduction combined with near-zero skipping is proposed based on differential input method (DIM). The DIM-based design technique can reduce 62.5% of operation bit-width and improve 17.0% of activation sparsity with almost ignorable CNN accuracy degradation. Second, it has been found that adopting a bi-directional filtering window in a CNN accelerator can considerably reduce the energy for data movement with a much smaller number of memory accesses. To expedite the bi-directional filtering operations, we also propose a bi-directional first-input-first-output (bi-FIFO). With SRAM bit-cell layout manner, the proposed bi-FIFO facilitates fast data re-distribution with area and energy efficiency. To verify the effectiveness of the proposed techniques, the AlexNet accelerator has been designed. The numerical results show that the proposed adaptive bit-width reduction scheme achieves 34.6% and 58.2% of area and energy savings, respectively. The bi-FIFO-based accelerator also achieves 32.8% improved processing time.

Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits

In the paradigm of stochastic computing, arithmetic functions are computed on randomized bit streams. The method naturally and effectively tolerates very high clock skew. Exploiting this advantage, this paper introduces polysynchronous clocking, a design strategy in which clock domains are split at a very fine level. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock distribution network can be relaxed. This allows for a higher working frequency and so lower latency. The benefits of both approaches are quantified. Polysynchronous clocking results in significant latency, area, and energy savings for wide variety of applications.

A Dual-Clock Multiple-Queue Shared Buffer

Multiple parallel queues are versatile hardware data structures that are extensively used in modern digital systems. To achieve maximum scalability, the multiple queues are built on top of a dynamically-allocated shared buffer that allocates the buffer space to the various active queues, based on a linked-list organization. This work focuses on dynamically-allocated multiple-queue shared buffers that allow their read and write ports to operate in different clock domains. The proposed dual-clock shared buffer follows a tightly-coupled organization that merges the tasks of signal synchronization across asynchronous clock domains and queueing (buffering), in a common hardware module. When compared to other state-of-the-art dual-clock multiple-queue designs, the new architecture is demonstrated to yield a substantially lower-cost implementation. Specifically, hardware area savings of up to 55 percent are achieved, while still supporting full-throughput operation.

Development and Testing of Innovative SOFC System Prototype with Staged Stack Connection for Efficient Stationary Power and Heat Generation

Solid oxide fuel cells (SOFC) are ideally suited to the conversion of hydrocarbons at high electrical efficiencies. The essential advantage of SOFC based CHP systems besides high electrical efficiency is the independence of electrical efficiency from system size. Therefore, residential heat and power generation (multi-family homes) is considered as the largest potential market followed by commercial applications involving year-round heat demand (hotels, laundries, etc.). The load profiles of these applications were used to define basic prototype system specifications across parameters like system power output, heat production, efficiency and part load capability. In order to establish environmentally friendly small-scale CHP units in the range of 5 to 50 kW, a concept with serial connection of two SOFC stacks and an electrical efficiency of up to 50 % was developed. The idea behind STAGE-SOFC is to couple an exothermal CPOX stage with one or multiple endothermic steam reforming stages and thus, combining the benefits of a simple, robust CPOX layout with high efficiencies achievable using a steam reforming process. This concept allows to save error-prone, maintenance-intensive water supplies or costly equipment for anode off-gas recirculation and to ensure a simple and compact design. The STAGE-SOFC system is set up for natural gas operation and requires one CPOX reformer and one steam reformer for fuel processing as well as an after burner for post-combustion of anode-off gas. In addition, a staged cathode air supply facilitates individual stack temperature control and savings in costly heat exchanger area. Building a working SOFC-system based on a completely new system layout requires a lot of detailed simulations. For a robust system layout, the most important simulations are not performed in the vicinity of the nominal operating point, since limiting factors for system operation come to light in extreme conditions. To push the performance of the system to its limits, the selection of the nominal operating point must be optimal. A simulation method based on classical design experiment methods was developed in this project, allowing massive multidimensional parameter scans to find out the optimal operation points. For verification of the basic layout and system operability a thermally self-sustained and completely integrated 5 kW prototype system was developed. The testing of the prototype was focused on the variation of parameters like electrical load, CPOX air ratio, O/C ratio, fuel utilization and their influence on the system performance. The prototype system was operated for more than 600 hours under various parameters and stable loads from 1.5 to 5.3 kW(AC). It was possible to achieve an electrical efficiency of 50 % in part load and 45 % at 5 kW power output. Significant experience for improvement of main components and system controllability was gained during the testing. After detailed evaluation of the testing data a new hotbox layout with improved components for better thermal and functional integration was developed. The new design was kept as simple as possible to reduce the manufacturing costs. Flow-sheet simulations and testing of the first prototype revealed that the extent of methane reforming is not high enough with an adiabatic reformer. To drive methane conversion further, a compact heated reformer unit it was developed using a simple plate-type heat exchanger with a precious metal catalyst coating on the plate surface to reform natural gas with anode-off gas. Experimental investigations of the reformer performance were carried out in a test bench with model gas feeds for 150 h. The reformer testing conditions were based on operating results of the first prototype system. Furthermore, a new integrated burner concept for both, non-premixed anode-off gas combustion and premixed natural gas combustion in one combined burner unit was developed. Combustion experiments are often challenging and dangerous due to the presence of reactive mixture that may explode. Thus, a virtual prototyping analysis over the new burner design was carried out using the CFD technique. The developed model has supported the understanding of complex interactions between reactive flows and has delivered input for design optimization. The goal was to analyze the location of high temperature regions and emission characteristics in the new burner type under operating conditions at different flow regimes and molar concentrations. The second STAGE-SOFC prototype is currently under manufacturing. After successful commissioning this proof-of-concept prototype will be transferred to project partner ICI Caldaie, where it will be tested for at least 3000 hours under real operating conditions starting in April 2017. Figure 1

Bespoke Processors for Applications with Ultra-low Area and Power Constraints

A large number of emerging applications such as implantables, wearables, printed electronics, and IoT have ultra-low area and power constraints. These applications rely on ultra-low-power general purpose microcontrollers and microprocessors, making them the most abundant type of processor produced and used today. While general purpose processors have several advantages, such as amortized development cost across many applications, they are significantly over-provisioned for many area- and power-constrained systems, which tend to run only one or a small number of applications over their lifetime. In this paper, we make a case for bespoke processor design, an automated approach that tailors a general purpose processor IP to a target application by removing all gates from the design that can never be used by the application. Since removed gates are never used by an application, bespoke processors can achieve significantly lower area and power than their general purpose counterparts without any performance degradation. Also, gate removal can expose additional timing slack that can be exploited to increase area and power savings or performance of a bespoke design. Bespoke processor design reduces area and power by 62% and 50%, on average, while exploiting exposed timing slack improves average power savings to 65%.

Impact of climate resilient technologies in rainfed agro-ecosystem

Climate change has been given the dubious moniker for asymmetrical development of Indian economy in general and agriculture sector in particular. Climate resilient technologies are promising tool to guard a farming system from climatic variations. National Initiative on Climate Resilient Agriculture (NICRA) has demonstrated, and promoted application of climate resilient technologies in most vulnerable 100 districts. This study has been conducted to recognize the technological and socio-economic impact of these technologies upon the society. To enable impact assessment the study employed with –without and before-after comparison, of samples of two NICRA and two non-NICRA villages constituting 120 respondents. Among the technologies demonstrated in the NICRA villages, improved soil and land management practices, water management practices, crop production interventions and cropping system interventions were compared. Various analyses demonstrated that significant difference between NICRA and non-NICRA, farmers on cropping intensity, crop diversification, average irrigated land area and irrigation frequency, employment generation, land area (leased in) and annual savings, with a favorable tilt towards NICRA group. Before-after comparison of NICRA group, to isolate the project impact also testified significant improvement on a set of indicators like average irrigated land area and irrigation frequency, employment generation, land area (leased in), savings, crop yield and expenditure pattern. The study thus provides a springboard for the policy makers and civil societies to stretch out the activities for wide adaptation.

Design and Applications of Approximate Circuits by Gate-Level Pruning

Energy-efficiency is a critical concern for many systems, ranging from Internet of things objects and mobile devices to high-performance computers. Moreover, after 40 years of prosperity, Moore’s law is starting to show its economic and technical limits. Noticing that many circuits are over-engineered and that many applications are error-resilient or require less precision than offered by the existing hardware, approximate computing has emerged as a potential solution to pursue improvements of digital circuits. In this regard, a technique to systematically tradeoff accuracy in exchange for area, power, and delay savings in digital circuits is proposed: gate-level pruning (GLP). A CAD tool is build and integrated into a standard digital flow to offer a wide range of cost-accuracy tradeoffs for any conventional design. The methodology is first demonstrated on adders, achieving up to 78% energy-delay-area reduction for 10% mean relative error. It is then detailed how this methodology can be applied on a more complex system composed of a multitude of arithmetic blocks and memory: the discrete cosine transform (DCT), which is a key building block for image and video processing applications. Even though arithmetic circuits represent less than 4% of the entire DCT area, it is shown that the GLP technique can lead to 21% energy-delay-area savings over the entire system for a reasonable image quality loss of 24 dB. This significant saving is achieved thanks to the pruned arithmetic circuits, which sets some nodes at constant values, enabling the synthesis tool to further simplify the circuit and memory.

Design and Implementation of 32-Bit High Valency Jackson Adders

Parallel prefix addition offers a highly efficient solution to most of the applications which requires fast addition of two binary numbers. An efficient adder design demands proper selection of recurrence equations and its realization. There are different recursion equations like Weinberger recursion, Ling recursion, Jackson recursion, to name a few, available to suit a variety of design requirements. In this work, we have proposed adders based on Jackson recursion. In these adders, the complexity found in generate term is reduced at all the levels of the carry graph to optimize the adder performance parameters. The proposed adder structures are implemented for a word size of 32-bit based on the Jackson recursion equations for valency-4 and valency-5. The synthesis results reveal that the high-valency Jackson adder structures are superior in terms of power and area over the Ling adders for comparable delay values. Experimental results obtained reveals that an average of [Formula: see text] and [Formula: see text] savings in area and power, respectively, are achieved by the proposed adders, as compared to Ling adders for the same word size. Furthermore, the proposed adders demonstrate enhanced area-delay and the power-delay values compared to the adders based on the Weinberger’s recursion.