Area Savings Research Articles

An optimal device sizing for a performance-driven and area-efficient subthreshold cell library for IoT applications

Ultra-low power design techniques specifically subthreshold designs, play a vital role in Internet of things systems that survive on limited power budget or harvested energy sources. In this paper, the width and length of a transistor operating at subthreshold region are optimized considering the nano-scale effects such as reverse short channel effect and inverse narrow width effect, which improves performance, reduces area, minimizes sensitivity to process variation and reduces energy consumption. A subthreshold standard cell library consisting of 45 standard cells is designed. The physical synthesis of ISCAS′85 benchmark circuits and a floating point unit shows that energy savings in area-mapped design are up to 23% whereas area savings in performance-mapped design are up to 30%. The measurement results from a test chip fabricated in industrial 130 nm technology demonstrate a performance improvement of up to 27%, reduction in delay variability of up to 24% and energy savings of 18%.

Energy‐efficient VLSI implementation of multipliers with double LSB operands

Multiplication is an arithmetic operation that has a significant impact on the performance of various real-life applications, such as digital signal processing, image processing and computer vision. In this study, targeting to exploit the efficiency of alternative number representation formats, the authors propose an energy-efficient scheme for multiplying 2's-complement binary numbers with two least significant bits (LSBs). The double-LSB (DLSB) arithmetic delivers several benefits, such as the symmetric representation range, the number negation performed only by bitwise inversion, and the facilitation of the rounding process in the results of floating point architectures. The hardware overhead of the proposed circuit, when implemented at 45 nm, is negligible in comparison with the conventional Modified Booth multiplier for the ordinary 2's-complement numbers (3.1% area and 3.3% energy average overhead for different multiplier's bit-width). Moreover, the proposed DLSB multiplier outperforms the previous state-of-the-art implementation by providing 10.2% energy and 7.8% area average gains. Finally, they demonstrate how the DLSB multipliers can be effectively used as a building block for the implementation of larger multiplications, delivering area and energy savings.

432 nW per Channel 130 nV/rtHz ECG Acquisition Front End With Multifrequency Chopping

An ultralow-power low-noise analog front end (AFE) for ECG signal acquisition is demonstrated. The key to its performance is a multifrequency chopping technique that helps to significantly reduce power consumption by frequency-division multiplexing of two channels in a single low-noise instrumentation amplifier (IA). A complete two-channel AFE, chopped at frequencies of 4 and 8 kHz, is implemented in a 0.13- $\mu \text{m}$ CMOS technology from United Microelectronics Corporation. A current-reuse technique is employed in the first stage of the IA to achieve area savings and improve interchannel isolation. Experimental results show that the front end achieves an input-referred noise voltage density of 130 nV/rtHz while consuming current of 360 nA per channel from a 1.2-V power supply. The 1/f noise corner of the system is around 10 Hz, and the measured common-mode rejection ratio (CMRR) is 98 dB.

Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols

Public key cryptography protocols, such as RSA and elliptic curve cryptography, will be rendered insecure by Shor’s algorithm when large-scale quantum computers are built. Cryptographers are working on quantum-resistant algorithms, and lattice-based cryptography has emerged as a prime candidate. However, high computational complexity of these algorithms makes it challenging to implement lattice-based protocols on low-power embedded devices. To address this challenge, we present Sapphire – a lattice cryptography processor with configurable parameters. Efficient sampling, with a SHA-3-based PRNG, provides two orders of magnitude energy savings; a single-port RAM-based number theoretic transform memory architecture is proposed, which provides 124k-gate area savings; while a low-power modular arithmetic unit accelerates polynomial computations. Our test chip was fabricated in TSMC 40nm low-power CMOS process, with the Sapphire cryptographic core occupying 0.28 mm2 area consisting of 106k logic gates and 40.25 KB SRAM. Sapphire can be programmed with custom instructions for polynomial arithmetic and sampling, and it is coupled with a low-power RISC-V micro-processor to demonstrate NIST Round 2 lattice-based CCA-secure key encapsulation and signature protocols Frodo, NewHope, qTESLA, CRYSTALS-Kyber and CRYSTALS-Dilithium, achieving up to an order of magnitude improvement in performance and energy-efficiency compared to state-of-the-art hardware implementations. All key building blocks of Sapphire are constant-time and secure against timing and simple power analysis side-channel attacks. We also discuss how masking-based DPA countermeasures can be implemented on the Sapphire core without any changes to the hardware.

A closed-loop ASIC design approach based on logical effort theory and artificial neural networks

Standard cell library is the backbone of modern day application specific integrated circuit (ASIC) design flow provided by electronic design automation (EDA) vendors worldwide. In these libraries, standard cells are generally available in terms of discrete drive strengths with higher drive strength indicating a faster version of the cell belonging to some predefined logic functionality. However, this leads to increased values of area and power consumption in comparison to a lower drive strength standard cell which has slower response time indicating the underlying tradeoff between speed, area and power. A standard cell with discrete drive strength is not always required during the process of logic synthesis and non-availability of standard cells with fractional drive strengths in the aforementioned libraries hugely impacts the overall performance of resulting digital integrated circuits (ICs) and systems [1]. In this paper, a novel technique has been introduced for on-demand generation and inclusion of standard cells in the logic synthesis process leading to availability of a continuous spectrum of standard cells in terms of drive strengths which ultimately provides a platform for closed-loop ASIC design flow. Logical effort (LE) theory has been utilized alongside artificial neural networks (ANNs) in order to implement the proposed methodology. Extensive circuit simulations have been performed using HSPICE in 130 nm/1.2 V CMOS process technology. Preliminary results are encouraging with up to 41.7% and 62.8% reduction in power-delay product (PDP) and power-delay-area product (PDAP) for a 5-stage gate level test circuit. An 8-bit counter realized using the proposed methodology shows up to 29.77% reduction in power dissipation and 37.8% savings in area at varying capacitive loads when compared to conventional logic synthesis technique which employs a library comprising of standard cells with discrete drive strengths. It is noteworthy that the proposed approach is a general technique which can be easily mapped to high complexity circuits and advanced technology nodes. To support this fact, simulation results have also been provided at 90 nm/1 V CMOS process node for the 5-stage test circuit.

Energy efficient VLSI architecture of real‐valued serial pipelined FFT

This study presents an energy-efficient serial pipelined architecture of fast Fourier transform (FFT) to process real-valued signals. A new data mapping scheme is presented to obtain a normal order input–output without the requirement of a post-processing stage. It facilitates reduction in the computational workload on the hardware resources which is confirmed through mathematical derivations. Further, the proposed design involves a novel quadrant multiplier with relatively lower hardware complexity. It performs the quarter operation of a complex multiplier in one clock cycle, and thereby consumes relatively lower power. Moreover, in the last stage, a merged unit for butterfly computation and data re-ordering is also proposed which performs either a half-butterfly operation or interchanges data, and thereby reduces the hardware usage. Application specific integrated circuit synthesis and field programmable gate array results show that for a 1024-points FFT computation, the proposed architecture offers 10.26% savings in area, 20.83% savings in power, 16.98% savings in area-delay product and 26.76% savings in energy-per-sample, 7.79% savings in sliced look-up tables, and 11.93% savings in flip-flops over the best existing design.

A 5.8 GHz digitally configurable DSRC RF-SoC transmitter for China ETC systems

This paper presents a CMOS DSRC transmitter architecture for China electronic toll collection systems. A digitally configurable transmitter architecture is proposed to reduce chip area, power, cost, and design complexity. This transmitter consists of only two digitally configurable analog blocks: an ASK modulator and a power amplifier, other than the digital baseband. The use of digital configuration extends output dynamic range, and facilitates rapid prototyping in different process technologies. The RF-SoC is fabricated using a 0.13 μm CMOS technology. Chip measurement results show that the maximum output power from a single-end port is 7.23 dBm, the occupied bandwidth is 2 MHz, the adjacent channel power ratio is −38 dBc at a 10 MHz offset, the adjustment range of modulation index is 77%–95%, and the transmitter dissipates 36 mA in active mode under a 2 V supply. Compared with state-of-the-art designs in the literature, this design demonstrates remarkable advantages in design complexity, modulation index, chip area, power consumption, output dynamic range, and output peak power. The chip area savings is at least 60%, the power consumption is reduced by at least 10%, the output dynamic range is enhanced by 9%, and the single-end output peak power is improved by at least 45%.

Energy-Efficient Hadamard-Based SATD Hardware Architectures Through Calculation Reuse

The Hadamard-based Sum of Absolute Transformed Differences (SATD) is a distortion metric that correlates better with other video encoding steps than the commonly used Sum of Absolute Differences (SAD) and thus potentially improves coding efficiency. However, due to the Hadamard Transform (HT), it demands a large share of total encoding time. Meanwhile, the widespread use of embedded encoders made computational complexity and energy efficiency two relevant issues, besides the usual trade-off between the rate and distortion. Hence, the adoption of SATD during video coding requires the design of energy-efficient hardware accelerators. In this paper, we show that the SATD improves coding efficiency by up to −2.99% in BD-Rate when used in motion estimation within the HEVC Model (HM). Subsequently, as the main contribution, we combined two properties featured by the SATD to devise a novel hardware architecture based on calculation reuse. These properties allow for rearranging the architecture components to reduce the hardware size, save operations, and thus, reduce energy. The synthesis and simulation results indicate that the proposed architecture can lead to area and energy savings of about 28% and 32%, respectively, compared to the state-of-the-art architecture based on reuse solely.

Design trade-offs for emerging HPC processors based on mobile market technology

High-performance computing (HPC) is at the crossroads of a potential transition toward mobile market processor technology. Unlike in prior transitions, numerous hardware vendors and integrators will have access to state-of-the-art processor designs due to Arm’s licensing business model. This fact gives them greater flexibility to implement custom HPC-specific designs. In this paper, we undertake a study to quantify the different energy-performance trade-offs when architecting a processor based on mobile market technology. Through detailed simulations over a representative set of benchmarks, our results show that: (i) a modest amount of last-level cache per core is sufficient, leading to significant power and area savings; (ii) in-order cores offer favorable trade-offs when compared to out-of-order cores for a wide range of benchmarks; and (iii) heterogeneous configurations help to improve processor performance and energy efficiency.

Monolithic Integration of GaN Nanowire Light-Emitting Diode With Field Effect Transistor

Gallium nitride (GaN)-based light-emitting diodes (LEDs) are being investigated for the next generation display technology. The persistent issue, however, has been the lack of ability to integrate transistors with LEDs for control. Here, a novel vertical integration scheme is utilized to fabricate nanowire LEDs with nanowire field effect transistors (FETs) for the first time. This approach utilizes the unintentionally doped GaN template layer which is common to LED growth for the fabrication of nanowire FETs. The demonstrated voltage-controlled light-emitting unit provides area savings, scaling, and easier fabrication due to the vertical integration. For these initial nanowire devices, light modulation is demonstrated with LED turn OFF at −10 V. Due to the nanowire approach, these devices show over two times improvement in the $I_{ \mathrm{\scriptscriptstyle ON}}$ to $I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio compared with the alternative integration schemes.

Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience

Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively.

Reduced ordered binary decision diagram-based combinational circuit synthesis for optimising area, power and temperature

In this paper, an attempt is made to reduce the rise in circuit temperature by optimising power-density during logic synthesis level. Reduced ordered binary decision diagram (ROBDD) being canonical in nature makes a suitable choice of logic realisation in this work. ROBDD is used here not only to reduce area (node) but also the possibility of reducing power and temperature (power-density) is explored. In this work, a genetic algorithm based approach is presented to determine a suitable variable ordering during the formation of the ROBDD for its thermal-aware realisation considering other parameters like area and power without performance degradation. The proposed approach shows more than 33% savings in area and power, and 5.61% savings in power-density with respect to initial ROBDD representation of LGSynth93 benchmark circuits. Actual on-chip area, power dissipation and the absolute value of temperature are calculated using CADENCE and HotSpot tool to validate the power-density based results.

An Approximate Bufferless Network-on-Chip

Bufferless network-on-chip (NoC) designs have drawn research attention in massively parallel multicore systems via their significant benefits in power and area savings. However, it shows poor throughput and low bandwidth in current bufferless designs due to complex bufferless routing and arbitration. Especially in the NACK-based bufferless network, the network performance will be affected significantly as the network conflicts increased caused by packet retransmissions. To this end, we proposed a novel approximate bufferless network, ABNoC. ABNoC lessens network conflicts and packet retransmissions via an approximate allocation mechanism (AAM) and a packet approximation method. We show that, compared with SCARAB, ABNoC improved the bandwidth up to 1.92 times and achieved 1.2 times faster in runtime. Besides, ABNoC accomplished 83.6% retransmission reduction and 46.7% latency reduction, while maintaining low application error.

Area- and Power-Efficient Nearly-Linear Phase Response IIR Filter by Iterative Convex Optimization

Low complexity infinite impulse response (IIR) filter design with nearly-linear phase response has attracted considerable attention in recent years due to the substantially high area and power consumption of linear phase finite impulse response (FIR) filter. Compared with the FIR filter, designing an IIR filter with the minimized group delay deviation and low power cost is a challenging topic. In this paper, the non-convex group delay deviation minimization problem for IIR filter design is reformulated into an iterative optimization problem to achieve lower group delay deviation. The hardware complexity of the solution is iteratively reduced by approximating the IIR filter coefficients to maximize the number of eliminable common subexpressions. The headroom for the coefficient adjustment is governed by the gradient of group delay deviation between iterations. Using our proposed design algorithm, a high-order lowpass filter with a minimum stopband attenuation of 60dB can be implemented by a 13-tap IIR filter with a group delay deviation of 0.002 only, as opposed to two linear-phase FIR filters designed by two recent and competitive FIR filter design algorithms with tap number of 51 and 57, respectively. Logic synthesis shows that the proposed IIR design saves 39.4% of the area and 41.8% of power consumption over the FIR solutions. Comparing with the latest nearly-linear phase IIR filter design algorithms, the group delay deviation of the solutions generated by our proposed algorithm are on average 25.5% lower, along with an average area and power savings of 20.5% and 18.4%, respectively, from the logic synthesis results.

Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors

Approximate computing has been exploited for many years in application-specific architectures. Recently, it has also been proposed for low-power programmable processors. However, this poses some challenges as, in a microprocessor, the energy consumed by fetching and decoding an instruction may be significantly higher than that of the execution itself. Therefore, approximate computing would be advisable only for those instructions, in which the execution stage is significantly expensive in terms of energy consumption. In this paper, we present new architectures for truncated SIMD multipliers able to calculate signed and unsigned products from $8\times {}8$ to $64\times {}64$ bits. Next, we analyze the precision loss incurred by truncation for all product sizes. We implement accurate and truncated architectures for both scalar and SIMD products and find that truncation allows area savings of up to 27%. The proposed design is experimentally evaluated in different scenarios, showing potential energy savings ranging from 29% to 42%. Finally, this paper analyzes the overall convenience of introducing truncated SIMD architectures with respect to accurate SIMD and scalar architectures.

Design and Implementation of Reference-Free Drift-Cancelling CMOS Magnetic Sensors for Biosensing Applications

Magnetic imagers, which utilize magnetic nanoparticles as labels to realize biodetection assays, hold significant promise for deployment at the point-of-use. Resonance-shift-based sensors can be realized in standard CMOS processes without post-process modifications and offer great sensitivity at low price tags. Unfortunately, CMOS resonant-shift magnetic sensors suffer significant degradation in SNR and long-term stability due to low on-chip inductor quality factors and significant noise introduced from active devices and thermal variations. This makes standard resonant-shift-based imagers undesirable for use in low-signal biodetection assays. Furthermore, and most importantly, the significant long-term drift due to slow-varying noise sources and temperature changes makes these sensors inadequate for bioexperiments which may take timescales on the order of hours to reach completion. In this paper, we propose a transformer-based approach which enables sub-parts-per-million (PPM) signal detection without the need for any thermal compensation. The approach is self-referencing, leading to significant savings in chip area by removing the need for replica reference cells. We analyze the performance of the transformer-based circuit compared to the original second-order system and demonstrate its superiority for rejecting system noise. A proof-of-concept design of a fully integrated $2 \times 2$ CMOS transformer-based magnetic sensor array is presented which achieves reference-free, sub-PPM detection of magnetic signals. The system can be powered and operated completely from a laptop USB interface and each sensing cell can consume less than 3 mW of DC power. Finally, we show the results of an initial DNA biodetection experiment which confirms the capability of the sensor to be used for realistic bioassays.

Mm‐wave power control

mm‐wave power control

An Element-Matched Electromechanical <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma$ </tex-math> </inline-formula> ADC for Ultrasound Imaging

This paper presents a power- and area-efficient approach to digitizing the echo signals received by piezoelectric transducer elements, commonly used for ultrasound imaging. This technique utilizes such elements not only as sensors but also as the loop filter of an element-level $\Delta \Sigma $ analog to digital converter (ADC). The receiver chain is thus greatly simplified, yielding savings in area and power. Every ADC becomes small enough to fit underneath a $150\,\,\mu \mathrm {m} \times 150\,\,\mu \mathrm {m}$ transducer element, enabling simultaneous acquisition and digitization from all the elements in a 2-D array. This is especially valuable for miniature 3-D probes. Experimental results are reported for a prototype receiver chip with an array of $5 \times 4$ element-matched ADCs and a transducer array fabricated on top of the chip. Each ADC consumes 800 $\mu \mathrm {W}$ from a 1.8 V supply and achieves a SNR of 47 dB in a 75% bandwidth around a center frequency of 5 MHz.

Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding

Globalization of microchip fabrication opens the possibility for an attacker to insert hardware Trojans into a chip during the manufacturing process. While most defensive methods focus on detection or prevention, a recent method, called Randomized Encoding of Combinational Logic for Resistance to Data Leakage (RECORD), uses data randomization to prevent hardware Trojans from leaking meaningful information even when the entire design is known to the attacker. Both RECORD and its sequential variant require significant area and power overhead. In this paper, a Time-Division Multiplexed version of the RECORD design process is proposed which reduces area overhead by 63% and power by 56%. This time-division multiplexing (TDM) concept is further refined to allow commercial off the shelf (COTS) products and IP cores to be safely operated from a separate chip. These new methods tradeoff latency ( $5.3\times $ for TDM and $3.9\times $ for COTS) and energy use to accomplish area and power savings and achieve greater security than the original RECORD process.

The Impact of Pavement Albedo on Radiative Forcing and Building Energy Demand: Comparative Analysis of Urban Neighborhoods

Albedo is the measure of the ratio of solar radiation reflected by the Earth’s surface. High-albedo reflective surfaces absorb less energy and reflect more shortwave radiation. The change in radiative energy balance at the top-of-atmosphere (TOA), which is called radiative forcing (RF), reduces nearby air temperatures and influences the surrounding building energy demand (BED). The impact of reflective surfaces on RF and BED has been investigated separately by researchers through modeling and observational studies, however, no one has compared RF and BED impacts under the same context and the net effect of these two phenomena remains unclear. This paper presents a comprehensive approach to assess the net impacts of pavement albedo modification strategies in selected urban neighborhoods. We apply an adapted analytical model for RF and a hybrid model framework combining two different models for BED to estimate the impacts of increasing pavement albedo from 0.1 to 0.3 for different urban neighborhoods in Boston and Phoenix. The impact of several context-specific factors, including location, urban morphology, shadings etc., are taken into account in the models. Comparative analysis reveals that the net impact of changing pavement albedo can vary from one neighborhood to another. In Phoenix downtown, reflective pavements create net global warming potential burdens, while increasing pavement albedo results in potential savings in the Boston downtown area. This work provides insights into pavement albedo impacts at urban scale and supports more informed decisions on pavement designs that save energy and counteract some of the effects of global warming.