Design and Implementation of 32-Bit High Valency Jackson Adders

Abstract

Parallel prefix addition offers a highly efficient solution to most of the applications which requires fast addition of two binary numbers. An efficient adder design demands proper selection of recurrence equations and its realization. There are different recursion equations like Weinberger recursion, Ling recursion, Jackson recursion, to name a few, available to suit a variety of design requirements. In this work, we have proposed adders based on Jackson recursion. In these adders, the complexity found in generate term is reduced at all the levels of the carry graph to optimize the adder performance parameters. The proposed adder structures are implemented for a word size of 32-bit based on the Jackson recursion equations for valency-4 and valency-5. The synthesis results reveal that the high-valency Jackson adder structures are superior in terms of power and area over the Ling adders for comparable delay values. Experimental results obtained reveals that an average of [Formula: see text] and [Formula: see text] savings in area and power, respectively, are achieved by the proposed adders, as compared to Ling adders for the same word size. Furthermore, the proposed adders demonstrate enhanced area-delay and the power-delay values compared to the adders based on the Weinberger’s recursion.