Saturated Output Power Research Articles

A D-Band Power Amplifier in 65-nm CMOS by Adopting Simultaneous Output Power-and Gain-Matched Gmax-Core

This paper proposes a simultaneous output power- and gain-matching technique in a sub-THz power amplifier (PA) design based on a maximum achievable gain ( G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) core. The optimum combination of three-passive-elements-based embedding networks for implementing the G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> -core is chosen considering the small- and large-signal performances at the same time. By adopting the proposed technique, the simultaneous output power- and gain-matching can be achieved, maximizing the small-signal power gain and large-signal output power simultaneously. A 150 GHz single-ended two-stage PA without power combining circuit is implemented in a 65-nm CMOS process based on the proposed technique. The amplifier achieves a peak power gain of 17.5 dB, peak power added efficiency (PAE) of 13.3 and 16.1 %, saturated output power ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) of 10.3 and 9.4 dBm, and DC power consumption of 86.3 and 52.4 mW, respectively, under the bias voltage of 1.2 and 1 V, which corresponds to the highest PAE, gain per stage and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> per single transistor among other reported CMOS D-band PAs.

Monolithic Integrated Semiconductor Optical Amplifier With Broad Spectrum, High Power, and Small Linewidth Expansion

Semiconductor optical amplifiers (SOAs) offer direct electrical injection, power consumption, integration, and anti-radiation advantages over optical fiber amplifiers. However, saturation output power and gain bandwidth have been limited in traditional structure SOAs. We demonstrate a monolithic integrated SOA with broad spectrum, high power, high gain, and small spectral linewidth expansion. The device adopts a two-stage amplified large optical cavity structure, and a lower optical field confinement factor is obtained by adjusting the thickness of the waveguide layer. The lower optical field confinement factor is conducive to improving the coupling efficiency and the maximum output power. Our device, fabricated only by standard i-line lithography with micron-scale precision, obtains excellent and stable performance. When the input power is set to 1 mW, the output power is 419 mW with a gain of 26.23 dB. When the input power is set to 25 mW at 25 °C, the output power increases to 600 mW with a gain of 13.8 dB. The corresponding gain bandwidth of 3 dB measures at least 70 nm. The spectral linewidth after the SOA is 1.15 times wider than that of the seed laser.

A Broadband Doherty Power Amplifier With a New Load Modulation Network

In this paper, we proposed a new load modulation method to improve bandwidth and efficiency at output power back-off (OBO) of the Doherty Power Amplifier (DPA). The quarter wavelength transmission line behind the combination point of the impedance inverter was replaced with a dual-frequency matching circuit to matche the impedance value of the combination point to the load impedance in this method. The dual-frequency matching was used to compensate for the frequency dispersion effect that occurs in the traditional impedance inverter network and to a certain extent solves the bandwidth limitation of the Doherty power amplifier. To verify the proposed theory, a broadband high-efficiency power amplifier was designed and manufactured for 5G mobile communications. Measurement results show that the designed DPA is in the range of 2.4-3.7GHz, the saturated output power is above 42dBm, the saturated drain efficiency is 61.2%-68.4%, and the 6dB back-off efficiency is 49.7%-61.4%.

A Highly Efficient and Linear mm-Wave CMOS Power Amplifier Using a Compact Symmetrical Parallel–Parallel Power Combiner With IMD3 Cancellation for 5G Applications

This paper presents a fully integrated linear power amplifier (PA) in a 65-nm CMOS process for mm-wave 5G applications. The proposed linear PA employs a compact symmetrical 4-way parallel–parallel power combiner with a third-order intermodulation distortion (IMD3) cancellation method to achieve high linear output power with a high power-added efficiency (PAE). An on-chip 4-way parallel–parallel power combiner, which combines the output power from 8-unit PAs, is designed with a compact footprint ( $241\,\,\mu \text{m}\,\,\times 241\,\,\mu \text{m}$ ). Conventional series power-combining transformer based power combiners have poor symmetrical performance for the amplitude and phase of the input impedance among unit PAs owing to the parasitic effects of the power combiners. However, the proposed parallel–parallel power combiner, which is based on parallel power-combining transformer structures, shows good symmetrical performances among unit PAs. Moreover, an IMD3 cancellation method using a parallel–parallel power combiner is proposed in this work. The proposed IMD3 cancellation method can support high-order modulation signals without increasing the complexity and reduce the dependence for digital predistortion (DPD). Consequently, the proposed linearization method obtains a high linear POUT and PAE without DPD. The PA in 65-nm CMOS demonstrates a saturated output power (PSAT) of 23.2 dBm, a 15.9-dB power gain, a 1-dB compressed output power ( $\text{P}_{\mathrm {O,1dB}}$ ) of 22 dBm, and a peak power-added efficiency (PAE) of 33.5% at 28 GHz. The measured error vector magnitude with 100 Msym/s of 256/512-QAM is −31.2/−32.1 dB with average output power of 18.02/17.73 dBm, average PAE of 17.6/16.1%, and adjacent channel power ratio (ACPR) of −30/−33.1 dBc without DPD. To the best of the authors’ knowledge, the proposed PA demonstrates high output power with the highest PAE performance supporting 256/512-QAM compared to the recently published fully integrated mm-wave 5G CMOS PAs.

Research on ultra-wideband and high saturation power uni-traveling carrier photodetectors (Invited)

Ultra-wideband uni-traveling carrier (UTC) photodetectors have broadband advantages over traditional PIN detectors, as only fast electrons are required to transport in UTC photodetectors. They will be one of the key optoelectronic devices in the sub-terahertz systems, such as 6G broadband wireless communications, terahertz imaging, ultra-wideband noise generators, etc. For the requirements of optoelectronic conversion in sub-terahertz frequency band, high-speed photo-generated carrier transport mechanics and inductive coplanar waveguide (CPW) structure were studied to improve the device bandwidth and saturation power of the photodetector. A dual-drift layer structure MUTC photodetector chip with bandwidth of 106 GHz, saturated output power of 7.3 dBm, and a CPW-optimized MUTC photodetector chip with bandwidth over 150 GHz were developed.

Highly Efficient HBT Power Amplifier Using High-Q Single- and Two-Winding Transformer With IMD3 Cancellation

This paper presents a highly efficient InGaP/GaAs HBT power amplifier (PA) implemented using a proposed high- Q single- and two-winding transformer. A single- and two-winding transformer is designed with a printed circuit board (PCB) to combine the output power with a reduced passive loss. Compared to a typical 1:2 two-winding transformer, an additional unit amplifier is connected at the mid-point of the secondary winding to construct a single-winding transformer without additional windings. An IMD3 cancellation technique using a single- and two-winding transformer is also proposed to obtain a high linear output power with high power-added efficiency (PAE) without additional design circuitry. The IMD3 components of the two input currents in the single- and two-winding transformer are 180° out-of-phase cancelling each other at output. The proposed PA is integrated with an InGaP/GaAs HBT process using a PCB transformer. The experimental results demonstrate that the PA achieves a saturated output power of 33.3 dBm, with a PAE of 61.3% at 0.91 GHz. The proposed PA is also tested with an orthogonal frequency-division multiplexing (OFDM) 64-quadrature amplitude modulation (QAM) signal having a bandwidth of 10 MHz and peak-to-average power ratio (PAPR) of 7.8 dB at 0.91 GHz to evaluate the improvement in linearity. The PA achieves an adjacent channel leakage ratio (ACLR) of -42 dBc up to an output power of 26.0 dBm with a PAE of 26.8% and current consumption of 297 mA.

A 25.1 dBm 25.9-dB Gain 25.4% PAE X-band Power Amplifier Utilizing Voltage Combining Transformer in 65-nm CMOS

We present an X-band two-stage power amplifier (PA) in 65-nm CMOS process using a transformer (TF)-based voltage combining technique (VTC) which achieves the highest figure of merit (FOM) among recently reported CMOS PAs. The PA architecture is constructed with two-stage push-pull amplifiers with a three-way voltage power combiner and splitter which play the main role to achieve outstanding performance. The power combining was applied in the voltage domain to increase the output device size aiming at boosting the output power of the CMOS PA. We constructed a compact two-stage PA with a push-pull structure with conjugate matchings at the input, inter-stage, and output with the capacitive neutralization technique to improve the power gain and drain efficiency. Working under a 1.2-V supply with DC quiescent current of 865-mA, the proposed PA achieved a maximum saturated output power of 25.1 dBm with a 1-dB power bandwidth of 3-GHz from 8.4-GHz to 11.4-GHz, a peak power added efficiency (PAE) of 25.4% at 10.2 GHz, a power gain of 25.9-dB at 9.5-GHz with a 3-dB gain bandwidth of 2-GHz (8.7-10.7 GHz). The total chip size is 0.9 mm2, and the core size excluding pads is only 0.342 mm2.

Design of 35-dB 0.03-to-2.7 GHz Two-Stage Broadband Power Amplifier With 37.2 dBm Psat Using Modular Technology

This paper presents a modular technology for two-stage broadband power amplifier (PA) design. The proposed method focuses on separately realizing two stage’s flat gain characteristics, thus providing the entire circuit’s required flatness over broad bandwidth. The power stage employs stacked structure to provide enough power and confine the output impedance around $50~\Omega $ , while the driver stage’s periphery is selected to achieve impedance transformation demanded by modularization. The elaborate requirements for input and inter-stage matching networks (MNs) are repeatable which can be synthesized by real frequency technique (RFT), shortening the design time of broadband MNs. The modular approach can also be transferred to the implementation of other broadband PAs. This novel technology was verified using $0.25~\mu \text{m}$ GaAs PHEMT process. The fabricated two-stage broadband PA obtains a small-signal gain higher than 35.0 dB and saturated output power of 37.2± 1.6 dBm from 30 MHz to 2.7 GHz, with a peak power added efficiency (PAE) of 46.2% at 500 MHz. To our knowledge, this is the highest gain and output power in GaAs broadband amplifier below 2.7 GHz.

A Broadband Power Amplifier in 130-nm SiGe BiCMOS Technology

This letter describes an ultrabroadband power amplifier (PA) in a 130-nm SiGe:C BiCMOS technology. To achieve this broadband while keeping a compact chip size, an on-chip transformer-based dual-LC-tank power matching method is proposed and implemented for achieving this 54.8% fractional large-signal 3-dB bandwidth (28.5-50 GHz). Additionally, a high quality factor (Q) bypass MOM capacitor is proposed and implemented in the transistor layout to decrease the parasitic inductance influence for increasing the gain and keep unconditional stability of the PA. The complete PA achieves a measured saturated output power of 19.2 dBm with 21.5-GHz (28.5-50 GHz) large-signal -3-dB bandwidth at 3.3-V power supply. This broadband PA is only 0.63 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the measured S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> is higher than 22.5 dB from 18.5 to 50 GHz with recorded 70.3% fractional small-signal 3-dB bandwidth for silicon-based cascode PA. The measured peak OP1dB is 16.8 dBm at 44 GHz, and the maximum power-added efficiency (PAE) is 23.9% at 32 GHz.

A 65nm CMOS 60 GHz Class F-E Power Amplifier for WPAN Applications

This work presents a two-stage 60 GHz Power Amplifier designed in a 65nm CMOS technology dedicated to low cost Wireless Personal Area Network (WPAN) applications. In order to provide a high efficiency operation, the PA is based on a Class E power stage. A Class F driver stage is also designed to provide a square waveform signal to the Class-E power stage. To realize the output networks of both driver and power stage at 60 GHz, distributed elements are used instead of lumped elements. The post-layout simulation results show a saturated output power of 15 dBm with a peak PAE of 26% at 60 GHz. It achieves a gain of 15dB at 60 GHz.

A 60 GHz 8-Way Combined Power Amplifier in 0.18 μm SiGe BiCMOS

A 60 GHz fully-integrated 8-way combined power amplifier (PA) is developed in a standard 0.18 μm SiGe BiCMOS technology. The 8-way power splitter and combiner are co-optimized with transformer based baluns inside the eight differential PA cells, and hence resulting in minimum loss and high gain, linearity and efficiency. The measurement shows that the PA can achieve a gain of 22.2 dB around 60 GHz and 3-dB bandwidth from 53.5 GHz to 66.5 GHz, which covers all the channels specified in IEEE 802.11ad standard. It also attains a 1-dB power compression point (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ) of 21.8 dBm and saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> ) of 22.6 dBm, with power-added-efficiency of 10.7% and 12%, respectively.

A MM-Wave Current-Mode Inverse Outphasing Transmitter Front-End: A Circuit Duality of Conventional Voltage-Mode Outphasing

This article presents a millimeter-wave (mm-wave) transmitter (TX) front-end employing a new inverse outphasing architecture with current-mode power amplifiers (PAs). This study on the conventional outphasing operation reveals its strong dependence on its voltage-mode driving source assumption and thus exhibits major limitations at mm-wave, since efficient and linear mm-wave PAs often behave as current sources. To address this challenge, we propose a current-mode inverse outphasing architecture that employs current-mode driving sources and is inherently compatible with mm-wave linear PAs. Moreover, the conventional series outphasing combiner is replaced by a much simpler and low-loss parallel power combining scheme. Closed-form mathematical expressions are derived for both the outphasing and inverse outphasing operations, including the active load modulation, Chireix compensations, and outphasing efficiency, which fundamentally explains the limitations of the conventional approach and the advantages of the inverse outphasing architecture. Further theoretical analysis discovers a circuit duality relationship between outphasing and inverse outphasing architectures, which offers unique circuit intuitions. As a proof-of-concept, we implement a 28-GHz TX front-end using cascode PAs, based on the inverse outphasing architecture. In the measurement, the TX achieves 22.7-dBm saturated output power with 42.6% PA drain efficiency. The TX exhibits effective PA efficiency enhancement at 6-dB power back-off (PBO), validating the high-efficiency inverse outphasing active load modulation. Modulation tests with high-order quadrature amplitude modulation (QAM) signals demonstrate that the TX supports >10-Gb/s high-fidelity complex signals and achieves the state-of-the-art modulation performance.

Design of a Ka-Band Cascode Power Amplifier Linearized With Cold-FET Interstage Matching Network

A Ka-band CMOS cascode power amplifier (PA) linearized with a cold-FET-based interstage matching network is presented, which is designed in a 65-nm CMOS process. Since it is difficult to make a cascode PA matched to the optimum output and input impedances at high frequencies, a matching network has to be introduced at the node between the common-source (CS) and common-gate (CG) stages. The cold-FET-based matching network improves the linearity and the input and output impedance matchings, which is analyzed and optimized with its simple model. It makes the PA have gain expansion and phase lag with the power, which allows the PA to have less amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortions. In addition, it improves the return losses of the PA by making the impedances for power matching and conjugate matching located closely. The implemented PA achieves the peak power-added efficiency (PAE) of 38.2% and the saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) of 17.1 dBm at 31 GHz while occupying the chip area of 0.16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It is also shown that the OP1 dB is improved by 1.7 dB, and the AM-PM distortion is reduced to only 1.1° due to the linearization technique. It is tested with 64-quadrature amplitude modulation (QAM) signals, which has a 400-MHz channel bandwidth (BW) and a 9.7-dB peak-to-average power ratio (PAPR). It achieves average output powers of 9.6/7.7 dBm with error vector magnitudes (EVMs) of -25/-30 dB for 64-QAM OFDM signals, efficiencies of 17.7%/12%, and the adjacent channel leakage ratio (ACLR) of -28.2/-32.8 dBc, respectively.

A Broadband Transformer-Based Power Amplifier Achieving 24.5-dBm Output Power Over 24–41 GHz in 65-nm CMOS Process

A fully integrated one-stage cascode wideband power amplifier (PA) in 65-nm CMOS technology is presented in this letter. A matching technique is leveraged to achieve broadband matching network, which provides optimum load impedance for maximum output power within a wide operating frequency range. The proposed PA shows measured results of 24.5-dBm saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) covering the full Ka-band (26.5-40 GHz) and 38.2% output 1-dB compression point (OP1dB) fractional bandwidth (BW) from 25 to 37 GHz. To the best of the authors' knowledge, the proposed PA demonstrates superior output power BW performance compared with the reported state-of-the-art Ka-band CMOS PAs.

A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology

For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added efficiency (PAE). In the proposed design, a 40-nm standard CMOS process is used for higher integration with other RF building blocks, compared with other CMOS PA designs with larger process node. Transistor cells are designed with neutralization capacitors to increase stability and gain performance of the PA. As a trade-off among gain, output power, and PAE, the transistor cells in driving stage and power stage are biased for class A and class AB operation, respectively. Both transistor cells consist of two transistors working in differential mode. Furthermore, transformer-based matching networks (TMNs) are used to realize a two-stage X-band CMOS PA with compact size. The PA achieves an effective conductivity (EC) of 117.5, which is among the highest in recently reported X-band PAs in CMOS technology. The PA also attains a saturated output power (Psat) of 20.7 dBm, a peak PAE of 22.4%, and a gain of 25.6 dB at the center frequency of 10 GHz under a 1 V supply in 40-nm CMOS.

A 52–58 GHz Power Amplifier With 18.6-dBm Saturated Output Power for Space Applications

This brief presents a 52–58 GHz power amplifier (PA) with constant output power across the entire band. A new topology based on the impedance transformation of transmission lines was adopted as the inter-stage matching network. Compared with the conventional 2-section LC matching topology, our approach reduced the matching loss by 1.5 dB at 54 GHz. Such topology made the design capable of operating at a frequency close to 80% of the unit-current-gain cut-off frequency ( $f_{T}$ ) specified by the device technology. Additionally, stacked-FET was adopted as the power stage for the output power enhancement in a broadband sense. Implemented in the commercially available 0.15- $\boldsymbol{\mu }\text{m}$ GaAs pseudomorphic high-electron-mobility transistor (pHEMT) process, the 2-stage PA demonstrated a small-signal gain of 14.7 dB, a saturated output power ( $P_{sat}$ ) of 18.6 dBm, and a maximum power-added-efficiency (PAE) of 18.2% at 54 GHz.

Output power saturation effect in Yb – Er fibre lasers

The output power saturation effect in Yb – Er fibre lasers is experimentally observed. A formula for estimating the saturation power is derived. A method is proposed for measuring the 4I11/2 level lifetime or the concentration of Er ions based on the measurements of the saturation power.

A 28 GHz GaAs front‐end IC with single positive supply voltage

AbstractThis paper presents 28 GHz GaAs front‐end IC for 5G beamforming systems with single positive supply voltage. A 28 GHz front‐end IC consists of a 3‐stage power amplifier, a 3‐stage low noise amplifier and two reflective type single pole double throw switches in 0.15 μm enhancement‐mode (E‐mode) GaAs pHEMT technology. The proposed 28 GHz front‐end IC is controlled only with single positive supply voltage. The measured front‐end IC Tx mode gain and Rx mode gain are 16.3 dB and 16.8 dB at 28 GHz, respectively. The achieved output P1dB and saturation power (PSAT) in Tx mode are 18 dBm and 21 dBm, respectively. The achieved input P1dB and noise figure in Rx mode are −8 dBm and 3 dB, respectively. The 28 GHz GaAs front‐end IC consumes DC current of 216 mA in Tx mode at 4 V supply voltage and 20 mA in Rx mode at 2.5 V supply voltage. The proposed 28 GHz front‐end IC chip size is 2.5 x 2.2 mm2.

A Broadband 110–170-GHz Stagger-Tuned Power Amplifier With 13.5-dBm P sat in 130-nm SiGe

This letter presents a fully integrated three-stage single-ended D-band power amplifier (PA) designed in 0.13-μm silicon-germanium (SiGe) BiCMOS technology. Several bandwidth extension techniques and matching networks are mutually exploited to maximize Bandwidth (BW) performance while assuring unconditional stability. Its measured 3-dB bandwidth covers the entire D-band (110-170 GHz). The PA has a small-signal peak gain of 21 dB at 151 GHz. Its saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) in the D-band varies from 11.8 to 13.9 dBm and its output referred 1-dB compression point (OP1 dB) from 9.2 to 12.5 dBm within the D-band. The presented amplifier occupies 0.65 × 0.47 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (including pads) and draws a current of 115 mA from a 3.3-V supply. To the best of our knowledge, these performances represent the state of the art in silicon technology with a minimum (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) of 11.8 dBm and (OP1 dB) of 9.2 dBm covering the entire D-band.

A Highly Linear and Efficient 28-GHz PA With a P sat of 23.2 dBm, P 1 dB of 22.7 dBm, and PAE of 35.5% in 65-nm Bulk CMOS

This article presents a 28-GHz power amplifier (PA) suitable for fifth-generation (5G) wireless systems. Designed in a 65-nm bulk CMOS, the PA achieves a saturated output power ( $P_{\text {sat}}$ ) of 23.2 dBm at 28 GHz. The AM–AM and the AM–PM distortion have the overshoot of less than 0.3 dB and 0.2°, respectively, at 28 GHz. The AM–PM variation remains less than 1.9° over the frequency band of 26–31 GHz with a peak power-added efficiency (PAE) of 35.5%. Several techniques, including strategic placement of varactors, a proposed multi-function coplanar-waveguide (CPW)-like power combining structure, and a systematic design approach for the passive networks, are used to improve the efficiency and linearity of the design leading to a negligible difference between $P_{1\,\text {dB}}$ and $P_{\text {sat}}$ . The proposed linearity improvement technique, which uses an adaptive feedback structure to adjust the input impedance of the output stage based on the output power and also direct more current at higher output power levels, enhances the linearity through lowering both AM–AM and AM–PM conversions. The design enables 2.5-GS/s 64-QAM operation at average $P_{\text {out}}$ of 16.1 dBm with an error-vector magnitude/adjacent-channel power ratio (EVM/ACPR) of better than −26.2-dB/−28.32-dBc without using any digital pre-distortion.