ADC Sampling Research Articles

Quantitative analysis of the high speed and high precision waveform digital system for Jinping Neutrino Experiment

The Jinping Neutrino Experiment (JNE) aims to construct a 500-ton liquid scintillator detector for detecting and studying neutrinos. In JNE data analysis, particle energy and position reconstruction are crucial, with result accuracy closely related to the performance of the waveform digitization system. This study developed a quantitative model to explore correlations between sampling characteristics (effective number of bits and sampling rate) and detector system performance (single photoelectron charge spectrum resolution and transfer time spread). Additionally, three ADCs (Tsinghua ADC13B1G, ADI AD9695, TI ADS54J60) and MCP-PMTs were utilized to validate the model accuracy. The experimental results for the system charge spectrum resolution are in alignment with the theoretical predictions. When the ENOB of the ADC exceeds 10.66-bit and the sampling rate exceeds 1 GSPS, the system charge spectrum resolution is better than 45%, approaching the PMT inherent resolution of 44%. The transfer time spread within the system demonstrates minimal impact from the ADC sampling characteristics. These results serve as a reference for upgrading the JNE 60-channel and 4000-channel readout electronic systems. Additionally, this study can assist developers in maximizing the performance of physics experiment readout electronics systems within constrained budgets.

Development and study of ultrasonic pulse velocity measurement system using wave analysis and two-point detection approach

Abstract This article focuses on the development and analysis of an Ultrasonic Pulse Velocity (UPV) measurement system used for the evaluation of concrete and Reinforced Cement Concrete (RCC) in civil construction. The UPV tester is essential for on-site assessments of structures, as it is used to measure the velocity of ultrasonic waves within the material, directly correlating with its strength. UPV testing is affected by the attenuation of ultrasonic waves in concrete, particularly due to the interfacial transition zone. Excess ultrasonic attenuation results in the reduction in the received signal amplitude which may also results in the omission of the initial pulses due to threshold comparison at the receiver. The study highlights the impact of receiver gain on threshold error and discusses the limitations associated with ADC sampling rate and amplitude resolution. UPV measurement, including counter or data acquisition approach, have error contributions associated with threshold voltage comparison. The error due to threshold amplitude selection is quantified, emphasizing the importance of accurate signal analysis, particularly in highly attenuating medium. The article presents the design and development of a PC-based UPV tester with automatic threshold error compensation. The system includes a transmitter, receiver, 32-bit microcontroller, and a Graphical User Interface (GUI) for data analysis. The article introduces a two-point linear detection logic to minimize errors caused by selected signal amplitude and omission of initial pulses in transit time measurements. The proposed method provides effective resolution of 10 ns through software, even at low sampling rate of 2 MS/s. The experimental results demonstrate the effectiveness of the developed UPV tester, with comparisons to a reference calibration facility at CSIR-NPL. The standard deviation in the ultrasonic transit time measurement by the developed UPV device, with threshold error correction, was ±70 ns.

A SoC-FPGA based readout platform for the free-running AMBER data acquisition system

Owing to a change in the scope of physics research, the AMBER spectrometer at CERN is undergoing an update on its instrumentation and trigger strategy for the data acquisition system. One of the key updates is the adoption of a free-running and trigger-less operation, which differs from the predecessor of AMBER, COMPASS, by working in a continuous mode but in an event-based triggered way.In this article, we present a multichannel data-acquisition platform developed in line with the next generation of trigger-less and free-running data acquisition systems. The platform is based on a pre-existing Mezzanine Sampling ADC board for the analog-to-digital conversion and a Xilinx Zynq Ultrascale+ System on Module for online real-time data processing. We also present the evaluation of the system operating in continuous mode, taking data from a 25-element electromagnetic calorimeter prototype with a muon beam, during the first AMBER pilot run. The acquired data were used for noise and pulse shape studies required for the design of the algorithms for lossless compression and data feature extraction needed for trigger-less operation.

WASA: a low power and high integration readout ASIC for TPCs in 65 nm CMOS

The paper presents the development of a low-power and high-integration readout ASIC (WASA) for time projection chambers (TPCs). Each channel of the ASIC consists of the analog front-end, a waveform sampling ADC and digital signal processing circuits. To reduce power consumption, a simple CR-RC shaper and a digital trapezoid filter are adopted to achieve comparable performance to a CR-RC4 shaper with much lower power. Trigger logic and data buffer have also been integrated to reduce the data bandwidth. A 16-channel prototype chip was fabricated in a 65 nm CMOS process and was tested. The test results were consistent with the simulation. At 40 MSPS sampling rate, the power consumption of the chip was only 4.94 mW per channel, including 1.38 mW from the analog front-end, 0.83 mW from the waveform sampling ADC and 2.73 mW from digital logics. The equivalent noise charge of 569 e+14.8 e/pF has been achieved. The measured dynamic range was 120 fC and the integral nonlinearity was less than 0.74%. More design details and test results will be given in this paper.

Doppler Aliasing in OFDM Radar – A Method for Reducing the ADC Sampling Frequency without Losing Range Resolution

Doppler Aliasing in OFDM Radar – A Method for Reducing the ADC Sampling Frequency without Losing Range Resolution

Automatic feedthrough cancellation methods for MEMS gyroscopes

The feedthrough effect can significantly affect the performance of MEMS gyroscopes and even lead to device failure. In order to address the inevitable problem of feedthrough capacitance caused by microfabrication process and circuit structure, two automatic feedthrough cancellation solutions are proposed based on the analysis of the feedthrough effect. Firstly, an equivalent feedthrough model is established for MEMS gyroscopes. Then, through theoretical derivation and model simulation, various influences of feedthrough effect are analysed, and the critical value of feedthrough capacitance is calculated to achieve better compensation effects. For feedthrough capacitance greater than the critical value, a feedthrough cancellation method utilizing AD5231 digital potentiometer for generating an inverse signal is designed. For the situation of feedthrough capacitance less than the critical value, a feedthrough cancellation method based on pure digital circuit calculation is proposed. The experimental results show that the method of utilizing digital potentiometer effectively reduces the feedthrough level from −17.46 dB to −32.75 dB, and the method of utilizing pure digital circuit calculation compensates the feedthrough signal of 100.04 mV to almost zero (2.44 mV) within the range of ADC sampling accuracy. These two methods can accurately and quickly suppress feedthrough signal to improve the detection performance of MEMS gyroscopes, and are expected to meet the needs of future mass production. In addition, they can be widely applied to various MEMS devices that require feedthrough cancellation.

RF-PSF: A CNN-Based Process Distinction Method Using Inadvertent RF Signatures

Stochastic variation of process parameters within a die and technology-limitation-driven variation from die-to-die give rise to unique distribution patterns for manufacturing process parameters. These patterns work as a process signature that is transferred from the device level to the system level through electrical circuits and can be used to make a distinction among the processes. In this work, we propose an in-situ manufacturing process technology distinction method‘, Radio Frequency Process Specific Functions (RF-PSF)’, that uses process-specific inherent properties of an IC manifested in the transmitted radio frequency signal. Among many desirable testing criteria, RF-PSF addresses the question of fabrication with the intended process technology. This information plays an important role in modern zero-trust architecture and IC clone detection, a counterfeiting method where the IC is manufactured using a different process. An RF transmitter with RF-DAC power amplifier for QPSK modulation has been designed and simulated in 14nm, 22nm, and 65nm processes for 5 process corners (TT, FF, FS, SF, and SS) in Cadence. The simulated data have been processed in MATLAB. A Multilayer Perceptron (MLP), trained with the constellation data, provides an average accuracy of ~90% for process distinction. Realizing that (i) a higher order modulation will have even more process information and (ii) we can harness the Convolutional Neural Network’s (CNN) improved capability on pattern recognition, we can feed image-like constellation plots to a CNN to get better and consistent performance. Using the baseband constellations for 64-QAM modulated data as images, we have achieved ~100% accuracy with commonly used, pretrained CNN models (ResNet18, ResNet50, and GoogleNet) through transfer learning. The separation among 5 process corners within a process, termed intra-process variation, is also analyzed. The effect of baseband sampling rate and ADC resolution, two practical limitations in RF systems, have been explored. An extensive study has been performed on the effect of a key design parameter at the RF circuit level i.e. W/L or aspect ratio, leading to design insights, proper CNN selection, and some control parameters. This work establishes RF-PSF as a zero-power, zero-area overhead, in-situ process distinction method.

AGATA phase 2 advancements in front-end electronics

The AGATA collaboration has a long-standing leadership in the development of front-end electronics for high resolution gamma -ray spectroscopy using large volume high purity germanium detectors. For two decades, the AGATA collaboration has been developing state-of-the-art digital electronics processing with high resolution sampling ADC, high-speed signal transfer and fast readout to a high throughput computing (HTC) farm for on-line pulse shape analysis. The collaboration is presently addressing the next challenge of equipping a 4pi array with more than 6000 channels in high resolution mode, generating approximately 10 MHz of total trigger requests, coupled to a large variety of complementary instruments. A next generation of front-end electronics, presently under design, is based on industrial products (System on Module FPGA’s), has higher integration and lower power consumption. In this contribution, the conceptual design of the new electronics is presented. The results of the very first tests of the pre-production electronics are presented as well as future perspectives.

A low computation detection method of signal nonlinear distortion based on digital quadrature detection principle

This paper presents a digital low computation detection method for signal nonlinear distortion. After presetting ADC sampling rate and completing data sampling, the low sampling rate data extracted from the sampling data complete the autocorrelation analysis to correct and calculate the accurate fundamental frequency. According to the relationship between the fundamental frequency and the sampling rate, the complete periodic segment data of the signal cutting out from the sampling data carry out the digital quadrature detection operation to obtain the value of each harmonic component and nonlinear distortion. Experiments show that the calculation of this method is less than that of FFT spectrum analysis method when measuring the THD lower than 15 order. When calculating the 15-order THD at 1024 points, the calculation time is reduced by 44.26%. Moreover, the digital quadrature detection method has high measurement accuracy with less than 0.6% error of detecting 5-order THD.

An RRAM-based building block for reprogrammable non-uniform sampling ADCs

AbstractRRAM devices have recently seen wide-spread adoption into applications such as neural networks and storage elements since their inherent non-volatility and multi-bit-capability renders them a possible candidate for mitigating the von-Neumann bottleneck. Researchers often face difficulties when developing edge devices, since dealing with sensors detecting parameters such as humidity or temperature often requires large and power-consuming ADCs. We propose a possible mitigation, namely using a RRAM device in combination with a comparator circuit to form a basic block for threshold detection. This can be expanded towards programmable non-uniform sampling ADCs, significantly reducing both area and power consumption since significantly smaller bit-resolutions are required. We demonstrate how a comparator circuit designed in 130 nm technology can be reprogrammed by programming the incorporated RRAM device. Our proposed building block consumes 83 µW.

Improving the ranging performance of chaos LiDAR.

Chaos lidar has gained significant attention due to its high spatial resolution, natural anti-interference capability, and confidentiality. However, constrained by the power of the chaos laser, the sensitivity of the linear detector, and the hardware bandwidth, chaos lidar is greatly restricted in the application of long-distance target detection and imaging. To overcome these constraints, we propose a novel, to the best of our knowledge, chaos lidar based on Geiger mode avalanched photodetectors (GM-APDs) in a previous study called chaos single-photon (CSP) lidar. In this paper, we compare the CSP lidar with the linear mode chaos lidars by combining with lidar equation. Regarding the ranging principle, the CSP lidar is fully digital and breaks through the constraints of a detector's bandwidth and ADC's sampling rate. The simulation results indicate that the detection range of the CSP lidar is approximately 35 times and 8 times greater than that of a continuous-wave chaos lidar and pulsed chaos lidar, respectively. Although the detection accuracy of the CSP lidar is only at the centimeter level and is lower than the linear mode chaos lidars, its consumption of storage resources and power is greatly reduced due to 1-bit quantization in the GM-APD. Additionally, we investigate the impact of GM-APD parameters on the signal-to-noise ratio (SNR) of the CSP lidar system and demonstrate that the dead time difference between GM-APDs has a negligible effect. In conclusion, we present and demonstrate a new chaos lidar system with a large detection range, high SNR, low storage resources and power consumption, and on-chip capability.

A Modular Hardware Design of an Intelligent Distributed Feeder Terminal Unit

The development of a new power system is proposing new requirements for the function of the feeder terminal unit (FTU), which is the core equipment of the distribution automation system. At the same time, the improvement of FTU intelligence brings a new solution to the problem of line loss calculation. Aiming at the problems of complex structure and low measurement accuracy of current FTU, a hardware scheme combining ADC sampling chip and high-performance MCU is proposed in this paper to realize the integrated application of energy measurement function. Moreover, it is equipped with a line loss calculation module to achieve high precision line loss calculation when the metering chip cannot meet the precision requirements. At the same time, the modular design effectively improves the operation reliability and function expansion of the terminal.

Быстродействие АЦП в СВЧ радиометре

The configuration of a microwave switched radiometer is considered. The grounds that guide developers in determining the requirements for the ADC sampling rate are analyzed. It is shown that the ADC rate can be significantly reduced if an additional analog integrator is installed at the ADC input. Statistical modeling of such a circuit has been carried out, and the optimal parameters of the integrator have been determined. Calculations and laboratory tests of the microwave radiometer unit have been carried out. It is shown that the introduction of the simplest RC integrator makes it possible to use a low-speed ADC and leads to an insignificant change in the radiometer sensitivity.

Research on Gamma Spectroscopy System While Drilling Based on DSP and FPGA

The traditional gamma energy spectrum measurement system performs filtering, shaping, amplification, baseline recovery, stacking discrimination, peak hold, and low-speed ADC sampling on the pulse signal output by the gamma-ray detector. It generates energy spectrum curves. There are problems such as large dead time and pulse signal accumulation. A high-speed digital processing chip (FPGA) and a high-speed ADC are used to perform full pulse sampling on the amplified ray pulses directly. The high-speed digital processing chip (DSP) directly realizes the pulse signal recognition, which remarkably improves the efficiency of signal acquisition and is very suitable for developing the drill gamma spectroscopy system. Scholars have studied the pulse digital Gaussian shaping algorithm and the trapezoidal shaping algorithm in gamma-spectroscopy while drilling to explore this phenomenon. In this case, a gamma-ray spectrum measurement while drilling system based on DSP and FPGA is designed. It realizes the functions of full-pulse high-speed sampling and energy spectrum curve generation for the narrow pulse signal input to the detector. It also converts the energy spectrum curve. It is transmitted to the host computer through the serial port for energy spectrum analysis.

Improved dynamic performance with discrete sampling in digital ACM controlled DC‐DC boost converter with capacitor ESR inclusion

AbstractA classical symmetrical carrier‐based digital Average Current Mode (ACM) control has two sampling choices, peak point and valley point, to control the average inductor current. If it is employed to regulate the DC‐DC boost converter, there will be a difference in the dynamic performance at peak and valley point sampling instants because of discontinuous output voltage ripple due to Equivalent Series Resistance (ESR) of the output capacitor. Therefore, this paper investigates the effect of sampling instant on the dynamic performance of the PWM DC‐DC boost converter in consideration of capacitor ESR. The small‐signal transfer functions of a boost converter for both sampling positions are prominent to analyze each sampling impact on its dynamics. They are derived by using discrete‐time modeling. Further, the choices of sampling instant are investigated related to the RHP zero elimination, voltage stability, and peak‐to‐peak ripple current of the DC‐DC boost converter. The boost converter has improved stability performance by synchronizing the ADC sampling at starting position (valley point) of the symmetrical carrier signal, as evident by the analytical and hardware results of both sampling techniques working from 25% to 100% load working conditions.

Compressed Sensing EEG Measurement Technique with Normally Distributed Sampling Series

We propose a sampling method that incorporates a normally distributed sampling series for EEG measurements using compressed sensing. We confirmed that the ADC sampling count and amount of wirelessly transmitted data can be reduced by 11% while maintaining a reconstruction accuracy similar to that of the conventional method.

Experimental investigation of the ADC sampling rate effect on the digital gamma spectrometry

Gamma spectrometer is not available in many laboratories because it is very expensive. Analog to digital converter ADC is the basic component of digital gamma spectrometers. The sampling rate of the ADC plays an important role in determining the performance and the cost of the gamma spectrometers. This paper investigates experimentally the ADC's sampling rate effect on the performance of the gamma spectroscopy. The conducted experiment started by sampling a real pre-amplifier output. Then, the acquired samples have been processed at different sampling rates to build the dedicated gamma spectrums. During the processing of the sampled signals, three different digital filters have been tested to distinguish their effect on the energy resolution when the sampling rate is reduced. The results of this experimental investigation will help later in proposing new low-cost and efficient gamma spectrometer prototypes.

Performance Analysis of an MLS-Based Interface for Impulse Response Estimation of Resistive and Capacitive Sensors

This paper presents a performance analysis of a system for electrochemical impedance spectroscopy (EIS). The system, composed by an analog front-end (AFE) and a custom microcontroller (MCU) board, performs the impulse response (IR) measurement of linear and time-invariant (LTI) systems with pseudo-random excitation signals. As a novelty, a specific AFE for the interfacing of two-terminal resistive and capacitive sensors is covered in detail. The paper proposes, for the first time, a mathematical model to predict the impact of the main noise sources in the measured IR. Thanks to the proposed approach, the AFE and the system’s parameters can be properly designed in order to reduce the error, thus, minimizing the energy-per-error figure of merit (FOM) as well. The AFE is realized as discrete-components circuit and it has been included in a custom MCU-based measurement system as an expansion module. The predicted results from the mathematical model, in terms of noise power, SNR, and measurement error are validated through system-level simulation and experimental measurements. The system performs the IR measurement with 1023 points, showing root-mean-square (RMS) measurement errors of 1% and 1.4% for the tested ADC sampling frequencies of 62.5 kHz and 125 kHz, respectively. These lead to excellent FOM values of 128.9 mJ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> % <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 252.6 mJ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> % <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> that outstand the state of the art.

Versatile free-running ADC-based data acquisition system for particle detectors

A high-density and low-power (<300 mW/channel) data acquisition (DAQ) system integrating 2240 readout channels inside a single OpenVPX crate is presented. It is intended to be used in various applications, e.g. gaseous or scintillator-based particle detectors. 14 payload slots, controller and data concentrator communicate via a multi-gigabit backplane. Each payload slot consists of a front module for digital and a rear transition module for analog processing. A pair of modules implements 160 full readout chains including amplification/shaping, sampling, and feature extraction. The sampling rate and ADC resolution are configurable for 100–1000 MS/s and 14–8 bit, respectively. To extract the pulse arrival time we used a proper shaping of signals and a timing algorithm based on a non-linear rise approximation, which strongly reduces the sampling phase error, thus providing a good performance at moderate (100–250 MS/s) sampling rates. This allows raw data acquisition, arrival time extraction, energy calculation, and pile-up reconstruction for all 160 channels to be implemented in a single FPGA. It occupies less than 30% of its processing resources. The system was tested using the proton beam at COSY (Cooler Synchrotron) at Juelich Research Center (Germany). An off-detector DAQ with a 12-m long cabling was investigated. It introduces considerable additional thermal noise and crosstalk affecting the timing performance. For a sampling rate of 150 MS/s, the time resolution was found to be about 270 ps.

Ofine noise calibration of the CAEN V1742 ADCs at the PADME experiment

Abstract This work aims to provide robust methods for ofine calibration of the noise foor for CAEN’s V1742 sampling ADCs, used at the PADME experiment. It has been found that a part of the noise in the fnal signals originates from not fully equalized storage capacitor properties in the DRS4 chip, even after application of the CAEN’s proprietary drs4 calibration. Two approaches to ofine equalization are discussed and fnally two methods are proposed for obtaining the calibration data from random and physics trigger runs.