ADC Sampling Research Articles

A Power and Performance Study of CompactL-Band Total Power Radiometers for UAV Remote Sensing Based in the Processing on ZYNQ and ARM Architectures

This article presents a study on the power consumption and performance analysis of a small, portable, and ultra-low power total power <i>L</i>-band radiometer. The article explores two processing architectures: the ZYNQ 7010 and the ARM A8 embedded microprocessor. The processing algorithm based in C&#x002B;&#x002B; was tested for different clock frequencies, ADC sampling speeds, and sizes of the ADC buffer. To reduce the power consumption and the algorithm execution time, high-level and system-level optimizations, along with fixed-point <i>Q</i>(16,16) data representation, were applied to the main code running on LINUX Debian V8. In the case with the ZYNQ 7010, the optimizations had no notable impact on reducing power or execution time in comparison with the ARM A8, where significant variations were measured, showing a tradeoff between power consumption and algorithm performance that limits the processing capability and the system flight time. The ZYNQ 7010 runs the algorithm faster, but the power consumption is higher than the ARM A8. Using the fixed-point <i>Q</i>(16,16) implementation reduced the power consumption and the execution time in both architectures. Based on these results, we developed a heuristic methodology to minimize power consumption and increase the performance. Energy consumption savings for the radiometer during 20 min of flight was 48&#x0025;. The size of the radiometer was reduced to 30 cm &#x00D7; 30 cm &#x00D7; 10 cm, with a weight of 1.36 kg, (3 lb) allowing the system be carried by small drones. The results were validated measuring salinity at two locations in Western Puerto Rico.

Deterministic Dithering-Based 12-b 8-MS/s SAR ADC in 0.18-μm CMOS

This paper presents a 12-bit binary-weighted SAR ADC calibrated using self-subtractive deterministic dithering to determine the capacitor mismatch. A prototype 12-bit SAR ADC sampling at 8-MHz is realized in UMC 180-nm CMOS process and achieves an ENOB of 11.7-bits while consuming 600 μW of power from 1.8 V supply, thereby achieving a figure-of-merit of 22.5 fJ/conv-s and occupying only 0.13 mm2.

Smoothed Phase-Coded FMCW: Waveform Properties and Transceiver Architecture

Smoothed phase-coded frequency modulated continuous waveform (SPC-FMCW), which is aimed to improve the coexistence of multiple radars operating within the same frequency bandwidth, is studied, and the receiving strategy with a low ADC sampling requirement is investigated. The Gaussian filter is applied to obtain smooth waveform phase transitions, and then quadratic phase lag compensation is performed before waveform transmission to enhance decoding. The proposed waveform is examined in different domains, and its waveform properties are analysed theoretically and demonstrated experimentally. Both simulation and experimental results show that the introduced waveform with the investigated processing steps helps combine all advantages of the FMCW waveform, including hardware simplicity and small operational bandwidth of the receiver, with the advantages of phase coding.

Wind speed sensor data processing based on Kaman Vortex Street principle

Wind speed is one of the important monitoring parameters to ensure mine safety. The commonly used mine wind speed sensor can be divided into ultrasonic type, impeller type and hot wire type according to the design principle. The accuracy of the latter two methods is not high enough because they are susceptible to steam and coal dust in mines. The ultrasonic wind speed sensor has better measuring accuracy. In this paper, ultrasonic wind speed sensor, ultrasonic sending and receiving circuit combined with ADC sampling function of the chip, to obtain the received ultrasonic amplitude change data, statistics of ultrasonic waveform changes caused by blowing, according to the number of changes in the wind speed frequency, and then calculate the real-time wind speed.

Analog self-interference cancellation based on zero-forcing sampling for in band full duplex radios

A uniformly zero-forcing sampling method applied in the base-band analog domain is proposed for Self-Interference Cancellation (SIC) in Band Full-Duplex (IBFD) radios. In order to releasing the ADC dynamic range to enable the desired signal for further processing in the digital domain, the SIC is performed when ADC samples the received signal. Specifically, first, an auxiliary signal is designed to rectify the zero-crossings of the self-interference (SI) to be consistent with the ADC sampling points. Second, to achieve the auxiliary signal, a zero-forcing function is established by leveraging one-to-one mapping from the complex domain to the complex exponential domain. Meanwhile, a closed-form expression of the zero-forcing function is derived according to the Z transformation. Additionally, an orthogonal pilot structure is proposed to improve the SIC capability, and the computational complexity is investigated. Finally, simulation and experimental results show the effectiveness of the proposed method.

The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems

The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.

Development of the Line Protection Measurement and Control Device based on Domestic MCU

In this paper, the dual MCU hardware architecture of protection measurement and control device was presented by analyzing the current situation of domestic MCU and chip selection. The problems existing in ADC sampling accuracy and ADC integral non-linearity were studied. The design scheme of high-precision ADC acquisition system based on dual MCU architecture was proposed, which could meet the requirements of technical specifications by using oversampling and adaptive processing of sampling nonlinear area. In terms of reliability, the EMC performance of the device was promoted by the improvement of outlet and ADC acquisition circuit.

A Novel TRNG Based on Traditional ADC Nonlinear Effect and Chaotic Map for IoT Security and Anticollision

In the rapidly developing Internet of Things (IoT) applications, how to achieve rapid identification of massive devices and secure the communication of wireless data based on low cost and low power consumption is the key problem to be solved urgently. This paper proposes a novel true random number generator (TRNG) based on ADC nonlinear effect and chaotic map, which can be implemented by traditional processors with built-in ADCs, such as MCU, DSP, ARM, and FPGA. The processor controls the ADC to sample the changing input signal to obtain the digital signal DADC and then extracts some bits of DADC to generate the true random number (TRN). At the same time, after a delay based on DADC, the next time ADC sampling is carried out, and the cycle continues until the processor stops generating the TRN. Due to the nonlinear effect of ADC, the DADC obtained from each sampling is stochastic, and the changing input signal will sharply change the delay time, thus changing the sampling interval (called random interval sampling). As the input signal changes, DADC with strong randomness is obtained. The whole operation of the TRNG resembles a chaotic map, and this method also eliminates the pseudorandom property of chaotic map by combining the variable input signal (including noise) with the nonlinear effect of ADC. The simulation and actual test data are verified by NIST, and the verification results show that the random numbers generated by the proposed method have strong randomness and can be used to implement TRNG. The proposed TRNG has the advantages of low cost, low power consumption, and strong compatibility, and the rate of generating true random number is more than 1.6 Mbps (determined by ADC sampling rate and processor frequency), which is very suitable for IoT sensor devices for security encryption algorithms and anticollision.

A Study on Sampling Penalties Reduction of Kramers-Kronig Receivers

Kramers-Kronig (KK) relation-based receiver can recover the field using a single-photodiode. However, the KK receiver requires a high carrier-to-signal power ratio (CSPR), and digital signal processing performed a few times faster than the Nyquist sampling rate. We propose a method to relax the requirements for sampling rate and CSPR by using digital upsampling with harmonic filtering. In the proposed method, log calculation of the KK algorithm is preceded by digital upsampling and followed by harmonics elimination and downsampling, respectively. Our results predict that the combination of digital upsampling and harmonic elimination can comply with the requirement of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> generation FEC limit in 16-QAM 40-km transmission with the following signal parameters, CSPR 6.7 dB, ADC sampling rate 2.5 sps, digital upsampling 3 sps. We propose performing harmonic elimination in combination with Hilbert transform using a single finite impulse response (FIR) filter to increase computation efficiency. Compared with the frequency-domain implementation, similar performances were observed for FIR filters of length 33 or higher.

Estimation of Nuclear Medicine Exposure Measures Based on Intelligent Computer Processing.

This paper provides an in-depth discussion and analysis of the estimation of nuclear medicine exposure measurements using computerized intelligent processing. The focus is on the study of energy extraction algorithms to obtain a high energy resolution with the lowest possible ADC sampling rate and thus reduce the amount of data. This paper focuses on the direct pulse peak extraction algorithm, polynomial curve fitting algorithm, double exponential function curve fitting algorithm, and pulse area calculation algorithm. The detector output waveforms are obtained with an oscilloscope, and the analysis module is designed in MATLAB. Based on these algorithms, the data obtained from six different lower sampling rates are analyzed and compared with the results of the high sampling rate direct pulse peak extraction algorithm and the pulse area calculation algorithm, respectively. The correctness of the compartment model was checked, and the results were found to be realistic and reliable, which can be used for the analysis of internal exposure data in radiation occupational health management, estimation of internal exposure dose for nuclear emergency groups, and estimation of accidental internal exposure dose. The results of the compartment model of the respiratory tract and the compartment model of the digestive tract can be used to calculate the distribution and retention patterns of radionuclides and their compounds in the body, which can be used to assess the damage of radionuclide internal contamination and guide the implementation of medical treatment.

Study on design of visual intelligent detection instrument for aviation cable fault

Aviation cable is used to transmit electric energy and signal, and its performance directly affects the safety of aircraft. It is difficult to locate cable faults on aircraft and there is a lack of suitable high-precision detection equipment. Based on the Time-Domain Reflectometry Technology (TDR), combining with the embedded systems such as Raspberry Pi and FPGA, an aviation cable fault detector is designed. Firstly, based on the frequency-doubling clock generated by the PLL, the detector emits a low-voltage pulse whose width is smaller than the cycle of the source clock. Then, based on the multiple ADC sampling method, the detector samples the reflected pulse. Finally, the detector uses the intelligent algorithm to automatically determine the fault type and fault location, and displays the sampling waveform and detection results on the LCD screen. Through experimental verification, the detector can basically meet the requirements of aviation cable fault detection.

The GosipGUI Framework for Control and Benchmarking of Readout Electronics Front-Ends

The GOSIP (Gigabit Optical Serial Interface Protocol) provides communication via optical fibres between multiple kinds of front-end electronics and the KINPEX PCIe receiver board located in the readout host PC. In recent years a stack of device driver software has been developed to utilize this hardware for several scenarios of data acquisition. On top of this driver foundation, several graphical user interfaces (GUIs) have been created. These GUIs are based on the Qt graphics libraries and are designed in a modular way: All common functionalities, like generic I/O with the front-ends, handling of configuration files, and window settings, are treated by a framework class GosipGUI. In the Qt workspace of such GosipGUI frame, specific sub classes may implement additional windows dedicated to operate different GOSIP front-end modules. These readout modules developed by GSI Experiment Electronics department are for instance FEBEX sampling ADCs, TAMEX FPGA-TDCs, or POLAND QFWs. For each kind of front-end the GUIs allow to monitor specific register contents, to set up the working configuration, and to interactively change parameters like sampling thresholds during data acquisition. The latter is extremely useful when qualifying and tuning the front-ends in the electronics lab or detector cave. Moreover, some of these GosipGUI implementations have been equipped with features for mostly automatic testing of ASICs in a prototype mass production. This has been applied for the APFEL-ASIC component of the PANDA experiment currently under construction, and for the FAIR beam diagnostic readout system POLAND.

Frequency-offset-tolerant optical frequency comb-based coherent transmission for intra-datacenter interconnections.

In recent years, in order to increase the capacity and scalability of intra-datacenter (DC) transmission, the optical frequency comb (OFC) source has been considered promising to replace discrete lasers, aiming to reduce the cost of wavelength division multiplexing (WDM) transmission within DC. In this paper, an OFC based coherent architecture is proposed. An OFC, in the receiver side, is split by a splitter with a uniform power ratio and separately used as local oscillators (LOs) to detect the demultiplexed signals. The signal spectrum is copied onto every tone of the LO-OFC, and a large frequency offset (FO) tolerance is achieved. In addition, the required ADC sampling rate is the same as a system without FO. Extensive simulations are conducted. In the simulated coherent WDM transmission system, a 3-tone-OFC is used to provide 3 carriers, and an 11-tone-OFC is split and used to provide LO-OFCs. For a 64GBd polarization multiplexing 16 quadrature amplitude modulation (PM-16QAM) WDM transmission, the tolerances of FO are up to about ±0.3THz and ±0.374THz for the 1st/3rd signal, and the 2nd signal, respectively, below the pre-forward error correction (FEC) bit error rate (BER) level of 1.25×10-2. Moreover, the maximum tolerance of FO linearly increases with the number of effective tones in LO-OFC. Further, extensive experiments with back-to-back connection are conducted to verify the performance. The tolerance of FO is up to >36 GHz for 36GBd PM-16QAM transmission with a 3-tone-LO-OFC below the BER level of 1.25×10-2. The proposed OFC based coherent architecture is a promising solution for intra-DC interconnections with a large FO.

Weighted SPICE Algorithms for Range-Doppler Imaging Using One-Bit Automotive Radar

We consider the problem of range-Doppler imaging using one-bit automotive LFMCW1 or PMCW radar that utilizes one-bit ADC sampling with time-varying thresholds at the receiver. The one-bit sampling technique can significantly reduce the cost as well as the power consumption of automotive radar systems. We formulate the one-bit LFMCW/PMCW radar rangeDoppler imaging problem as one-bit sparse parameter estimation. The recently proposed hyperparameter-free (and hence user friendly) weighted SPICE algorithms, including SPICE, LIKES, SLIM and IAA, achieve excellent parameter estimation performance for data sampled with high precision. However, these algorithms cannot be used directly for one-bit data. In this paper we first present a regularized minimization algorithm, referred to as 1bSLIM, for accurate range-Doppler imaging using onebit radar systems. Then, we describe how to extend the SPICE, LIKES and IAA algorithms to the one-bit data case, and refer to these extensions as 1bSPICE, 1bLIKES and 1bIAA. These onebit hyperparameter-free algorithms are unified within the one-bit weighted SPICE framework. Moreover, efficient implementations of the aforementioned algorithms are investigated that rely heavily on the use of FFTs. Finally, both simulated and experimental examples are provided to demonstrate the effectiveness of the proposed algorithms for range-Doppler imaging using one-bit automotive radar systems.

Nonlinear distortion signal generation and THD measuring device

In order to generate nonlinear distortion when the amplifiers work in the nonlinear region, the system uses the transistor amplifiers to combine the analog switch and MCU to realize nonlinear distortion signal generation and THD(Total Harmonic Distortion) measurement device. The system is mainly composed of fixed gain amplifier circuit, multi-type signal selection circuit, class A and B complementary symmetric circuit, analog switch and microcontroller. The input signal is fixed as a 1KHz, 20mVp-p sinusoidal signal. Based on the influence of quiescent operation point on the common emitter amplifier circuit and the characteristics of Type B push-pull circuit, the analog switch is turned on or off by pressing the button of MCU to adjust the static working point and circuit structure to realize output of different types of signals. THD was calculated by sampling ADC inside MCU and FFT processing. The experimental results show that the system can successfully output sinusoidal signals and four kinds of nonlinear distortion signals (top distortion, bottom distortion, bidirectional distortion and cross-over distortion), and the peak-to-peak values are all greater than 2Vp-p. THD measurement error is less than 0.6%, which can achieve a more accurate measurement of total harmonic distortion.

A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion

A 4× interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages the performance advantages of ring amplifiers to unlock greater architectural freedom. The first pipeline stage MDAC with a “passive-hold” mode eliminates the sub-ADC sampling path and associated problems. A high-speed ringamp topology employs digital bias control, robust common-mode feedback (CMFB), and an elegant self-resetting behavior. An asynchronous, event-driven timing control system improves several aspects of performance and enables fully dynamic power consumption and modular design re-use. A general technique is presented whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be measured in the background with an analog hardware overhead of only one comparator. In this amplifier-intensive architecture utilizing 36 ringamps, the 4-GS/s ADC fabricated in 16-nm CMOS achieves 62-dB SNDR and 75-dB SFDR at Nyquist, consumes 75 mW (including input buffer), and has a Walden figure of merit (FoM) of 18 fJ/conversion-step and a Schreier FoM of 166 dB, advancing the state of the art in direct-RF sampling ADCs by roughly an order of magnitude.

Museum Display Showcase Furniture System Research Based on Internet of Things Technology in Intelligent Environment

The protection of cultural relics has always been an important issue in the field of museums and archaeology. With the development of Internet of Things technology, the security system of the museum is more intelligent and integrated. In order for the museum display system to keep up with the intelligent age, this article mainly studies the research and realization of the museum showcase system based on the Internet of Things technology in a smart environment. Before the start of the experiment, we developed the overall design of the system, including three functional modules: temperature module, illumination module, and monitoring module. The experiment is done mainly for system testing. The performance test of the sensor module needs to sample the temperature and humidity sensor to verify the accuracy of the temperature and humidity signal collected in the instrument circuit. The light information collection test uses the ADC sampling inside the CC2530 to obtain the required data and judges whether these temperature, humidity, and light intensity values exceed the preset values. The serial port needs to be initialized to carry out data communication and transmission normally. After the receiving end finishes receiving, the sending end will clear the data buffer to prepare for the next data transmission. The experimental data show that the error between the predicted value and measured value of the temperature system is about 3°C, which is within the allowable error range of the experiment. The results show that the system has perfect functions, is safe and reliable, meets the expected requirements, and has good practicability.

Implementation of the deconvolution method for signal peak detection in read-out ASIC

An application of the deconvolution method for signal peak detection in read-out ASIC for GEM detectors is described. Instead of usage of the conventional analog or digital peak detector, deconvolution technique to define the signal maximum was studied. In this case the digital data coming from the ADC are processed by a digital filter that deconvolves according to the pre-determined transfer function of the analog channel. Such processing allows to identify the signal peak values and also to provide reasonable pileup rejection. That enables higher rates of the incoming signals and reduces the amount of lost data.Combined with the analog channel employing 10-bit 25 MHz sampling rate ADC and 250 ns time constant 2nd-order shaper, the designed deconvolution block maintains peak detection accuracy within 9 LSBs. Time resolution of peak separation is 4 ADC sampling intervals or 100 ns.

Read-out analog channel with interpolator for signal peak finding

A prototype of an analog channel with a digital processing system for reading signals from GEM detectors is presented. Each channel consists of a charge-sensitive amplifier, a shaper, a switch, an amplifier and a 10-bits ADC. The data from the ADC is processed by the digital system based on an interpolator to find signal peaks. The interpolator uses a 6th order Lagrange polynomial. It maintains peak detection accuracy within 1.1 LSB at 25 MHz ADC sampling rate and 270 ns shaper peaking time.

An FPGA-based Direct Sampling and Digital Processing System for Wideband and Narrowband Radar Signal

This paper designs an integrated wideband and narrowband radar signal direct sampling and digital processing system based on FPGA. The system comprises a VPX case, a main board, a direct sampling board, a fiber board. It makes direct sampling of 1.8GHz-3.0GHz echo waves, with 3.2GHz sampling rate. The wideband and narrowband echo waves share the same ADC channel. After ADC sampling, both of wideband and narrowband data are exported to a mix-free digital quadrature demodulation module in FPGA. The narrowband data will be further processed by digital frequency down conversion. The wideband data will be further processed by digital de-chirp operation, with parallel DDS structure and multi-level decimation filters. Data rate of both the wideband and narrowband data after processing is decreased obviously. The designed sampling system cut down the analog radar signal processing operation, and decreases signal distortion. Besides, it integrated the reception, sampling and processing of wideband and narrowband signal, simplified the structure of radar system.