Sacrificial Silicon Research Articles

Flexible photonics in low stiffness doped silica for use in fibre reinforced polymer composite materials

The production of a flexible photonic device in doped silica with a Young's modulus that is significantly less than that of traditional silica glass is described. Here the purpose of reducing the modulus is to make planar sensors more applicable for integration into fibre reinforced polymer composite structures. The flexible planar substrate (58 μm thick) consists of three doped silica layers, fabricated using sacrificial silicon wafer processing. It is demonstrated that a Young's modulus of around 40 GPa can be achieved in comparison to a value above 70 GPa for typical silica glass. The optical response of a few mode waveguide that is direct UV written within the central core layer of the flexible glass platform is described. The mechanical stiffness of the platform is determined using nano-indentation tests and confirmed in mechanical tests that demonstrate clearly the flexible nature of the platform. To assess usability for applications integrated into structures undergoing mechanical loading the fatigue lifetime for one million bending cycles is investigated. No degradation to the optical response was observed under the performed testing.

A novel hardmask-to-substrate pattern transfer method for creating 3D, multi-level, hierarchical, high aspect-ratio structures for applications in microfluidics and cooling technologies

This letter solves a major hurdle that mars photolithography-based fabrication of micro-mesoscale structures in silicon. Conventional photolithography is usually performed on smooth, flat wafer surfaces to lay a 2D design and subsequently etch it to create single-level features. It is, however, unable to process non-flat surfaces or already etched wafers and create more than one level in the structure. In this study, we have described a novel cleanroom-based process flow that allows for easy creation of such multi-level, hierarchical 3D structures in a substrate. This is achieved by introducing an ultra-thin sacrificial silicon dioxide hardmask layer on the substrate which is first 3D patterned via multiple rounds of lithography. This 3D pattern is then scaled vertically by a factor of 200–300 and transferred to the substrate underneath via a single shot deep etching step. The proposed method is also easily characterizable—using features of different topographies and dimensions, the etch rates and selectivities were quantified; this characterization information was later used while fabricating specific target structures. Furthermore, this study comprehensively compares the novel pattern transfer technique to already existing methods of creating multi-level structures, like grayscale lithography and chip stacking. The proposed process was found to be cheaper, faster, and easier to standardize compared to other methods—this made the overall process more reliable and repeatable. We hope it will encourage more research into hybrid structures that hold the key to dramatic performance improvements in several micro-mesoscale devices.

Preparation and properties of SiC/SiOX heterojunction fiber reinforced porous SiC composite materials

Porous silicon carbide composite ceramics were prepared by partial sintering method and sacrificial silicon, with phenolic resin applied as carbon template, and silicon powder as silicon source and pore-forming agent. It showed a composite structure of SiC/SiO2/SiC sandwich shell structure and SiC/SiOX heterojunction nanofiber. Through an investigation into the effect of carbon-silicon atomic ratio on the structure and thermodynamic properties of porous SiC. It was revealed that the carbon network formed by the phenolic resin played a role in restricting the position of the silicon powder and building a regularly-arranged porous SiC structure. The prepared samples reached a porosity of 50–75% while exhibiting a low thermal conductivity ranging from 0.74 to 1.3 W/(m·K), which is attributed to the nanoscale phonon dispersion mechanism and nanofiber thermal insulation, together with high stiffness. Porous ceramics demonstrate both mechanical and thermal insulation properties, which makes them applicable as thermal protection materials for hypersonic aircraft. This is effectively in reducing the aerodynamic thermal effects of hypersonic aircraft.

Improvement of thermal‐type MEMS flow sensor chip via new process of silicon etching with sacrificial polycrystalline silicon layer

AbstractThis paper reports upon a new process for the flow sensor fabrication of a thermal microelectromechanical systems (MEMS) and its performance improvement. A unique feature of the proposed process is the silicon etching, which is a combination of normal crystal‐oriented silicon etching and isotropic etching of polycrystalline silicon (poly‐Si). The poly‐Si layer works as a sacrificial layer and promotes etching of the silicon substrate in the horizonal direction, thereby enabling location of the etching holes in the membrane of the flow sensor without the conventional etching rules. Some designs for the flow sensors, which have been infeasible with normal processes, were thus fabricated and evaluated. Hence, the new process improves the design flexibility of the membrane and enhances flow sensor performance, such as 38.3% reduction in power consumption.

Realization of a Graphene/PMMA Acoustic Capacitive Sensor Released by Silicon Dioxide Sacrificial Layer

We report the realization of an acoustic capacitive microphone formed by graphene/poly(methyl methacrylate) (PMMA). It is the first time that the ultra-large graphene/PMMA membrane suspended fully over the cavity has been fabricated by releasing the silicon dioxide sacrificial layer underneath the membrane. The novelty in the fabrication method is that the silicon dioxide layer has been etched by hydrogen fluoride vapor from the back of the partly etched silicon substrate. Using the new process, the ultra-large graphene/PMMA membrane, with a diameter to thickness ratio of 7800, has been suspended over the cavity with a 2 μm air gap. The spacing of 2 μm is the minimum gap over the graphene-based acoustic capacitive microphones which have been reported so far. The static deformation of the suspended graphene/PMMA membrane after silicon dioxide has been etched is estimated to be 270 nm. The aspect ratio of the membrane's diameter over its static deformation is around 13,000, which shows that the graphene/PMMA membrane with a diameter of a few millimeters can be transferred and suspended over the substrate with relatively small deformation by releasing the sacrificial silicon dioxide layer. The dynamic behavior of the device under electrostatic actuation has been characterized. The acoustic response of the graphene/PMMA capacitive microphone has been measured, and the sensitivity has been observed to be -47.5 dB V (4.22 mV/Pa) ± 10%. The strain in the graphene/PMMA membrane is estimated to be 0.034%.

Sacrificial Materials and Release Etchants for Metal MEMS That Reduce or Eliminate Hydrogen-Induced Residual Stress Change

Metal microelectromechanical systems (MEMS) provide attractive properties such as high reflectivity and high conductivity. They are typically processed using an organic sacrificial layer that is removed by an oxygen ash. This enables low-temperature processing but presents other problems. For example, ashing is not applicable to metals that are susceptible to oxidation. However, if an inorganic sacrificial silicon dioxide is used, its removal commonly involves acids, exposure to which can be detrimental to metals. For example, metallic films are susceptible to hydrogen incorporation, resulting in large compressive stress. In recent work with structural tantalum and sacrificial silicon dioxide as a model system, we demonstrated that hydrogen injected during the release process can induce 1200 MPa compressive stress. This work explores AlN and Cu as alternative sacrificial materials in which release etching of structural Ta by AZ 400K developer and FeCl3 solution, respectively, is hydrogen free. Isotropic release etching is observed for Cu at room temperature and for AlN above 60 °C. In comparison with 1200 MPa, the uniaxial stress change after structure release is 80 MPa compressive with Cu and is unchanged after AlN sacrificial etch. [2021-0005]

Sacrificial grid release technology: a versatile release concept for MEMS structures

Micro-electro-mechanical-systems (MEMS) structures with different in-plane dimensions often need to be released simultaneously from the bulk of the wafer and a single dry etching or wet etching technique cannot fulfill all release requirements. In this paper we present a universally applicable solution to release MEMS structures with different surface areas in a controlled and uniform way, which combines isotropic etching of a sacrificial silicon support structure by xenon difluoride with a predefined etch surface made by deep reactive ion etching. Two applications of this Sacrificial Grid Release Technology are presented, in which MEMS devices are released in silicon-on-insulator wafers. The demonstrated applications involve the release of microstructures with in-plane dimensions ranging from tens of micrometers to a few millimeters. The sacrificial silicon structure provides mechanical support which allows freedom in process flow design for fragile MEMS structures. The release technique can also be used to separate the chips from the wafer.

Aluminum doped zinc oxide deposited by atomic layer deposition and its applications to micro/nano devices

This work reports investigation on the deposition and evaluation of an aluminum-doped zinc oxide (AZO) thin film and its novel applications to micro- and nano-devices. The AZO thin film is deposited successfully by atomic layer deposition (ALD). 50 nm-thick AZO film with high uniformity is checked by scanning electron microscopy. The element composition of the deposited film with various aluminum dopant concentration is analyzed by energy-dispersive X-ray spectroscopy. In addition, a polycrystalline feature of the deposited film is confirmed by selected area electron diffraction and high-resolution transmission electron microscopy. The lowest sheet resistance of the deposited AZO film is found at 0.7 kΩ/□ with the aluminum dopant concentration at 5 at.%. A novel method employed the ALD in combination with the sacrificial silicon structures is proposed which opens the way to create the ultra-high aspect ratio AZO structures. Moreover, based on this finding, three kinds of micro- and nano-devices employing the deposited AZO thin film have been proposed and demonstrated. Firstly, nanowalled micro-hollows with an aspect ratio of 300 and a height of 15 µm are successfully produced. Secondly, micro- and nano-fluidics, including a hollow fluidic channel with a nanowall structure as a resonator and a fluidic capillary window as an optical modulator is proposed and demonstrated. Lastly, nanomechanical resonators consisting of a bridged nanobeam structure and a vertical nanomechanical capacitive resonator are fabricated and evaluated.

Manipulating Etch Selectivities in XeF₂ Vapour Etching

The vapour etching of silicon sacrificial layers is often a critical process in the fabrication of micro/nanosystems. This method has a number of attractive features, in particular, high etch rates of sacrificial silicon layers and good selectivities associated with photoresist, SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , stoichiometric Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> and a number of regularly used metal films. However, materials that are commonly inert to XeF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> are etched when located in the proximity of a silicon sacrificial layer. This proximity is a common situation in the fabrication of such systems and can become a critical issue affecting process control and device reliability. This work uses test structures that have been designed to be very sensitive, thereby delivering much lower selectivities then are typically reported in the literature. This sensitive quantification of the proximity effect is used to evaluate methods designed to improve the selectivity. This work suggests that a reduction in the processing temperature from 25°C to 10°C increases the Si: PECVD SiN selectivity by 68%. However, a more easily implemented modification is to flow hydrogen into the reaction chamber. This method improves the Si: PECVD SiN selectivity by an order of magnitude and the Si: LPCVD SiN selectivity between 200% and 600%.

Development of a robust fabrication process for single silicon nanowire-based omega gate transistors on polyamide substrate

Single silicon nanowire (SiNW) omega-gate field-effect transistors have been fabricated using a standard photolithography method on a Kapton flexible polyamide thin film attached to a sacrificial silicon substrate. SiNWs have been grown by the chemical vapor deposition method using a vapor–liquid–solid mechanism and gold as the catalyst. A key step for proper SiNW integration, Kapton surface flattening, was performed via an innovative method based on soap. Contrary to a previously reported integration process on flexible substrates, this flexible/rigid hybrid substrate is compatible with temperature as high as , allowing the formation of low-resistive nickel silicide at the source/drain contacts. As a consequence, our devices can exhibit excellent electrical properties such as hole mobility, 105 ratio and subthreshold slope of about . These parameters can compete with those of organic transistors or in some aspects even exceeding electrical parameters of similar single SiNW transistors fabricated onto flexible substrates. In addition, after separation from the rigid silicon substrate, devices on Kapton experience a significant improvement in their performance, such as two orders of magnitude for ratio and halving the subthreshold slope. This flexible/rigid hybrid substrate, offering high chemical and thermal stability, as well as preserving good electrical features and even improving them, after detaching and transfering the polyamide layer to a plastic substrate, which opens up a new route for the integration of further nanostructures.

Fabrication of Ultra-High Aspect Ratio (>420:1) Al2O3 Nanotube Arraysby Sidewall TransferMetal Assistant Chemical Etching.

We report a robust, sidewall transfer metal assistant chemical etching scheme for fabricating Al2O3 nanotube arrays with an ultra-high aspect ratio. Electron beam lithography followed by low-temperature Au metal assisted chemical etching (MacEtch) is used to pattern high resolution, high aspect ratio, and vertical silicon nanostructures, used as a template. This template is subsequently transferred by an atomic layer deposition of the Al2O3 layer, followed by an annealing process, anisotropic dry etching of the Al2O3 layer, and a sacrificial silicon template. The process and characterization of the Al2O3 nanotube arrays are discussed in detail. Vertical Al2O3 nanotube arrays with line widths as small as 50 nm, heights of up to 21 μm, and aspect ratios up to 420:1 are fabricated on top of a silicon substrate. More importantly, such a sidewall transfer MacEtch approach is compatible with well-established silicon planar processes, and has the benefits of having a fully controllable linewidth and height, high reproducibility, and flexible design, making it attractive for a broad range of practical applications.

A novel hybrid technique to fabricate silicon-based micro-implants with near defect-free quality for neuroprosthetics application.

This paper introduces a new hybrid microfabrication technique which combines ultra-precision micro-milling and a ductile sacrificial material deposition process to fabricate a silicon-based implant for neuroprosthetics applications with near defect-free quality at several hundreds of micrometres in thickness. The sacrificial materials can influence the quality of silicon during machining. The cutting mechanism and feasibility of the hybrid technique are studied by molecular dynamics (MD) simulations and experiments. Due to the complexity of modelling PMMA and SU-8 structures in MD environment, only copper was modelled as the simulation is intended to understand the performance of using a ductile sacrificial layer structure in silicon machining. MD analysis shows that the reduced stress intensity and subsurface damage were mainly attributed to workpiece plasticity enhancement, where its mechanism was contributed by better deformability of the ductile sacrificial layer and enhanced thermal softening from the heat generated by the high interfacial stress between the sacrificial layer and silicon substrate. Despite the MD simulation and experiment having different machining scale in terms of cutting parameters, phenomenal behaviours of the cutting performance when observed under the experimental conditions are in good agreement with simulation. Experimental verification shows that near defect-free quality was achieved at large cutting depth of 150μm when silicon is coated either with PMMA or SU-8. An exemplary implant structure was also fabricated to better demonstrate the hybrid technique's capability. In addition, the hybrid technique will be beneficial for low volume high customisation applications as it is a serial process.

Hole Formation in a Diamond Substrate of Hybrid-Monolithic Integral SHF Schemes

In this paper, we study the technological process of separating a heteroplate from a polycrystalline diamond film (PDF-Si), separating a whole plate from sacrificial silicon. The hole formation in a diamond substrate from PDF via laser milling and plasma-chemical etching is studied. Plasma-chemical etching provided batch hole fabrication based on planar technology and precision lithography. The technological modes of hole etching through an aluminum mask via reactive ion etching with an inductively coupled plasma source (RIE-ICP) were optimized. The hole etching rate in the PDF was ~ 1.1 μm/min. A mathematical model of the technological process is developed. Etching is shown to occur mainly in oxygen. The technological process is adapted for the plasma-chemical etching setup “Plasma TM5”. The possibility of etching in a PDF holes 100 μm in diameter and more than 300 μm deep was studied. The etching rate was shown to depend on the hole depth and is nonlinear in nature, with etching of the hole walls and the aluminum mask.

A route towards the fabrication of 2D heterostructures using atomic layer etching combined with selective conversion

Heterostructures of low-dimensional semiconducting materials, such as transition metal dichalcogenides (MX2), are promising building blocks for future electronic and optoelectronic devices. The patterning of one MX2 material on top of another one is challenging due to their structural similarity. This prevents an intrinsic etch stop when conventional anisotropic dry etching processes are used. An alternative approach consist in a two-step process, where a sacrificial silicon layer is pre-patterned with a low damage plasma process, stopping on the underlying MoS2 film. The pre-patterned layer is used as sacrificial template for the formation of the top WS2 film. This study describes the optimization of a cyclic Ar/Cl2 atomic layer etch process applied to etch silicon on top of MoS2, with minimal damage, followed by a selective conversion of the patterned Si into WS2. The impact of the Si atomic layer etch towards the MoS2 is evaluated: in the ion energy range used for this study, MoS2 removal occurs in the over-etch step over 1–2 layers, leading to the appearance of MoOx but without significant lattice distortions to the remaining layers. The combination of Si atomic layer etch, on top of MoS2, and subsequent Si-to-WS2 selective conversion, allows to create a WS2/MoS2 heterostructure, with clear Raman signals and horizontal lattice alignment. These results demonstrate a scalable, transfer free method to achieve horizontally individually patterned heterostacks and open the route towards wafer-level processing of 2D materials.

Influence of Sacrificial Layer Germanium Content on Stacked-Nanowire FET Performance

The stacked nanowire field-effect transistor is an important option for future generations of CMOS technology. It features superior electrostatic control due to all-around gates while maintaining sufficient drive currents by stacking multiple channels. One of the challenges for manufacturing such devices is the fabrication of inner spacers between the nanowires in order to control the parasitic capacitances. A previously demonstrated approach for inner spacer fabrication uses the wet chemical etching of a sacrificial silicon–germanium layer between the silicon channels in order to prepare a cavity into which the spacer material is deposited. The etch rate of the sacrificial layer depends on the germanium content. Thus, the variations of the Si–Ge composition across the wafer lead to the corresponding geometrical variations of the transistor structures. This work traces the effect of Si–Ge composition variations via the inner spacer geometry on the key electrical properties of the devices using the numerical simulations. A significant impact on on-current and capacitances was determined. It could be shown that the dependence of the current on the Si–Ge composition is closely related to the doping profile in the nanowires. These results improve the understanding of sources of variability in nanowire transistors and, hence, may help to improve device reproducibility.

Laser ablation microgrooving and nanostructured silicon surfaces for an effective gettering process and reduced optical losses

This work investigates the effect of laser microgrooved monocrystalline silicon surfaces to improve the gettering effectiveness of Si substrates for enhanced solar cell electrical properties. A combination of microgrooves and a grown sacrificial porous silicon layer (PSL), subjected to a heat treatment at different temperatures was considered to point out the crucial role of the microgrooves during the gettering procedure. This treatment leads to a significant decrease of the impurities concentration and recombination activities, in addition to a noticeable enhancement of light trapping, enabling an increased carrier collection probability. The microgrooves were made by means of NWR 213 laser ablation system. The PS layers were performed by a thermal activated stain etching method that will act as sacrificial trapping layers of the gettered impurities. The topography of the patterned surfaces with and without PSLs was investigated using field emission scanning electron microscopy (FESEM). As we expected, the combination of microgrooves with higher density at both surfaces and PSL improved obviously the optoelectronic properties of the processed solar cells. The minority carrier lifetime measured by means of the photoconductive decay method (PCD) was significantly increased from 9.2 μsec to 89 μsec. The Hall Effect measurement shows a significant increase of the carrier mobility. Moreover, the dark IV characteristics and the internal quantum efficiency (IQE) found to be improved. An apparent enhancement of the open circuit voltage Voc and current density Jsc was obtained indicating improved solar cell electrical properties.

Highly Selective Silicon Dry Chemical Etch Technique for Advanced FinFET Technology

With transistor scaling in 7nm technology and beyond, sacrificial silicon materials etches (e.g. dummy poly silicon gate removal) are considered to be among the most challenging hurdle in FinFET process development. In this paper, we present a dry chemical etch technique for selective etching of single crystal, poly-crystal and amorphous silicon on various FinFET device process steps. It was demonstrated that this technique could completely remove poly silicon in vertically high aspect ratio (AR>5) FinFET gates with a large process window (over-etch budget ~200%) while achieving the lowest gate leakage current and best short channel FET yield. Proper surface preparation, queue time control and etch by-product removal strategies are discussed. The residue free etch and etch by-product sublimation mechanisms are also investigated by High Resolution Electron Microscopy (HREM) and Fourier Transform Infrared Spectroscopy (FTIR) surface analysis. This work was performed by the IBM Research at various IBM Research and Development Facilities.

Multimaterial Nanoporous Membranes Shaped through High Aspect-Ratio Sacrificial Silicon Nanostructures.

We present an innovative fabrication method for solid-state nanoporous membranes based on the casting of sacrificial silicon nanostructures. The process allows the individual definition of geometry and placement of each nanopore through e-beam lithography and is compatible with a wide range of materials without the need to adapt the process to the materials used. We demonstrate the fabrication of membranes integrating high aspect-ratio nanopores with critical dimensions as small as 30 nm, 1.2 μm in length, with round or elongated shapes, and made of silicon dioxide or amorphous carbon. The capability to engineer nanoporous membranes made of a variety of materials and with tailored designs will lead to new applications in the field of electrochemical sensing, flow modulation, or the chemical functionalization of nanopores.

Optimized process for fabrication of free-standing silicon nanophotonic devices.

A detailed procedure is presented for fabrication of free-standing silicon photonic devices that accurately reproduces design dimensions while minimizing surface roughness. By reducing charging effects during inductively coupled-plasma reactive ion etching, undercutting in small, high-aspect ratio openings is reduced. Slot structures with a width as small as 40 nm and an aspect ratio of 5.5:1 can be produced with a nearly straight, vertical sidewall profile. Subsequent removal of an underlying sacrificial silicon dioxide layer by wet-etching to create free-standing devices is performed under conditions which suppress attack of the silicon. Slotted one-dimensional photonic crystal cavities are used as sensitive test structures to demonstrate that performance specifications can be reached without iteratively adapting design dimensions; optical resonance frequencies are within 1% of the simulated values and quality factors on the order of 105 are routinely attained.

Epitaxial lift-off of electrodeposited single-crystal gold foils for flexible electronics.

We introduce a simple and inexpensive procedure for epitaxial lift-off of wafer-size flexible and transparent foils of single-crystal gold using silicon as a template. Lateral electrochemical undergrowth of a sacrificial SiO x layer was achieved by photoelectrochemically oxidizing silicon under light irradiation. A 28-nanometer-thick gold foil with a sheet resistance of 7 ohms per square showed only a 4% increase in resistance after 4000 bending cycles. A flexible organic light-emitting diode based on tris(bipyridyl)ruthenium(II) that was spin-coated on a foil exploited the transmittance and flexibility of the gold foil. Cuprous oxide as an inorganic semiconductor that was epitaxially electrodeposited onto the gold foils exhibited a diode quality factor n of 1.6 (where n = 1.0 for an ideal diode), compared with a value of 3.1 for a polycrystalline deposit. Zinc oxide nanowires electrodeposited epitaxially on a gold foil also showed flexibility, with the nanowires intact up to 500 bending cycles.