Run-time Reconfiguration Research Articles

An architecture based on computing with words to support runtime reconfiguration decisions of service-based systems

Service-based systems (SBSs) need to be reconfigured when there is evidence that the selected Web services configurations no further satisfy the specifications models and, thus the decision-related models will need to be updated accordingly. However, such updates need to be performed at the right pace. On the one hand, if the updates are not quickly enough, the reconfigurations that are required may not be detected due to the obsolescence of the specification models used at runtime, which were specified at design-time. On the other hand, the other extreme is to promote premature reconfiguration decisions that are based on models that may be highly sensitive to environmental fluctuations and which may affect the stability of these systems. To deal with the required trade-offs of this situation, this paper proposes the use of linguistic decision-making (LDM) models to represent specification models of SBSs and a dynamic computing-with-words (CWW) architecture to dynamically assess the models by using a multi-period multi-attribute decision making (MP-MADM) approach. The proposed solution allows systems under dynamic environments to offer improved system stability by better managing the trade-off between the potential obsolescence of the specification models, and the required dynamic sensitivity and update of these models.

Reconfigurable Digital Channelizer Design Using Factored Markov Decision Processes

In this work, a novel digital channelizer design is developed through the use of a compact, system-level modeling approach. The model efficiently captures key properties of a digital channelizer system and its time-varying operation. The model applies powerful Markov Decision Process (MDP) techniques in new ways for design optimization of reconfigurable channelization processing. The result is a promising methodology for design and implementation of digital channelizers that adapt dynamically to changing use cases and stochastic environments while optimizing simultaneously for multiple conflicting performance goals. The method is used to employ an MDP to generate a runtime reconfiguration policy for a time-varying environment. Through extensive simulations, the robustness of the adaptation is demonstrated in comparison with the prior state of the art.

Component-Based Systems Reconfigurations Using Graph Transformations with GROOVE

Component-based systems permit standardisation and re-usability of code through the use of components. The architecture of component-based systems can be modified thanks to dynamic reconfigurations, which contribute to systems’ (self-)adaptation by adding or removing components without incurring any system downtime. In this context, the present article describes a formal model for dynamic reconfigurations of component-based systems. It provides a way of expressing runtime reconfigurations of a system and proving their correctness according to a static invariant for consistency constraints and/or a user-provided post-condition. Guarded reconfigurations allow us to build reconfigurations based on primitive reconfiguration operations using sequences of reconfigurations and the alternative and the repetitive constructs, while preserving configuration consistency. A practical contribution consists of the implementation of a component-based model using the GROOVE graph transformation tool. This implementation is illustrated on a cloud-based multi-tier application hosting environment managed as a component-based system. In addition, after enriching the model with interpreted configurations and reconfigurations in a consistency compatible manner, component systems’ implementations are related to their specifications by a simulation relation.

CoRQ: Enabling Runtime Reconfiguration Under WCET Guarantees for Real-Time Systems

Real-time systems have an increasing demand for predictable performance. Only recently novel models and analyses were proposed that make the performance benefits of runtime-reconfigurable architectures accessible for optimized worst-case execution time (WCET) guarantees. However, the implicit assumption in these works is that the process of reconfiguration itself complies with execution time guarantees. The realization of a reconfiguration controller that fulfills these assumptions and that is amenable to WCET guarantees is so far unavailable. In this letter, we detail the challenges of runtime reconfiguration in real-time systems and show that conflicts while accessing a shared main memory during reconfiguration can lead to a slowdown of more than ${21\times }$ in reconfiguration bandwidth. We present concepts that enable runtime reconfiguration under WCET guarantees and release our implementation of these concepts as open source.

HEAL-WEAR: An Ultra-Low Power Heterogeneous System for Bio-Signal Analysis

Personalized healthcare devices enable low-cost, unobtrusive and long-term acquisition of clinically relevant biosignals. These appliances, termed wireless body sensor nodes (WBSNs), are fostering a revolution in health monitoring for patients affected by chronic ailments. Nowadays, WBSNs often embed complex digital processing routines, which must be performed within an extremely tight energy budget. Addressing this challenge, in this paper, we introduce a novel computing architecture devoted to the ultra-low power analysis of biosignals. Its heterogeneous structure comprises multiple processors interfaced with a shared acceleration resource, implemented as a coarse-grained reconfigurable array (CGRA). The CGRA mesh effectively supports the execution of the intensive loops that characterize biosignal analysis applications, while requiring a low reconfiguration overhead. Moreover, both the processors and the reconfigurable fabric feature single-instruction/multiple data (SIMD) execution modes to increase efficiency when multiple data streams are concurrently processed. The run-time behavior on the system is orchestrated by a lightweight hardware mechanism, which concurrently synchronizes processors for SIMD execution and regulates access to the reconfigurable accelerator. By jointly leveraging run-time reconfiguration and SIMD execution, the illustrated heterogeneous system achieves, when executing complex biosignal analysis applications, speedups of up to $11.3\times $ on the considered kernels and up to 37.2% overall energy savings, with respect to an ultra-low power multi-core platform, which does not feature CGRA acceleration.

A novel transceiver structure including power and audio amplifiers for Internet of Things applications

Both of the Circuit and System design aspects of the Internet of Things (IoT) are emerging with computation and communication issues. In communication, it utilizes transceivers like wireless sensor network (WSN). In spite of the conventional WSN, a key component of IoT is its direct engagement with humans (animals). Therefore, communication is required in audio–visual ranges. This means an IoT device (IoTD) will be ported with audio amplifiers. This paper presents a novel IoT transceiver with a reconfigurable PA-CDA with time-domain and task-oriented multiplexing. The run-time reconfiguration of an area-power-efficient common part is utilized. The topology and scheduling issues of the Bluetooth Low Energy (BLE) standard are well-suited to the proposed architecture. Time, energy, and protocol concerns are studied and appropriate models presented. The PA and CDA operate in the 2.4 GHz and audio-range frequencies, respectively. The battery life and power consumption are improved by about 40% and 20%, respectively.

Self-reconfigurable architectures for HEVC Forward and Inverse Transform

This work introduces a run-time reconfigurable system for HEVC Forward and Inverse Transforms that can adapt to time-varying requirements on resources, throughput, and video coding efficiency. Three scalable designs are presented: fully parallel, semi parallel, and iterative. Performance scalability is achieved by combining folded/unfolded 1D Transform architectures and one/two transposition buffers. Resource usage is optimized by utilizing both the recursive even–odd decomposition and distributed arithmetic techniques. The architecture design supports video sequences in the 8K Ultra High Definition format (7680 × 4320) with up to 70 frames per second when using 64 × 64 Coding Tree Blocks with variable transform sizes. The self-reconfigurable embedded system is implemented and tested on a Xilinx® Zynq-7000 All-Programmable System-on-Chip (SoC). Results are presented in terms of performance (frames per second), resource utilization, and run-time hardware adaptation for a variety of hardware design parameters, video resolutions, and self-reconfigurability scenarios. The presented system illustrates the advantages of run-time reconfiguration technology on PSoCs or FPGAs for video compression.

Reconfigurable Constant Multiplication for FPGAs

This paper introduces a new heuristic to generate pipelined run-time reconfigurable constant multipliers for field-programmable gate arrays (FPGAs). It produces results close to the optimum. It is based on an optimal algorithm which fuses already optimized pipelined constant multipliers generated by an existing heuristic called reduced pipelined adder graph (RPAG). Switching between different single or multiple constant outputs is realized by the insertion of multiplexers. The heuristic searches for a solution that results in minimal multiplexer overhead. Using the proposed heuristic reduces the run-time of the fusion process, which raises the usability and application domain of the proposed method of run-time reconfiguration. An extensive evaluation of the proposed method confirms a 9%–26% FPGA resource reduction on average compared to previous work. For reconfigurable multiple constant multiplication, resource savings of up to 75% can be shown compared to a standard generic lookup table based multiplier. Two low level optimizations are presented, which further reduce resource consumption and are included into an automatic VHDL code generation based on the FloPoCo library.

Towards the encapsulation and decentralisation of OKD-MES services within embedded devices

Traditionally, the resources of embedded devices which are employed for process control at shop floors were resource constrained. However, advances in embedded system technologies permit the enhancement of the processing and storage capabilities of embedded devices. Therefore, semantic descriptions of manufacturing systems can now be hosted and computed at the device level. This fact permits the creation of a decentralised solution for controlling processes at the lowest level of the manufacturing enterprises and the reduction in the time and effort requirements for the configuration and information exchange. The eScop project presented the Open Knowledge-Driven Manufacturing Execution System (OKD-MES) solution, which enables monitoring and controlling production systems openly and allows runtime re-configurability of interconnected industrial equipment and services. This research work presents how part of the OKD-MES functionality can be handled at lower level. More precisely, the OKD-MES representation and management of knowledge can be decentralised and handled at the shop floor level, where the industrial machines are connected to devices that are capable of controlling the execution of processes. The main objective of this paper is to describe a decentralised vision for the OKD-MES framework, which is a centric solution in terms of knowledge management. Moreover, the article also discusses some of the advantages to be gained from decentralising the management of knowledge model semantic descriptions.

Run-time Reconfigurable Acceleration for Genetic Programming Fitness Evaluation in Trading Strategies

Genetic programming can be used to identify complex patterns in financial markets which may lead to more advanced trading strategies. However, the computationally intensive nature of genetic programming makes it difficult to apply to real world problems, particularly in real-time constrained scenarios. In this work we propose the use of Field Programmable Gate Array technology to accelerate the fitness evaluation step, one of the most computationally demanding operations in genetic programming. We propose to develop a fully-pipelined, mixed precision design using run-time reconfiguration to accelerate fitness evaluation. We show that run-time reconfiguration can reduce resource consumption by a factor of 2 compared to previous solutions on certain configurations. The proposed design is up to 22 times faster than an optimised, multithreaded software implementation while achieving comparable financial returns.

Energy efficient processing of motion estimation for embedded multimedia systems

Visual sensor networks require low power compression techniques of large amount of video data in each camera node due to the energy-constrained and bandwidth-limited environments. In this paper, energy-efficient architecture for Variable Block Size Motion Estimation is proposed to fully utilize dynamic partial reconfiguration capability of programmable hardware fabric in distributed embedded vision processing nodes. Partial reconfiguration of FPGA is exploited to support run-time reconfiguration of the proposed modular hardware architecture for motion estimation. According to the required search range, hardware reconfiguration is performed adaptively to reduce the hardware resources and power consumption. A reconfigurable ME ranging from simple 1-D to a complex 2-D Sum of Absolute Differences (SAD) array to perform full search block matching is selected in order to support different search window size. The implemented scalable SAD array can provide different resolutions and frame rates for real time applications with multiple reconfigurable regions.

Flexible and timely on-line integration of medical services using iLand middleware

Modern medical systems are intensive in the use of distribution technology in medical services. Communication among professionals and patients is enabled to exchange patient information, and for on-line monitoring of health conditions. A miriad of specialized middleware solutions that have appeared in this domain, typically focus on providing more and more patient-data processing services over basic communication backbones (e.g., from pure socket communication to more sophisticated interaction models). Paradigms such as service oriented architectures and decoupled communication middleware support the development of emerging medical systems based on the composition of existing (posibly remote) services into a new application. This adjusts to the phylosophy of systems of systems (SoS) development. In a cyber-physical medical domain, service based applications require support for this composition in a way that a new application is created (or simply modified) in a timely fashion. iLand middleware supports this phylosophy, enabling both off-line and run-time reconfiguration of distributed service based applications. It provides timely operation, controlled communication delays, and a decoupled interaction model for stateless services. iLand has been used in medical applications for remote patient monitoring and in surveillance domains for remote real-time video transmission. This paper presents the systems that iLand has enabled in the medical domain, mainly based on remote patient monitoring. These iLand-based systems have shown to be flexible and capable of undergoing timely service reconfigurations.

Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures

Dynamically reconfigurable architectures, such as NATURE, achieve high logic density and low reconfiguration latency compared to traditional field-programmable gate arrays. Unlike fine-grained NATURE, reconfigurable DSP block incorporated NATURE architecture achieves significant improvement in performance for mapping compute-intensive arithmetic operations. However, the DSP block fails to fully exploit the potential provided by the run-time reconfiguration. This paper presents a pipeline reconfigurable DSP architecture to target the NATURE platform that supports temporal logic folding. The proposed approach allows the DSP pipeline stages to be reconfigured independently such that different functions can be performed distinctively and individually at every clock interval during runtime. In addition, a multistage clock gating technique is also used in the design to minimize the power consumption. We also extend NanoMap tool for mapping circuits on NATURE platform to exploit the pipeline-level reconfigurability of our proposed DSP block to enable efficient resource sharing and area/power reduction. Simulation results on 13 benchmarks show that the proposed approach enables area-delay improvement of up to 3.6\(\times \) compared to the fine-grained NATURE architecture. The proposed architecture also delivers 31.42% reduction in area and a maximum of 4.18\(\times \) improvement in power-delay compared to existing NATURE architecture. We also observe an average improvement of 29 and 54.13% in performance and area when compared to commercial Xilinx Spartan-3A DSP platform, thereby allowing the designers to tune the circuit implementations for the area, power, or performance benefits.

Timing Analysis of Tasks on Runtime Reconfigurable Processors

Real-time embedded systems need to be analyzable for timing guarantees. Despite significant scientific advances, however, timing analysis lags years behind current microarchitectures with out-of-order scheduling pipelines, several hardware threads, and multiple (shared) cache layers. To satisfy the increasing performance demands, analyzable performance features are required. We propose a novel timing analysis approach to introduce runtime reconfigurable instruction set processors as one way to escape the scarcity of analyzable performance while preserving the flexibility of the system. We introduce extensions to the state-of-the-art Integer linear programming (ILP)-based program path analysis for computing precise worst case time bounds in the presence of the widely used technique to continue processor execution during reconfiguration by emulating not yet reconfigured custom instructions (CIs) in software. We identify and safely bound a timing anomaly of runtime reconfiguration, where executing faster than worst case time during reconfiguration extends the execution time of the whole program. Stalling the processor during reconfiguration (easier to analyze but not state-of-the-art for reconfigurable processors) is not required in our approach. Finally, we show the precision of our analysis on a complex multimedia application with multiple reconfigurable CIs for several hardware parameters and give advice on how to deal with reconfiguration delay under timing guarantees.

Runtime Reconfiguration of FPGA for Biomedical Applications

Runtime Reconfiguration of FPGA for Biomedical Applications

RSCM technology for developing runtime-reconfigurable telecommunication applications

Runtime reconfiguration is a fundamental requirement of many telecommunication applications which also has been addressed by management standards like CMIP, 3GPP TS 32.602, and NETCONF. Two basic commands considered by these standards are CREATE and DELETE which operate on managed objects inside an application. The available configuration management technologies, like JMX, OSGi, and Fractal, do not support the CREATE and DELETE reconfiguration commands of the telecommunication standards. In this paper, we introduce a novel technology, called RSCM, for development of runtime reconfigurable applications complying with the telecommunication standards. The RSCM subagent takes the responsibility of loading the application from the configuration file, executing the runtime reconfiguration commands (including CREATE and DELETE), enforcing validity of the configuration state, and updating the configuration file according to the latest reconfiguration commands. We exploit the modular and object oriented features of the XML technology for storing the configuration state of a program in a configuration file. The software development process is tailored such that the design of XML schemas of managed classes is performed parallel to the design of software classes. In addition, a novel programming approach based on indirect referencing is proposed which allows safe and almost immediate deletion of managed objects at runtime. This indirect referencing mechanism affects the implementation of associations in class diagrams and prevents methods of a class to use the “this” pointer freely. The RSCM technology has been successfully used in several commercial telecommunication applications; including an SMS service center, an SMS gateway, and an SMS hub.

Improving Energy Efficiency of OFDM Using Adaptive Precision Reconfigurable FFT

Being an essential issue in digital systems, especially battery-powered devices, energy efficiency has been the subject of intensive research. In this research, a multi-precision FFT module with dynamic run-time reconfigurability is proposed to trade off accuracy with the energy efficiency of OFDM in an SDR-based architecture. To support variable-size FFT, a reconfigurable memory-based architecture is investigated. It is revealed that the radix-4 FFT has the minimum computational complexity in this architecture. Regarding implementation constraints such as fixed-width memory, a noise model is exploited to statistically analyze the proposed architecture. The required FFT word-lengths for different criteria--namely BER, modulation scheme, FFT size, and SNR--are computed analytically and confirmed by simulations in AWGN and Rayleigh fading channels. At run-time, the most energy-efficient word-length is chosen and the FFT is reconfigured until the required application-specific BER is met. Evaluations show that the implementation area and the number of memory accesses are reduced. The results obtained from synthesizing basic operators of the proposed design on an FPGA show energy consumption experienced a saving of over 80 %.

TRUMP: Efficient and Flexible Realization of Medium Access Control Protocols for Wireless Networks

In order to cope with the increasing complexity of wireless networks, dynamic spectrum access, and varying application needs, fast and flexible reconfiguration of protocol stack is desired. Since Medium Access Control (MAC) layer plays a pivotal role in providing efficient spectrum sharing and utilization, rapid on-the-fly reconfigurability of MAC protocols is highly important. We have designed and implemented TRUMP: a Toolchain for RUntiMe Protocol realization. Based on the component-oriented design approach, TRUMP allows runtime realization, reconfiguration, and optimization of MAC layer according to the varying application requirements, spectral environmental, and network conditions. TRUMP, with a platform-independent MAC meta-language, also enables rapid MAC prototyping. In this article, we carry out a detailed performance evaluation of MAC schemes realized through TRUMP on WARP SDR platform. Our results indicate that TRUMP allows reconfiguration of MAC schemes in the order of a few microseconds, thus meeting the strict timeliness requirements of MAC processing. We also present application examples to highlight capabilities of TRUMP.

Racetrack Memory-Based Nonvolatile Storage Elements for Multicontext FPGAs

A multicontext field-programmable gate array (FPGA) is a solution to achieve fast run-time reconfiguration. However, SRAM-based multicontext FPGAs still suffer from high leakage power during sleep, slow power-ON speed, and excessive large memory area. Racetrack memory is one of the most promising resistive nonvolatile memories, with the advantages of low power, high density, and high speed. In this paper, we propose two racetrack memory-based nonvolatile storage elements (NVSEs) for multicontext FPGAs. One is the shifting-based NVSE (type-1) with the advantages of high density and low power. The other one is the address-based NVSE (type-2) with the advantages of high context switching speed and low context switching power. The versatile place and route simulation results show that the type-1 NVSE-based eight-context FPGA reduces the area, critical path delay, and the power of the SRAM-based eight-context FPGA by more than 68.1%, 22.8%, and 13%, respectively. The proposed type-2 NVSE-based FPGAs allow the contexts to be switched 4.46 times faster than the type-1 NVSE-based FPGAs. Both designs improve the FPGA power-ON speed by more than a million times. Compared with the conventional racetrack memory-based lookup table (LUT), the proposed racetrack memory-based LUT may reduce the total power by more than 25%.

PERFORMANCE ANALYSIS AND IMPLEMENTATION OF MODIFIED SDM BASED NOC FOR MPSOC ON SPARTAN6 FPGA

To meet todays demanding requirements lowpower consumption, high performance while maintaing flexibility and scalability, system-On-Chip will combine several number of processors cores and other IPs with network-On-chip. To implement NoC based MPSoC on an FPGA, NoCs should provide guaranteed services and be run-time reconfigurable. Current TDM and SDM based NoCs takes more area and would not support run-time reconfiguration. This paper presents modified spatial division multiplexing based NoC on FPGA, in this we have modified complex network interface and proposed flexible network interface and efficient SDM based NoC.This architecture explored feasibility of connection requirements from IP cores during run-time.