Racetrack Memory-Based Nonvolatile Storage Elements for Multicontext FPGAs

Abstract

A multicontext field-programmable gate array (FPGA) is a solution to achieve fast run-time reconfiguration. However, SRAM-based multicontext FPGAs still suffer from high leakage power during sleep, slow power-ON speed, and excessive large memory area. Racetrack memory is one of the most promising resistive nonvolatile memories, with the advantages of low power, high density, and high speed. In this paper, we propose two racetrack memory-based nonvolatile storage elements (NVSEs) for multicontext FPGAs. One is the shifting-based NVSE (type-1) with the advantages of high density and low power. The other one is the address-based NVSE (type-2) with the advantages of high context switching speed and low context switching power. The versatile place and route simulation results show that the type-1 NVSE-based eight-context FPGA reduces the area, critical path delay, and the power of the SRAM-based eight-context FPGA by more than 68.1%, 22.8%, and 13%, respectively. The proposed type-2 NVSE-based FPGAs allow the contexts to be switched 4.46 times faster than the type-1 NVSE-based FPGAs. Both designs improve the FPGA power-ON speed by more than a million times. Compared with the conventional racetrack memory-based lookup table (LUT), the proposed racetrack memory-based LUT may reduce the total power by more than 25%.