Router Buffer Research Articles

Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty

Due to limited on-chip caching, data-driven applications with large memory footprint encounter frequent cache misses. Such applications suffer from recurring miss penalty when they re-reference recently evicted cache blocks. To meet the worst-case performance requirements, Network-on-Chip (NoC) routers are provisioned with input port buffers. However, recent studies reveal that these buffers remain underutilised except during network congestion. Trace buffers are Design-for-Debug (DfD) hardware employed in NoC routers for post-silicon debug and validation. Nevertheless, they become non-functional once a design goes into production and remain in the routers left unused. In this article, we exploit the underutilised NoC router buffers and the unused trace buffers to store recently evicted cache blocks. While these blocks are stored in the buffers, future re-reference to these blocks can be replied from the NoC router. Such an opportunistic caching of evicted blocks in NoC routers significantly reduce the miss penalty. Experimental analysis shows that the proposed architectures can achieve up to 21 percent (16 percent on average) reduction in miss penalty and 19 percent (14 percent on average) improvement in overall system performance. While we have a negligible area and leakage power overhead of 2.58 and 3.94 percent, respectively, dynamic power reduces by 6.12 percent due to the improvement in performance.

Revising NoC in Future Multicore-Based Consumer Electronics for Performance

With the increasing demand for efficient data processing, the latest consumer electronics are powered by multi-core processors. Many applications that run on these devices expect minimum data access latency, where Network-on-Chip (NoC) plays a crucial role. However, NoC is found to be responsible for 60-75% of miss penalty. The objective of this article is to present a revised NoC communication framework that can possibly reduce the miss penalty. The proposed architecture orchestrates buffers of NoC routers as a victim cache to store evicted cache blocks. Future references to such stored blocks are replied from NoC routers which significantly reduces miss penalty and improves system performance. Minimising miss penalty by maximising NoC resource utilisation in these devices is a win-win situation.

FPGA friendly NoC simulation acceleration framework employing the hard blocks

A major role is played by Modeling and Simulation platforms in development of a new Network-on-Chip (NoC) architecture. The cycle accurate software simulators tend to become slow when simulating thousands of cores on a single chip. FPGAs have become the vehicle for simulation acceleration due to the properties of parallelism. Most of the state-of-the-art FPGA based NoC simulators utilize soft logic only for modeling the NoCs, leaving out the hard blocks to be unutilized. In this work, the FIFO Buffer and Crossbar switch functionalities of the NoC router have been embedded in the Block RAM (BRAMs) and the DSP48E1 slices with large multiplexer respectively. Employing the proposed techniques of mapping the NoC router components on the FPGA hard blocks, an NoC simulation acceleration framework based on the FPGA is presented in this work. A huge reduction in the use of the Configurable Logic Blocks (CLBs) has been observed when the FIFO buffer and Crossbar components of the NoC topology’s router micro-architecture are embedded in FPGA hard blocks. Our experimental results show that the topologies implemented employing the proposed FPGA friendly mapping of the NoC router components on the hard blocks consume 43.47% fewer LUTs and 41.66% fewer FFs than the topologies with CLB implementation. To optimize the latency of the NoC under consideration, a control unit called “buf_empty_checker” has been employed. A reduction in average latency has been observed compared to the CLB based topology implementation employing the proposed mapping. The proposed work consumes 10.88% fewer LUTs than the CONNECT NoC generation tool. Compared to DART, a reduction of 73.38% and 66.55% in LUTs and FFs has been observed with respect to the proposed work. The average packet latency of the proposed NoC architecture is 24.8% and 19.1% lesser than the CONNECT and DART architectures.

Multi-indicator Active Queue Management Method

A considerable number of applications are running over IP networks. This increased the contention on the network resource, which ultimately results in congestion. Active queue management (AQM) aims to reduce the serious consequences of network congestion in the router buffer and its negative effects on network performance. AQM methods implement different techniques in accordance with congestion indicators, such as queue length and average queue length. The performance of the network is evaluated using delay, loss, and throughput. The gap between congestion indicators and network performance measurements leads to the decline in network performance. In this study, delay and loss predictions are used as congestion indicators in a novel stochastic approach for AQM. The proposed method estimates the congestion in the router buffer and then uses the indicators to calculate the dropping probability, which is responsible for managing the router buffer. The experimental results, based on two sets of experiments, have shown that the proposed method outperformed the existing benchmark algorithms including RED, ERED and BLUE algorithms. For instance, in the first experiment, the proposed method resides in the third-place in terms of delay when compared to the benchmark algorithms. In addition, the proposed method outperformed the benchmark algorithms in terms of packet loss, packet dropping, and packet retransmission. Overall, the proposed method outperformed the benchmark algorithms because it preserves packet loss while maintaining reasonable queuing delay.

Weight Queue Dynamic Active Queue Management Algorithm

The current problem of packets generation and transformation around the world is router congestion, which then leads to a decline in the network performance in term of queuing delay (D) and packet loss (PL). The existing active queue management (AQM) algorithms do not optimize the network performance because these algorithms use static techniques for detecting and reacting to congestion at the router buffer. In this paper, a weight queue active queue management (WQDAQM) based on dynamic monitoring and reacting is proposed. Queue weight and the thresholds are dynamically adjusted based on the traffic load. WQDAQM controls the queue within the router buffer by stabilizing the queue weight between two thresholds dynamically. The WQDAQM algorithm is simulated and compared with the existing active queue management algorithms. The results reveal that the proposed method demonstrates better performance in terms mean queue length, D, PL, and dropping probability, compared to gentle random early detection (GRED), dynamic GRED, and stabilized dynamic GRED in both heavy or no-congestion cases. In detail, in a heavy congestion status, the proposed algorithm overperformed dynamic GRED (DGRED) by 13.3%, GRED by 19.2%, stabilized dynamic GRED (SDGRED) by 6.7% in term of mean queue length (mql). In terms of D in a heavy congestion status, the proposed algorithm overperformed DGRED by 13.3%, GRED by 19.3%, SDGRED by 6.3%. As for PL, the proposed algorithm overperformed DGRED by 15.5%, SDGRED by 19.8%, GRED by 86.3% in term of PL.

Novel flexible buffering architectures for 3D-NoCs

In the conventional router architecture of Network-on-Chips (NoCs), each input port employs a set of dedicated flit buffers to store incoming flits. This mechanism unevenly distributes flits among router buffers, which in turn leads to higher packet blocking rates and under-utilization of buffers. In this paper, we address this problem by proposing two novel buffering mechanisms and their corresponding architectures to share flit buffers among several ports of a router efficiently. Our first proposed mechanism is called Minimum-First buffering. This mechanism distributes flits among buffers of input ports based on the number of free buffer slots available in each port, giving priority to minimum occupied buffers. This approach increases the utilization of underutilized buffers by allowing them to store flits of other input ports. The second mechanism (so-called Inverse-Priority buffering) is a lighter yet efficient, flexible buffering technique. This mechanism employs a simple priority order for each buffer. According to our analysis, prioritizing specific ports over others balances the traffic loads between router buffers, and thus yields higher throughput. Both mechanisms lead to lower waiting times in the router and higher utilization in hardware resources. After studying all possible scenarios and analyzing corner cases, we have optimally designed two router architectures equipped with the proposed buffering mechanisms. Moreover, a hardware optimization technique is introduced to reduce the area overhead of the Minimum-First router architecture. The proposed architectures show significant improvements in the performance of 3D-NoCs in terms of the average network throughput and average delay as well as the total number of blocked packets compared to different state-of-the-art and baseline router architectures.

Network-Cognitive Traffic Control: A Fluidity-Aware On-Chip Communication

A novel network-on-chip (NoC) integrated congestion control and flow control scheme, called Network-Cognitive Traffic Control (NCogn.TC), is proposed. This scheme is cognizant of the fluidity levels in on-chip router buffers and it uses this measurement to prioritize the forwarding of flits in the buffers. This preferential forwarding policy is based on the observation that flits with higher levels of fluidity are likely to arrive at their destinations faster, because they may require fewer routing steps. By giving higher priority to forward flits in high-fluidity buffers, scarce buffer resources may be freed-up sooner in order to relieve on-going traffic congestion. In this work, a buffer cognition monitor is developed to rapidly estimate the buffer fluidity level. An integrated congestion control and flow control algorithm is proposed based on the estimated buffer fluidity level. Tested with both synthetic traffic patterns as well as industry benchmark traffic patterns, significant performance enhancement has been observed when the proposed Network-Cognitive Traffic Control is compared against conventional traffic control algorithms that only monitor the buffer fill level.

Congestion Control Mechanism Based on Dual Threshold DI-RED for WSNs

In wireless sensor networks (WSNs), traffic flow congestion can reduce network performance. We propose a congestion control method for WSNs that use a cache state with a dual threshold in the router buffer to control congestion. In addition, the congestion is controlled by the channel transmission state that is monitored by the queuing variation tendency and the transmission rate. Based on the active queue management mechanism, a dual threshold with the double index random early detection (DI-RED) model is established to improve network performance. We also present the congestion control algorithm of DI-RED model to ensure the perfect actualization. By solving the DI-RED model, a series of channel indicators is obtained, including packet loss rate, average queue length, delay and throughput. Simulation results show that the proposed DI-RED model is more stable and demonstrates better control, which can overcome the parameter sensitivity of the RED mechanism. The proposed model realises a reasonable tradeoff between network performance and packet dropping probability, which effectively avoids degraded network performance caused by pursuing a lower packet dropping probability. The results are important when selecting a congestion control mechanism and parameter settings for WSNs.

Efficient bypass in mesh and torus NoCs

Minimizing latency and power are key goals in the design of NoC routers. Different proposals combine lookahead routing and router bypass to skip the arbitration and buffering, reducing router delay. However, the conditions to use them requires completely empty buffers in the intermediate routers. This restricts the amount of flits that use the bypass pipeline especially at medium and high loads, increasing latency and power. This paper presents NEBB, Non-Empty Buffer Bypass, a mechanism that allows to bypass flits even if the buffers to bypass are not empty. The mechanism applies to wormhole and virtual-cut-through, each of them with different advantages. NEBB-Hybrid is proposed to employ the best flow control in each situation. The mechanism is extended to torus topologies, using FBFC and shared buffers. The proposals have been evaluated using Booksim, showing up to 75% reduction of the buffered flits for single-flit packets, which translates into latency and dynamic power reductions of up to 30% and 23% respectively. For bimodal traffic, these improvements are 20 and 21% respectively. Additionally, the bypass utilization is largely independent of the number of VCs when using shared buffers and very competitive with few private ones, allowing to simplify the allocation mechanisms.

Regional stabilization of TCP/AQM system with polytopic uncertainties and homogeneous segmented time delay

In this paper, new local stabilization analysis for TCP/AQM process based on segmented delay is proposed. The new approach consists in describing the time delay as a sum of homogeneous loads delays plus the variation of the queuing delay resulting from the made actions inside the router buffer. By employing an appropriate new Lyapunov–Krasovskii functional that depends on the upper bounds of the loads, new segmented delays dependent local stabilization conditions are proposed. Furthermore, new results concerning the unsymmetrical saturation input are obtained. Finally, the theory is experimented on NS 3, which proves that the proposed Segment Controller (SegCont) mechanism is strong and robust.

An Exponential Active Queue Management Method Based on Random Early Detection

Congestion is a key topic in computer networks that has been studied extensively by scholars due to its direct impact on a network’s performance. One of the extensively investigated congestion control techniques is random early detection (RED). To sustain RED’s performance to obtain the desired results, scholars usually tune the input parameters, especially the maximum packet dropping probability, into specific value(s). Unfortunately, setting up this parameter into these values leads to good, yet biased, performance results. In this paper, the RED-Exponential Technique (RED_E) is proposed to deal with this issue by dropping arriving packets in an exponential manner without utilizing the maximum packet dropping probability. Simulation tests aiming to contrast E_RED with other Active Queue Management (AQM) methods were conducted using different evaluation performance metrics including mean queue length (mql), throughput (T), average queuing delay (D), overflow packet loss probability (PL), and packet dropping probability (DP). The reported results showed that E_RED offered a marginally higher satisfactory performance with reference to mql and D than that found in common AQM methods in cases of heavy congestion. Moreover, RED_E compares well with the considered AQM methods with reference to the above evaluation performance measures using minimum threshold position (min threshold) at a router buffer.

Right buffer sizing matters: Some dynamical and statistical studies on Compound TCP

Large and unmanaged router buffers could lead to an increase in queuing delays in the Internet, which is a serious concern for network performance and quality of service. Our focus is to conduct a performance evaluation of Compound TCP (C-TCP), in a regime where the router buffer sizes are small (i.e., independent of the bandwidth-delay product), and the queue policy is Drop-Tail. In particular, we provide buffer sizing recommendations for high speed core routers fed by well multiplexed TCP controlled flows. For this, we consider two topologies: a single bottleneck and a multi-bottleneck topology, under different traffic scenarios. The first topology consists of a single bottleneck router, and the second consists of two distinct sets of TCP flows, regulated by two edge routers, feeding into a common core router. We focus on some key dynamical and statistical properties of the underlying system. From a dynamical perspective, we first develop fluid models. A local stability analysis for these models yields a key insight: buffer sizes need to be dimensioned carefully, and smaller buffers favour stability. We also highlight that larger Drop-Tail buffers, in addition to increasing latency, are prone to inducing limit cycles in the system dynamics. These limit cycles in turn induce synchronisation among the TCP flows, which then results in a loss of link utilisation. We then empirically analyse some statistical properties of the bottleneck queues. These statistical analyses serve to validate an important modelling assumption: that in the regime considered, each bottleneck queue may be reasonably well approximated as either an M∕M∕1∕B or an M∕D∕1∕B queue. We also highlight that smaller buffers, in addition to ensuring stability and low latency, would also yield reasonable system-wide performance, in terms of throughput and flow completion times.

Bus manufacturing workshop scheduling method with routing buffer

Aiming at solving the problem that the moving route is complicated and the scheduling is difficult in the routing buffer of the bus in the manufacturing workshop, a routing buffer mathematical programming model for bus manufacturing workshop is proposed. We design a moving approach for minimizing the total setup cost for moving in routing buffer. The framework and the solution ofthe optimization problem of such a bus manufacturing workshop scheduling with routing buffer arepresented. The evaluation results show that, comparing with the irregularly guided moving method, the proposed method can better guide the bus movement in routing buffer by reducing the total setup time of all buses processed at the next stage, and obtaining a better scheduling optimization solution with minimize maximum total completion time.

Bus manufacturing workshop scheduling method with routing buffer

Aiming at solving the problem that the moving route is complicated and the scheduling is difficult in the routing buffer of the bus in the manufacturing workshop, a routing buffer mathematical programming model for bus manufacturing workshop is proposed. We design a moving approach for minimising the total setup cost for moving in routing buffer. The framework and the solution of the optimisation problem of such a bus manufacturing workshop scheduling with routing buffer are presented. The evaluation results show that, compared with the irregularly guided moving method, the proposed method can provide a better guide line for the bus movement in the routing buffer by reducing the total setup time of all buses processed at the next stage, and a better scheduling optimisation solution with minimise maximum total completion time.

Design and performance analysis of link-by-link congestion avoidance algorithm

In this paper, a simple but new approach, namely link-by-link congestion avoidance (LbLCA) algorithm, which works at the network layer, has been proposed. LbLCA is a proactive congestion avoidance algorithm. It uses explicit feedback to prevent congestion to happen in the first place. The novelty of LbLCA is that no per flow information is required, which makes it more scalable. Based on the design philosophy and equations, sizing of various router buffers has been arrived at for different typical network topologies. Buffer sizes depend upon the mean arrival rate at router input and outgoing link capacities and are independent of round trip time (RTT) and the number of flows passing through the router. The buffer sizes determined using LbLCA design are validated using extensive NS2 simulations. The performance evaluation has been done using NS2 simulations on the typical network topologies. The performance comparison between TCP and LbLCA reveals that proposed LbLCA algorithm gives improved performance for the end-to-end delay and packet delivery ratio. LbLCA is impartial to all flows, as LbLCA works at network layer and therefore, cannot differentiate between flows.

Design and Performance Analysis of Link-by-Link Congestion Avoidance (LbLCA) Algorithm

In this paper, a simple but new approach, namely link-by-link congestion avoidance (LbLCA) algorithm, which works at the network layer, has been proposed. LbLCA is a proactive congestion avoidance algorithm. It uses explicit feedback to prevent congestion to happen in the first place. The novelty of LbLCA is that no per flow information is required, which makes it more scalable. Based on the design philosophy and equations, sizing of various router buffers has been arrived at for different typical network topologies. Buffer sizes depend upon the mean arrival rate at router input and outgoing link capacities and are independent of round trip time (RTT) and the number of flows passing through the router. The buffer sizes determined using LbLCA design are validated using extensive NS2 simulations. The performance evaluation has been done using NS2 simulations on the typical network topologies. The performance comparison between TCP and LbLCA reveals that proposed LbLCA algorithm gives improved performance for the end-to-end delay and packet delivery ratio. LbLCA is impartial to all flows, as LbLCA works at network layer and therefore, cannot differentiate between flows.

Exploration on Routing Configuration of HNoC With Intelligent On-Chip Resource Management

The Heterogeneous Network-on-Chip (HNoC) integrates CPU cores, Graphic Processing Unit (GPU) cores, last-level-cache and memory controllers. The heterogeneity of this architecture inevitably brings resource contention and energy shortage. In this work, we first study the impact of different capacity of router buffers on communication delay and energy consumption. After comprehensive evaluation with a spectrum of benchmarks with different characteristics, we reveal the implicit tradeoff between performance and energy consumption under different constrains of buffer resource. We further show that intelligently allocating more on-chip network buffer resources to compute-intensive nodes can significantly improve system performance. We introduce a runtime strategy that dynamically allocates network buffers to applications based on application characteristics. Our evaluation shows that our system reduces the communication delay by 55.47% on average, and reduces energy consumption of the system by 21% on average.

Controlling Delay at the Router Buffer using Modified Random Early Detection

Controlling Delay at the Router Buffer using Modified Random Early Detection

Sizing router buffers (redux)

The queueing delay faced by a packet is arguably the largest source of uncertainty during its journey. It therefore seems crucial that we understand how big the buffers should be in Internet routers. Our 2004 Sigcomm paper revisited the existing rule of thumb that a buffer should hold one bandwidth-delay product of packets. We claimed that for long-lived TCP flows, it could be reduced by √ N , where N is the number of active flows, potentially reducing the required buffers by well over 90% in Internet backbone routers. One might reasonably expect that such a result, which supports cheaper routers with smaller buffers, would be embraced by the ISP community. In this paper we revisit the result 15 years later, and explain where it has succeeded and failed to affect how buffers are sized.

Adaptive and Stable Delay Control for Combating Bufferbloat: Theory and Algorithms

In recent years, inexpensive memory has resulted in large router buffers installed in the Internet, leading to high queueing delay and delay variation. This phenomenon is recently termed “bufferbloat.” Active queue management (AQM) algorithms play an important role in combating bufferbloat, but none of them has been widely deployed due to complicated parameter tuning. Moreover, the parameters of AQM algorithms are usually fixed, making them difficult to adapt to changing network environments. In this paper, we propose a framework to adaptively and stably control queueing delay based on network conditions, so as to combat bufferbloat. Specifically, we use controlled delay (CoDel), a recently proposed AQM, in our framework. To the best of our knowledge, this is the first work that develops an analytical model for the CoDel system and derives necessary and sufficient conditions for its stability. Based on the stability analysis, we propose adaptive CoDel with interval tuning (ACoDel-IT) and adaptive CoDel with target and interval tuning (ACoDel-TIT) algorithms, to improve the system stability and performance by automatic parameter tuning. Extensive simulation results demonstrate that ACoDel-IT and ACoDel-TIT effectively stabilize queueing delay, whereas ACoDel-TIT further improves link utilization and reduces packet drops, compared to other representative AQM algorithms.