Abstract

A novel network-on-chip (NoC) integrated congestion control and flow control scheme, called Network-Cognitive Traffic Control (NCogn.TC), is proposed. This scheme is cognizant of the fluidity levels in on-chip router buffers and it uses this measurement to prioritize the forwarding of flits in the buffers. This preferential forwarding policy is based on the observation that flits with higher levels of fluidity are likely to arrive at their destinations faster, because they may require fewer routing steps. By giving higher priority to forward flits in high-fluidity buffers, scarce buffer resources may be freed-up sooner in order to relieve on-going traffic congestion. In this work, a buffer cognition monitor is developed to rapidly estimate the buffer fluidity level. An integrated congestion control and flow control algorithm is proposed based on the estimated buffer fluidity level. Tested with both synthetic traffic patterns as well as industry benchmark traffic patterns, significant performance enhancement has been observed when the proposed Network-Cognitive Traffic Control is compared against conventional traffic control algorithms that only monitor the buffer fill level.

Highlights

  • Network-on-Chip (NoC) is an emerging on-chip communication infrastructure [1] for on-chip communications in Multi-Processor System on Chip (MPSoC) [1] and Chip Multi-Processor (CMP) [2], platforms

  • Congestion Control (OE-buffer fill level (BFilL).CC) are compared with OE equipped with the Buffer Cognition level and the hybrid Congestion Control (OE-buffer cognition level (BCogL).CC), in order to validate the performance differences between applying the conventional BFilL and our proposed BCogL

  • Hybrid Congestion Control (OE-BFilL.CC) are compared with OE equipped with the Buffer Cognition level and the hybrid Congestion Control (OE-BCogL.CC), in order to validate the performance differences between applying the conventional BFilL and our proposed BCogL

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Summary

Introduction

Network-on-Chip (NoC) is an emerging on-chip communication infrastructure [1] for on-chip communications in Multi-Processor System on Chip (MPSoC) [1] and Chip Multi-Processor (CMP) [2], platforms. Mehranzadeh et al [9], designed a congestion-aware output selection strategy based on calculations of congestion levels of neighboring nodes, Giroudot et al [10], realized a buffer-aware worst-case timing analysis of wormhole routers with different buffer sizes when consecutive-packet queuing occurs. These cognitive network traffic control schemes address isolated issues in NoC communication. There is yet an integrated approach to consider routing, congestion control, and flow control jointly to enhance performance of NoC communication.

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