Robust Circuit Research Articles

A Comprehensive Review on Automation-based Sizing Techniques for Analog IC Design

Analog integrated circuits are present in most electronic systems. They must be designed carefully in order to achieve the required performance specifications. Although almost half of the design effort in a chip is spent in analog modules, there are not yet a consolidated industry of analog design automation tools capable to fully synthesize analog circuits in a fast and generic way. This is due the fact that automatic or semi-automatic design tools have to deal with high design complexity, which includes several specifications and design variables. A lot of research effort have been done in this field in the past years, proposing methods for automating parts of the design flow, from topology selection to devices sizing and layout generation. This paper presents a review of the state-of-the art in analog design automation methods, focusing on techniques and algorithms used to size robust circuits while efficiently exploring the design space.

A High-Efficiency Protection Circuit Integrating Semi-Soft Switching and Voltage Limiting Functions for Solid-State Switch Applications

Despite the high performance of high-voltage direct current circuit breaker (CB) technology, its high cost restricts its further development. Thus, this article proposes a high-efficiency protection circuit for solid-state switches (SSs) that integrates semisoft switching and voltage limiting functions. The protection circuit also does not resonate with the system inductance which in turn does not affect the reclosing operation of the CB. The novel SS scheme reduces the cost and simplifies the layout of the SS. The special constraints for the parameter design of power electronics, gaps, and metal oxide varistors (MOVs) are proposed in this article for the first time, and a parameters design method that solves the transient power shock and voltage spike problems during the large current breaking process under multiple constraints is formed. Finally, an SS prototype is developed to verify the feasibility and the strong surge and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> ability of the novel SS and to test the robustness of the series-connected gapped-MOV circuits.

Transistor-Level Radiation Hardening by Design Techniques in Complex Gates

Single Event Transients (SETs) have become a major reliability concern for integrated circuits used in critical applications. Research to improve the radiation robustness of digital circuits has been conducted, assessing all abstraction levels (from the device up to the system). This study evaluates transistor-level radiation-hardened techniques in combinational logic, such as transistor folding, sizing and reordering. In addition, the efficiency of using supergates, including series-parallel and non-series-parallel CMOS structures, to harden the combinational logic is discussed. The dependence of input signals probability on a logic cell susceptibility to SET is assessed. Moreover, a new concept of electrical masking is introduced. The robustness of the investigated logic cells was evaluated regarding their SET rate. The CREME96 tool was used to generate the SET rates, and an electrical model was used to perform particle hit simulations. Obtained results have indicated that modifying the structure of logic gates can substantially improve circuit robustness without necessarily worsening its performance. Besides, using supergates in combinational logic design has demonstrated to be a promising hardening strategy. The most robust supergate implementation of a five-input logic function provided up to [Formula: see text] SET rate reduction regarding an approach based on standard cells, along with lower critical delay ([Formula: see text]) and average power ([Formula: see text]).

Strong photon–magnon coupling at microwave and millimeter-wave frequencies in planar hybrid circuits

Photon–magnon hybrid systems have potential applications in modern information processing technologies. Although planar hybrid circuits based on split ring resonators have shown strong coherent photon–magnon coupling, none of those operates at millimeter-wave frequencies. With specially designed electric-field-coupled resonators, strong coupling between resonator modes and ferromagnetic resonance modes (either in-plane or out-of-plane) was experimentally observed in two circuits working at 4.1 and 30 GHz. Their dynamics were well described by quantum models. The miniature, integrable, and physically robust circuits pave a way for planar photon–magnon hybrid systems at even higher frequencies, demonstrating the possibility to integrate magnon-based systems with millimeter-wave devices.

Repeated applications of high potassium elicit long-term changes in a motor circuit from the crab, Cancer borealis

SummaryWe examined the effects of altered extracellular potassium concentration on the output of the well-studied pyloric circuit in the crab, Cancer borealis. Pyloric neurons initially become quiescent, then recover spiking and bursting activity in high potassium saline (2.5x[K+]). These changes in circuit robustness are maintained after the perturbation is removed; pyloric neurons are more robust to subsequent potassium perturbations even after several hours of wash in control saline. Despite this long-term “memory” of the stimulus history, we found no differences in neuronal activity in control saline. The circuit’s adaptation is erased by both low potassium saline (0.4x[K+]) and direct hyperpolarizing current. Initial sensitivity of PD neurons to high potassium saline also varies seasonally, indicating that changes in robustness may reflect natural changes in circuit states. Thus, perturbation, followed by recovery of normal activity, can hide cryptic changes in neuronal properties that are only revealed by subsequent challenges.

A Critical Review on Reliability and Short Circuit Robustness of Silicon Carbide Power MOSFETs

A Critical Review on Reliability and Short Circuit Robustness of Silicon Carbide Power MOSFETs

A low-power high-quality CMOS image sensor using 1.5 V 4T pinned photodiode and dual-CDS column-parallel single-slope ADC

This paper presents a low-power high-quality CMOS image sensor (CIS) using 1.5 V 4T pinned photodiode (4T-PPD) and dual correlated double sampling (dual-CDS) column-parallel single-slope ADC. A five-finger shaped pixel layer is proposed to solve image lag caused by low-voltage 4T-PPD. Dual-CDS is used to reduce random noise and the nonuniformity between columns. Dual-mode counting method is proposed to improve circuit robustness. A prototype sensor was fabricated using a 0.11 µm CMOS process. Measurement results show that the lag of the five-finger shaped pixel is reduced by 80% compared with the conventional rectangular pixel, the chip power consumption is only 36 mW, the dynamic range is 67.3 dB, the random noise is only 1.55 e– rms, and the figure-of-merit is only 1.98 e–·nJ, thus realizing low-power and high-quality imaging.

(Invited) Breakthrough Avalanche and Short Circuit Robustness in Vertical GaN Power Devices

After decades of relentless efforts, GaN power devices, specifically, the lateral GaN high-electron mobility transistor (HEMT), have been commercialized in the 15-650 V classes. Owing to GaN’s competitive physical properties over Si and SiC for power electronics, GaN HEMTs allow for higher switching frequency and therefore, have already seen wide adoptions in fast chargers, wireless charging, data centers, and electrified transportation. Despite the success of lateral GaN HEMTs, a vertical device structure is usually believed to be more favorable for high-voltage, high-power devices. In the last few years, with the advent and maturity of large-diameter, low-dislocation GaN wafers on freestanding GaN substrates, a new generation of vertical GaN power devices have been developed to extend GaN’s application space beyond 650 V. Very recently, several industrial vertical GaN devices in the voltage classes of 1.2-1.7 kV have been demonstrated, which are close to commercialization.This presentation will review the key advancements in vertical GaN power devices in the past decade, with a focus on the device technologies that are being commercialized, and provide a prospective for research and development in the next decade. The devices to be covered will include two-terminal power rectifiers including the p-n diodes, Schottky barrier diodes, junction barrier Schottky diodes, and trench MIS/MOS barrier Schottky diodes. The transistors will include the trench and planar MOSFETs, current-aperture vertical electron transistors, fin-channel MOSFETs, and fin-channel JFETs. Particular emphasis will be on large-area rectifiers and transistors with a device performance superior to similarly-rated Si and SiC transistors. The newly demonstrated avalanche and short-circuit robustness in vertical GaN devices, which are lacking in lateral GaN HEMTs, as well as their underlying device physics, will also be introduced. The presentation will be concluded by a discussion of current challenges and future application spaces of vertical GaN devices, as well as emerging vertical GaN devices (e.g., superjunction) under development.

Circuit formation in the adult brain.

Neurons in the mammalian central nervous system display an enormous capacity for circuit formation during development but not later in life. In principle, new circuits could be also formed in adult brain, but the absence of the developmental milieu and the presence of growth inhibition and hundreds of working circuits are generally viewed as unsupportive for such a process. Here, we bring together evidence from different areas of neuroscience—such as neurological disorders, adult‐brain neurogenesis, innate behaviours, cell grafting, and in vivo cell reprogramming—which demonstrates robust circuit formation in adult brain. In some cases, adult‐brain rewiring is ongoing and required for certain types of behaviour and memory, while other cases show significant promise for brain repair in disease models. Together, these examples highlight that the adult brain has higher capacity for structural plasticity than previously recognized. Understanding the underlying mechanisms behind this retained plasticity has the potential to advance basic knowledge regarding the molecular organization of synaptic circuits and could herald a new era of neural circuit engineering for therapeutic repair.

Clocked molecular quantum-dot cellular automata circuits tolerate unwanted external electric fields

Quantum-dot cellular automata (QCA) may provide low-power, general-purpose computing in the post-CMOS era. A molecular implementation of QCA features nanometer-scale devices and may support ∼THz switching speeds at room-temperature. Here, we explore the ability of molecular QCA circuits to tolerate unwanted applied electric fields, which may come from a variety of sources. One likely source of strong unwanted electric fields may be electrodes recently proposed for the write-in of classical bits to molecular QCA input circuits. Previous models have shown that the input circuits are sensitive to the applied field, and a coupled QCA wire can successfully transfer the input bit to downstream circuits despite strong applied fields. However, the ability of other QCA circuits to tolerate an applied field has not yet been demonstrated. Here, we study the robustness of various QCA circuits by calculating their ground state responses in the presence of an applied field. To do this, a circuit is built from several QCA molecules, each described as a two-state system. A circuit Hamiltonian is formed and diagonalized. All pairwise interactions between cells are considered, along with all correlations. An examination of the ground state shows that these QCA circuits may indeed tolerate strong unwanted electric fields. We also show that circuit immunity to the dominant unwanted field component may be obtained by choosing the orientation of constituent molecules. This suggests that relatively large electrodes used for bit write-in to molecular QCA need not disrupt the operation of nearby QCA circuits. The circuits may tolerate significant electric fields from other sources as well.

Improvement of the low gray-level expression using hybrid pulse width modulation and pulse amplitude modulation driving method for a micro light-emitting diode pixel circuit

A novel hybrid pulse width modulation (PWM) and pulse amplitude modulation (PAM) (HPP) driving method is proposed for improving the low gray-level expression of a micro light-emitting diode (µLED) display. At the high and middle gray-levels, PWM is adopted in order to suppress the wavelength shift of µLEDs. At the low gray-level, PAM is applied when the emission time and current of µLEDs simultaneously decrease. The HPP driving method is simulated by using a simplified p-type low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT)-based µLED pixel circuit. HPP driving exhibits stable PWM and PAM operations. Furthermore, HPP driving guarantees a data voltage range approximately 14 times larger than PWM driving, thus resulting in a robust operation with a maximum error rate of 3.83% under data signal distortion. Consequently, the µLED pixel circuit adopting HPP driving improves the low gray-level expression and demonstrates a robust circuit operation.

Layout based radiation hardening techniques against single-event transient

The single-event transient (SET) is regarded as one of the critical reliability issues for the soft errors in modern circuit designs, especially at the advanced technology node. To improve the SET robustness of circuits applied in the space environment, two kinds of layout-based radiation hardening techniques, namely split active area (SAA), gapless well and source (GWS), are proposed to reduce the charge collection efficiency from vertical and horizontal direction respectively. The hardening efficiency of different layout configurations is investigated by TCAD simulations and the underlying reasons for pulse width mitigation of SET are elaborated. The results indicate the combination of the two layout techniques is highly recommended in the construction of hardened standard cell library.

Breakthrough Short Circuit Robustness Demonstrated in Vertical GaN Fin JFET

Insufficient short-circuit (SC) robustness of currently commercial GaN power devices, i.e., the high electron mobility transistors (HEMTs), is a key roadblock for their applications in automotive powertrains. At a 400 V bus voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BUS</sub> ), the SC withstanding time ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SC</sub> ) of commercial GaN HEMTs is typically below 1 μs, far below the usual system requirement (>10 μs). This letter presents breakthrough short-circuit capability in a vertical GaN fin-channel junction-gate field-effect transistor (Fin-JFET). The Fin-JFET is normally <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> with a 0.7 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> specific <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -resistance and 800 V avalanche breakdown voltage (BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AVA</sub> ) at the room temperature. The gate driver in the short-circuit test was designed to be identical to that in device switching applications. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SC</sub> of GaN Fin-JFETs was measured to be 30.5 μs at a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BUS</sub> of 400 V, 17.0 μs at 600 V, and 11.6 μs at 800 V, all among the longest reported for 600–700 V normally <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> transistors. In addition, GaN Fin-JFETs failed open in these tests and retained BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AVA</sub> after failure, which is highly desirable for system applications. In the repetitive 10 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> s, 400 V short-circuit tests, GaN Fin-JFETs showed no degradation after 30 000 cycles. Furthermore, to the best of our knowledge, this is the first report of a power transistor with good short-circuit ruggedness at a bus voltage close to its BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AVA</sub> . The underlying mechanism is the unique avalanche-through-fin in the Fin-JFET, which is validated by mixed-mode TCAD simulations and unclamped inductive switching tests. These results reveal the inherent ruggedness of GaN Fin-JFETs in the concurrent presence of short-circuit and overvoltage in power electronics systems.

Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design

The commercial success of silicon carbide (SiC) diodes and MOSFETs for the automotive industry has led many in the field to begin developing ultra-high voltage (UHV) SiC insulated gate bipolar transistors (IGBTs), rated from 6 kV to 30 kV, for future grid conversion applications. Despite this early interest, there has been little work conducted on the optimal layout for the SiC IGBT, most early work seeking to overcome difficulties in fabricating the devices without a P+ substrate. In this paper, numerical TCAD simulations are used to examine the link between the carrier lifetime of SiC IGBTs and their short circuit capability. For the planar devices, simulations show that increasing carrier lifetime from 1 to 10 μs, has not only a profound effect reducing on-state losses, but also increases short circuit withstand time (SCWT) by 39%. Two retrograde p-well designs are also investigated, the optimal device for SCWT having a 100 nm channel region of 5×1016 cm-3, with this increasing to a peak value of 2×1018 cm-3, in a 700 nm region beneath the channel.

(Invited) Breakthrough Avalanche and Short Circuit Robustness in Vertical GaN Power Devices

Power devices are highly desirable to possess excellent avalanche and short-circuit (or surge-current) robustness for numerous power electronics applications like automotive powertrains, electric grids, motor drives, among many others. Current commercial GaN power device, the lateral GaN high-electron-mobility transistor (HEMT), is known to have no avalanche capability and very limited short-circuit robustness. These limitations have become a roadblock for penetration of GaN devices in many industrial power applications. Recently, through collaborations with NexGen Power Systems (NexGen), Inc., we have demonstrated breakthrough avalanche, surge-current and short-circuit robustness in NexGen’s vertical GaN p-n diodes and fin-shape junction-gate field-effect-transistors (Fin-JFETs). These large-area GaN diodes and Fin-JFETs were manufactured in NexGen’s 100 mm GaN-on-GaN fab. The demonstrated avalanche, surge-current and short-circuit capabilities are comparable or even superior to Si and SiC power devices. Additionally, vertical GaN Fin-JFETs were found to fail to open-circuit under avalanche and short-circuit conditions, which is highly desirable for the system safety. This talk reviews the key robustness results of vertical GaN power devices and unveils the enabling device physics. Fundamentally, these results signify that, in contrast to some popular belief, GaN devices with appropriate designs can achieve excellent robustness and thereby encounter no barriers for applications in electric vehicles, grids, renewable processing, and industrial motor drives.

Neuromorphic Silicon Photonics and Hardware-Aware Deep Learning for High-Speed Inference

The relentless growth of Artificial Intelligence (AI) workloads has fueled the drive towards non-Von Neuman architectures and custom computing hardware. Neuromorphic photonic engines aspire to synergize the low-power and high-bandwidth credentials of light-based deployments with novel architectures, towards surpassing the computing performance of their electronic counterparts. In this paper, we review recent progress in integrated photonic neuromorphic architectures and analyze the architectural and photonic hardware-based factors that limit their performance. Subsequently, we present our approach towards transforming silicon coherent neuromorphic layouts into high-speed and high-accuracy Deep Learning (DL) engines by combining robust architectures with hardware-aware DL training. Circuit robustness is ensured through a crossbar layout that circumvents insertion loss and fidelity constraints of state-of-the-art linear optical designs. Concurrently, we employ DL training models adapted to the underlying photonic hardware, incorporating noise- and bandwidth-limitations together with the supported activation function directly into Neural Network (NN) training. We validate experimentally the high-speed and high-accuracy advantages of hardware-aware DL models when combined with robust architectures through a SiPho prototype implementing a single column of a 4:4 photonic crossbar. This was utilized as the pen-ultimate hidden layer of a NN, revealing up to 5.93% accuracy improvement at 5GMAC/sec/axon when noise-aware training is enforced and allowing accuracies of 99.15% and 79.8% for the MNIST and CIFAR-10 classification tasks. Channel-aware training was then demonstrated by integrating the frequency response of the photonic hardware in NN training, with its experimental validation with the MNIST dataset revealing an accuracy increase of 12.93% at a record-high rate of 25GMAC/sec/axon.

PERSIST platform provides programmable RNA regulation using CRISPR endoRNases

Regulated transgene expression is an integral component of gene therapies, cell therapies and biomanufacturing. However, transcription factor-based regulation, upon which most applications are based, suffers from complications such as epigenetic silencing that limit expression longevity and reliability. Constitutive transgene transcription paired with post-transcriptional gene regulation could combat silencing, but few such RNA- or protein-level platforms exist. Here we develop an RNA-regulation platform we call “PERSIST" which consists of nine CRISPR-specific endoRNases as RNA-level activators and repressors as well as modular OFF- and ON-switch regulatory motifs. We show that PERSIST-regulated transgenes exhibit strong OFF and ON responses, resist silencing for at least two months, and can be readily layered to construct cascades, logic functions, switches and other sophisticated circuit topologies. The orthogonal, modular and composable nature of this platform as well as the ease in constructing robust and predictable gene circuits promises myriad applications in gene and cell therapies.

Printable logic circuits comprising self-assembled protein complexes

This paper describes the fabrication of digital logic circuits comprising resistors and diodes made from protein complexes and wired together using printed liquid metal electrodes. These resistors and diodes exhibit temperature-independent charge-transport over a distance of approximately 10 nm and require no encapsulation or special handling. The function of the protein complexes is determined entirely by self-assembly. When induced to self-assembly into anisotropic monolayers, the collective action of the aligned dipole moments increases the electrical conductivity of the ensemble in one direction and decreases it in the other. When induced to self-assemble into isotropic monolayers, the dipole moments are randomized and the electrical conductivity is approximately equal in both directions. We demonstrate the robustness and utility of these all-protein logic circuits by constructing pulse modulators based on AND and OR logic gates that function nearly identically to simulated circuits. These results show that digital circuits with useful functionality can be derived from readily obtainable biomolecules using simple, straightforward fabrication techniques that exploit molecular self-assembly, realizing one of the primary goals of molecular electronics.

Schmitt Trigger Designs Using Domino Logic Style

The advancements in the VLSI regime at lower technology node necessitate robust circuit design. Schmitt trigger design using domino logic style exhibit better hysteresis, higher noise margin, and reduced power consumption while compared to static CMOS Schmitt trigger design. This paper proposes three different Schmitt trigger designs based on domino logic style which produces a stable output with increased robustness against noise. The evaluation of dynamic logic-based Schmitt trigger using only NMOS transistors makes high speed operation feasible with reduced power consumption and increased hysteresis. The design, simulation, and analysis of the circuits are performed using Cadence Virtuoso using GPDK 180 nm technology library.

Prediction-error neurons in circuits with multiple neuron types: Formation, refinement, and functional implications

SignificanceAn influential idea in neuroscience is that neural circuits do not only passively process sensory information but rather actively compare them with predictions thereof. A core element of this comparison is prediction-error neurons, the activity of which only changes upon mismatches between actual and predicted sensory stimuli. While it has been shown that these prediction-error neurons come in different variants, it is largely unresolved how they are simultaneously formed and shaped by highly interconnected neural networks. By using a computational model, we study the circuit-level mechanisms that give rise to different variants of prediction-error neurons. Our results shed light on the formation, refinement, and robustness of prediction-error circuits, an important step toward a better understanding of predictive processing.