RLC Interconnect Research Articles

Accelerated Simulation of Passive Analog Circuits Over GPU Using Explicit Integration Methods

Analog circuits composed by large number of nodes in a tightly coupled structure pose significant challenges due to their prohibitive CPU simulation time. This work describes a method to speed up the simulation of such circuits by means of the combination of space state formulation of circuit equations with explicit integration methods parallelized over a many-core processor such as a GPU. Although stability of explicit techniques require smaller integration steps compared to implicit methods, the proposed method employs a fast estimate of the maximum allowed step size to guarantee numerical stability, which yields a shorter simulation time for increasing complexity circuit architectures. Moreover, the proposed technique can be straightforward parallelized on a many core architecture. The proposed method is demonstrated with two examples using constant and variable coefficients respectively: an RLC interconnect and a MOS-C network to perform Gaussian filtering of medium resolution images. The results obtained have been compared to a parallel version of SPICE and show improvements up to two orders of magnitude for transient simulations depending of the circuit size.

Design of Global RLC Interconnect Circuit with Analytical Delay Model

Background: With the advancement in technology nodes and scaling trends, the majority of the device performance depends upon the interconnections made between two or more devices. With these scaling trends, frequency plays a vital role. As the technology decreases, frequency tends to rise to giga-hertz. This increase in frequency gives rise to inductance parameters in the interconnect circuits. For long wires, the inductive impedance can become comparable to the resistive component due to which performance degradation can be observed along with overshoot and crosstalk issues that can no longer be ignored. Method: This article aims to examine the delay model and reconstruct an interconnect circuit that serves as a transmission line, ranging in length from 1 mm to 10 mm. Result: By keeping the frequency high, low voltage and rise/ fall time, performance parameters such as delay, power consumption, and overshoot are observed. Conclusion: The interconnect structure is compared with another state-of-the-art technique.

Energy Optimization for RC and RLC Interconnect Design in Low Power VLSI

Background: The global RC interconnects have become the controlling parameter for a circuit’s performance. But with the decrease in technology, an increase in resistance has become prominent. This increase further directly affects the performance of the system by increasing the performance parameters of the circuit like delay and power consumption. To resolve this issue and to be compatible with Internet of Things (IoT) applications, the interconnect circuits are required to be high speed with less heat generation. Methods: In this paper, a new RC and RLC interconnect circuit design was proposed for 45 nm technology to enhance the performance parameters. Furthermore, the RC interconnect design was simulated for lumped and distributed networks. The parasitic component values (resistance, inductance, and capacitance) are evaluated using PTM technology. Results: The proposed interconnect circuit's resistance value decreased by a factor of 4, but the capacitance remains the same. Furthermore, power consumption and delay values were attained. An overall comparison was done between RC and RLC networks. Conclusion: 63.13% power improvement and 24.87% delay improvement were observed in the RLC network over RC distributed network.

WITHDRAWN: Dynamic switching analysis of coupled RLC interconnects with physical and environmental variations

Abstract With continuous downscaling of integrated circuits into deep submicron and nanometer regime, operating at high frequencies, it has become most important to evaluate the reliability and efficiency of on-chip interconnects. The study of device and dynamic variations on dynamic crosstalk in inductive coupled interconnect wires is discussed in this paper. It analyses and studies the effect of driver size, interconnect length, supply voltage and temperature on the coupled interconnect lines. In the analysis, single and cascaded repeaters are used to drive the coupled interconnect lines. For local interconnects, as the driver size increases from 1X to 4X, the propagation delay decreases by 70.9% and the power dissipation increases by 5.75%. For global interconnects, as length of the interconnect increases from 1 mm to 2.5 mm, power dissipation and propagation delay are increased by 56.77% and 51.93% respectively. Analysis of variation of supply voltage and operating temperature is also carried out in this work. The analysis is carried out using geometric dimensions and the impedance parameters of copper interconnect extracted from PTM models for 45 nm CMOS technology node.

High speed RLC equivalent RC delay model using normalized asymptotic function for global VLSI interconnects

This work proposes a mathematical delay models for global VLSI interconnects using normalized asymptotic value of characteristic impedance of RLC interconnected line. In the proposed Model (R0C0) the delay of RLC interconnects line is formulated by incorporating the line inductance in terms of effective impedance. The earlier simple RC interconnect models results in a significant error in delay estimation in long interconnects. Due to this analogy the non-ideal effect of inductive behaviour at high frequencies and scaled technologies such as ringing, spikes overshoot and undershoot can be suppressed. The dominance of inductance effect is optimized by Simulative Sweep Analysis Techniques (SSAT). Accuracy is verified by analytical and SPICE simulation results. Step response analysis of the proposed model is validated with the existing literature and found to be superior. Using this approach the results for both the signaling technique i.e. voltage and current mode signaling are found in close agreement between analytical and simulation for long interconnect lines.

Modeling the impact of fundamental and quantum resistance on the performance of SWCNT‐based RLC interconnects

AbstractAn analytical interconnect model for single‐walled carbon nanotube (SWCNT) interconnects is proposed using Fourier method. Nonapproximated transfer function of the RLC SWCNT interconnect is modeled. The effect of fundamental and quantum resistance of SWCNT is incorporated in the transfer function. The propagation delay and overshoot/undershoot voltages are computed using Fourier series technique for SWCNT interconnects. Further, the effect of inductance that is prominent in CNTs is shown in terms of increased number of harmonics. Comparative analysis is carried out for SWCNT and Cu interconnects using MATLAB and SPICE at 65‐nm technology node for various performance parameters. Good accuracy is observed between the analytical and simulated results.

FDTD Modeling with Passive Shielding for Crosstalk Reduction in Coupled RLC Interconnects

This paper presents passive shielding technique for crosstalk noise and delay reduction in resistive driven RLC interconnect. FDTD technique is used for modeling proposed geometry. The worst case delay and noise induced due to crosstalk in passive shielded interconnects are compared with unshielded lines and is validated using HSPICE simulations for 32nm global interconnects. From the results it has been demonstrated that the proposed model results and HSPICE simulations differ by 8% and by using proposed geometry crosstalk noise and delay has come down by 90% and 52% when compared to unshielded line.

FDTD modeling for Crosstalk Reduction in Coupled RLC Interconnects with Active Shielding

This paper presents efficient geometry for crosstalk noise and delay reduction using Active shielding in RLC interconnects with resistive drivers .FDTD modeling has been used for proposed geometry and is validated by HSPICE simulations for 32nm global interconnects .From the results it has been verified that the proposed model results and HSPICE simulations differ by 5% . From the outcomes it has been confirmed that the proposed model outcomes and HSPICE outcomes differ by 5% and by using proposed geometry crosstalk noise and delay has come down by 73% and 60% when compared to unshielded line.

Buffer insertion for delay minimization in RLC interconnects using cuckoo optimization algorithm

In this paper, cuckoo optimization algorithm (COA) as an efficient evolutionary algorithm is used for buffer insertion in digital circuits. Application of the COA to real problems and some benchmark functions has proven its capability of dealing with difficult optimization problems and shown its superiority in fast convergence and global optima achievement. The aim of the work is to reduce the propagation delay in resistance–inductance–capacitance (RLC) interconnects. Furthermore, inductance effects on optimal number and size of buffer are investigated. This work is performed in two case studies. Buffer insertion in RLC lines is done in case study-I. Buffer insertion in tree structured inductive interconnects is dealt in case study-II. The COA results show the considerable reduction in the propagation delay. Maximum percentage of reduction in delay is 59.78% for line, 67.67% for balanced tree and 63.75% for unbalanced tree respectively. Also, optimal area (size and number of buffers) is another result of paper that can lead to economical number of chips.

The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits**Project supported by the Guangdong Provincial Natural Science Foundation of China (No. 2014A030313441), the Guangzhou Science and Technology Project (No. 201510010169), the Guangdong Province Science and Technology Project (No. 2016B090918071), and the National Natural Science Foundation of China (No. 61072028).

With the continuous advancement of semiconductor technology, the interconnects crosstalk has had a great influence on the performances of VLSI circuits. To date, most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed. First of all, an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes. The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model. Secondly, the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique and ABCD parameter matrix approach at local level, intermediate level and global level, respectively. Moreover, the experimental results show that the CMS interconnects have lesser noise peak, noise width and noise amplitude than the VMS interconnects in the same cases, and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits. It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system.

Analytical Models of High-Speed RLC Interconnect Delay for Complex and Real Poles

Continuous shrinking of the size of CMOS technology leads to extremely fast devices, but the resulting interconnect structures impose so many parasitic effects that the advantage of extremely scaled and ultrahigh-speed transistors would be completely overshadowed if appropriate remedial steps are not taken. This requires an accurate and efficient estimation of interconnect parasitics and analysis of their impact on integrated circuit performance. This paper proposes a new delay model for RLC interconnect networks in CMOS technology based on a second order approximate transfer function. The proposed modeling approach includes all possible scenarios (complex poles, real poles, and double poles) in the interconnect model. Simulation results show that the proposed delay model is almost independent of the ratio of ${V}_{\mathrm { {out}}} / V_{\mathrm { {in}}}$ , and the driver resistance has significant impact on the delay. The simulation results also show that the real pole model provides better accuracy and is much faster than the complex pole model. This observation would help to optimize the values of interconnect parasitics for faster operation.

Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit

The 1-bit adder circuits are schematized using pass transistor logic (PTL) technique, that’s optimized by the Shannon expansion theorem. The proposed 32bit carry increment adder (CIA) circuit is designed by bit slice method. The CIA adder layout gives tremendous change compared to existing author results. The proposed circuit achieved better performance on power consumption, speed, throughput, and area. The 32-bit adder circuits are implemented in various types of 1-bit adder cells, such as Shannon, Mixed-Shannon and MCIT-7T. Furthermore, the 32-bit CIA adder layout is furtherly investigated for RLC interconnect parameter such as capacitive impedance, inductive impedance, power factor sin ϕ, tan ϕ for applying frequency. The 32bit adder circuit acts in a better way than existing circuits in terms of power dissipation, delay, throughput, latency, power factor, sin ϕ and tan ϕ.

Analysis of propagation delay and repeater insertion in single-walled carbon nanotube bundle interconnects

A new closed-form expression of 50% propagation delay for distributed RLC interconnects is proposed using the multivariable curve fitting method, with a maximum error of 4% with respect to SPICE results. Then accurate closed-form solutions for the optimum repeater number and size to minimize the propagation delay are further derived. The performance of single-walled carbon nanotube (SWCNT) bundle interconnects is evaluated using the proposed models in the intermediate and global levels at the 22- and 32-nm technology nodes, and compared against traditional Cu interconnects. It is shown that the performance of SWCNT bundle interconnects in propagation delay can outperform Cu interconnects, and the improvement will be enhanced with technology scaling and wire length increasing. On the other hand, the propagation delay of SWCNT bundle interconnects is super-linearly dependent on the wire length similar to Cu interconnects, indicating that the method of repeater insertion to reduce the propagation delay can also apply to SWCNT bundle interconnects. The results shown that repeater insertion can really reduce the propagation delay of SWCNT bundle interconnects effectively, and the optimum repeater number is much smaller than that of Cu interconnects.

Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects

This paper presents novel methods for modeling and analysis of on-chip Single and H-tree distributed resistance inductance capacitance interconnects. The matrix pade-type approximation and scaling and squaring methods are employed for the numerical estimation of delay in single interconnect, and H-tree interconnects. The proposed models, which are based on these methods, provide rational function approximation for obtaining a passive interconnect model. Multiple single input single output model approximated transfer functions are developed for H-tree interconnects structure. With the equivalent reduced order lossy interconnect transfer functions, finite ramp responses are obtained, and line delay is estimated for various line lengths, input ramp rise times, source resistances, parasitic capacitances and load capacitances. In order to demonstrate the accuracy of proposed models, the estimated 50 % delay values are compared with the standard HSPICE W-element model and are found to be in good agreement. The proposed models worst case 50 % delay errors of single interconnect are 0.27 and 0.24 % respectively, while the worst case 50 % delay errors of H-tree structure are 5.73 and 3.94 % respectively.

Analytical Solutions for Distributed Interconnect Models—Part II: Arbitrary Input Response and Multicoupled Lines

In this paper, a new method is presented to calculate the exact analytical solution of distributed RC , LC , and RLC interconnects with a random input at an arbitrary point through the line. The proposed method, based on a modified Duhamel theorem, is used to calculate the time-domain transient response of the initially conditioned interconnects. This method is applied to a line driven by ramp and exponential inputs. The new analytical solutions are expressed as an infinite summation of sinusoidal terms. However, a negligible worst case error of <1% is observed for the expressions compared with HSPICE simulations for Fourier series with tens of terms. In addition, from these results a new model for transient response of a line considering the driver output resistance and capacitance is presented. Good accuracy is observed between the model and HSPICE simulations for various distributed interconnects and drivers. Furthermore, the developed solution is extended to include signal transient and crosstalk noise in multicoupled inductive-effect-prominent lines. In addition, arbitrary switching patterns for identical and nonidentical lines are investigated employing the new method and evaluated with HSPICE simulations.

FDTD technique based crosstalk analysis of bundled SWCNT interconnects

The equivalent electrical circuit model of a bundled single-walled carbon nanotube based distributed RLC interconnects is employed for the crosstalk analysis. The accurate time domain analysis and crosstalk effect in the VLSI interconnect has emerged as an essential design criteria. This paper presents a brief description of the numerical method based finite difference time domain (FDTD) technique that is intended for estimation of voltages and currents on coupled transmission lines. For the FDTD implementation, the stability of the proposed model is strictly restricted by the Courant condition. This method is used for the estimation of crosstalk induced propagation delay and peak voltage in lossy RLC interconnects. Both functional and dynamic crosstalk effects are analyzed in the coupled transmission line. The effect of line resistance on crosstalk induced delay, and peak voltage under dynamic and functional crosstalk is also evaluated. The FDTD analysis and the SPICE simulations are carried out at 32 nm technology node for the global interconnects. It is observed that the analytical results obtained using the FDTD technique are in good agreement with the SPICE simulation results. The crosstalk induced delay, propagation delay, and peak voltage obtained using the FDTD technique shows average errors of 4.9%, 3.4% and 0.46%, respectively, in comparison to SPICE.

A Comparative Study of Interconnect Circuit Techniques for Energy Efficient On-Chip Interconnects

The aggressive technology scaling in VLSI leads to decrease the size of chip. Such continual miniaturization of VLSI devices has strong impact on interconnects in several ways. Interconnects in high speed applications suffer from crosstalk, signal delay and ground noise, causing degradation of system performance. Thus interconnects are becoming a limiting factor in determining circuit performance. This paper presents a comparative study on different interconnect circuit techniques for on chip interconnects. We have compared different circuit structure by placing on RC and RLC interconnects. In this delay benefit for current sensing increases with an increase in wire width. Unlike repeaters, current sensing does not require placement of buffers along the wire and it eliminates any placement constraints. Out of all these techniques a differential RLC current mode signaling circuit insertion has offered the less amount of energy. All the circuits are simulated and compared different parameters such as power, delay and energy by using micro wind in 45nm technology.

RLC equivalent RC delay model for global VLSI interconnect in current mode signalling

Current-mode signalling significantly increases the bandwidth of on-chip interconnects and reduces the overall propagation delay. The inductive effect of interconnects is more dominant in submicron technologies. This is because an RC interconnects model results in a significant error in delay estimation. Consequently to avoid such errors, a delay model for current-mode signalling is proposed for RLC interconnect line in the present work. RLC interconnect line is modelled using characteristic impedance of line. The inductive effects which are dominant at lower technology nodes are modelled as an equivalent resistance (). RLC line is modelled into a new equivalent ReffC interconnect line. The efficacy of the proposed model is validated for 8 and 10 mm interconnect lines. It is inferred that current mode provides better performance compared to the voltage-mode signalling. It is found that current-mode signal transporting technique provides higher speed improvements. Secondly, the damping factor of a lumped RLC circuit is shown to be a useful figure of merit. The analysis is carried out for 180 nm technology node.

Analytical Solutions for Distributed Interconnect Models—Part I: Step Input Response of Finite and Semi-Infinite Lines

With Fourier series and Fourier integrals, a new and systematic approach, called the Amir and Nasser (AMN) method, is proposed to derive exact analytical expressions for step input response of distributed resistance capacitance (RC), inductance-capacitance (LC), and resistance-inductance-capacitance (RLC) models of interconnects. These solutions are obtained for time-domain responses of any arbitrary point on a finite interconnect line, considering initial voltage through the line. This method is appropriate for both on-chip and printed circuit board wires without any limitations in their length or characteristic parameters. The developed solutions are expressed as infinite summation of sinusoidal terms. An accuracy of over 99.5% is observed for the expressions compared with the HSPICE simulations for at most a number of several tens of sinusoidal terms for Fourier series. It is shown that ignoring the initial voltage through the line leads to considerable error as high as 33% at the far end voltage in global interconnects for 65-nm technology node. The AMN method is extended to semi-infinite distributed RC and RLC interconnects for which exact closed-form expressions are achieved.

Carbon Nanotube Based Delay Model for High Speed Energy Efficient on Chip Data Transmission Using: Current Mode Technique

Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination. RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect. The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.