Ripple Cancellation Research Articles

Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier

A wideband hybrid Envelope tracking (ET) modulator utilizing a hysteretic-controlled three-level switching converter (3L-SWC) and a slew-rate enhanced linear amplifier (LA) are presented. In addition to smaller ripple and lower losses of 3L-SWCs, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80 MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage $V_{\mathrm{ CF}}$ and eliminates the conventionally required calibration loop to control it. The hysteretic-controlled 3L-SWC provides a high percentage of power amplifier (PA) supply load current with lower ripple, reducing the LA high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the LA, resulting in slew rate of over 307 V/ $\mu \text{s}$ and bandwidth of over 275 MHz for the LA. The SRE circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of output without modifying the operating point of the remaining LA, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in a 65-nm CMOS process. The measurement results show the tracking of long-term evolution (LTE)-40-MHz envelope with 93% peak efficiency at 1-W output power, while the SRE is disabled. Enabling the SRE, it can track LTE-80-MHz envelope with peak efficiency of 91%.

Quadratic buck–boost converter with reduced input current ripple and wide conversion range

This study introduces an advanced DC-DC power converter with two main objectives, (i) to achieve a wide range of voltage gain, which means the converter may work over a wide range of input voltage for a fixed desired output voltage and (ii) to achieve a reduced input current ripple. Those features are highly desired in renewable energy applications, for example with photovoltaic panels and fuel cells. The proposed converter was designed in a structure in which the input voltage is composed by the difference of two inductor currents, the currents through inductors are driven with transistors that may have different duty cycle, this allows the current ripple cancellation. In addition, the structure of the converter provides a quadratic type voltage gain, which leads to a wide range of operation voltage. The converter achieves both the wire range of voltage gain and current ripple cancellation, nonetheless, the buck-boost capability is also provided. The input current ripple reduction helps preserve the renewable energy sources since they suffer deterioration when current with considerable ripple is drawn from them. Dynamic and steady-state analysis are performed along with the components sizing. Simulation and experimental results are provided to demonstrate the principle of the proposition.

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique

This article presents a reference ripple cancellation technique for high-speed successive approximation register analog-to-digital converters (SAR ADCs) to address the reference voltage settling issue. Unlike prior techniques that aim to minimize the reference ripple, this article proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. To verify the proposed technique, a prototype 10-bit 120-MS/s SAR ADC is fabricated in a 40-nm CMOS process. The proposed ripple cancellation technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL)/differential non-linearity (DNL) by ten times. Overall, the ADC achieves an SNDR of 55 dB with only 3-pF reference decoupling capacitor.

A Multiplexing Ripple Cancellation LED Driver With True Single-Stage Power Conversion and Flicker-Free Operation

Although a single-stage off-line power light-emitting diode (LED) driver can achieve low cost and high efficiency, the notorious double-line-frequency flicker issue with a single-stage LED driver limits its usage in high-quality lighting applications. To solve lighting flicker, as well as maintain a low cost and high efficiency, a multiplexing ripple cancellation (MRC) LED driver is proposed in this paper. One switching cycle is divided into two intervals. During the first interval, the proposed LED driver operates as a conventional LED driver that transfers energy from the ac input to LED output, performs power factor correction, and generates the main output voltage. The main output voltage has a double-line-frequency ripple like in a conventional design. During the second interval, the proposed LED driver transfers energy from the ac input again to generate an opposite ripple voltage to cancel the ripple voltage from the main output. In this way, the voltage across the LED load is a dc to achieve flicker-free LED driving performance. More than 99% of the output power goes through one-time power conversion, while less than 1% goes through two-time power conversion. A 7.5-W experimental prototype is built and tested to verify the design concept.

A New Two Input-Single Output High Voltage Gain Converter With Ripple-Free Input Currents and Reduced Voltage on Semiconductors

In this paper, a new non-isolated two-input single-output dc-dc converter with high voltage gain is proposed. In the proposed converter, there are two three-winding coupled inductors used to achieve a high voltage gain and ripple-free input currents. The proposed converter has two switches, and their control pulses are the same as the control pulses of the two-phase interleaved converters with a phase shift equal to 180°. The voltage stresses of switches and diodes are reduced and are always lower than the high output voltage. The proposed converter is extendable to a four-input single-output converter in which the switches have the control pulses the same as those in four-phase converters with phase shifts equal to 90°. In this paper, the proposed topology is analyzed in all operating modes, and the values of current and voltage stresses of all switches and diodes, voltage gain, and required conditions for input current ripple cancellation are calculated during a switching period. Finally, the accuracy performance of the proposed converter is reconfirmed through experimental results for 225- and 298-W prototypes.

Optimization of a Series Converter for Low-Frequency Ripple Cancellation of an LED Driver

In this paper, the optimization of the power and control stages of a previously proposed topology for an off-line LED electronic driver is presented. The full system avoids the use of electrolytic capacitors at the D C link, therefore increasing the lifespan and reliability of the driver. As a consequence of having a relatively small capacitance, the D C link operates with a large Low-Frequency ( L F ) voltage ripple. This work presents a design optimization for the power and control stages of a current-fed bidirectional buck converter, operating as the LED current control stage. As this block processes only the A C power arising from the L F voltage ripple, it can increase the system efficiency against the typical two-stage solution. In the original proposal, the main drawback was the high inductor losses due to the resulting large inductor currents and large inductance value. The proposed optimization ensures an enhanced design of the inductor while keeping a constant current through the LEDs. A new optimization methodology is proposed and the theoretical results have been validated in a built prototype for a 40 W LED lamp.

Current balancing control for an interleaved boost power converter

ABSTRACTThe interleaved boost power converter has the advantages of ripple cancellation and better efficiency. The major problem of the interleaved boost power converter is the current balancing among different phases of the boost power converters. In this paper, a current balancing control method for equalizing the currents of two-phase interleaved boost power converter is proposed. The output current can effectively detect the mismatch between the boost power converters for the interleaved boost power converter. The output current is used to perform both the current balance and the current-mode control. The salient feature is that only one current sensor is used in the proposed current balancing control method. A hardware prototype is developed, and the experimental results verify the performance of the proposed current balancing control method is as expected.

Analysis of the Steady-State Current Ripple in Multileg Class-D Power Amplifiers Under Inductance Mismatches

Multileg Class-D amplifiers (CDAs) with phase-shifted carrier modulation can increase the equivalent switching frequency and reduce the output current ripples, which further reduces the size of the output filter. However, these benefits are degraded by the tolerances in the phase inductance values. The phase inductance mismatches impact the ripple cancelation effects (the harmonic contents at switching frequency and its harmonics appearing in the output current ripple). Therefore, the quality of the output waveform can further be impacted. Current research works dealing with this issue mainly focused on the interleaved dc–dc converters, which does not cover the analysis in multileg CDAs or inverters, especially for the full-bridge configuration. This paper proposes a general analytical method to characterize the steady-state phase and the total current ripple in the multileg CDAs with full-bridge configuration under inductance mismatches. Monte Carlo simulation is used to study the impact of inductance mismatches on the harmonic contents of the total current ripple, and the distribution law of the inductances at the worst case is revealed. The analytical method is verified by simulation and experimental results of a four-leg full-bridge CDA. A design guideline is given to optimize the filter design based on the analytical method.

Performance evaluation of a permanent magnet electric-drive-reconfigured onboard charger with active power factor correction

This paper presents a comprehensive charging operation for an electric-drive-reconfigured onboard charger (EDROC) with active power factor correction (APFC). The charging topology exclusively utilizes the three-phase permanent magnet synchronous motor (PMSM) propulsion system as a three-channel boost-type converter in which only a contactor and a small diode bridge are added. First, the operation scenario of the EDROC is introduced. Second, the relationship between electromagnetic torque and rotor position is investigated. Third, the current ripple cancellation of the EDROC is discussed in detail. Moreover, to implement the single-phase APFC along with charging voltage/current regulation of propulsion battery, control strategies including current balancing and synchronous/interleaving PWM strategies are incorporated. Finally, 200W proof-of-concept prototype-based tests are conducted under different operation scenarios.

Three‐phase ripple free DCM boost converter with low THD

High total harmonic distortion (THD) and ripple of input current are the two main disadvantages of a single switch discontinuous current mode boost power factor correction (PFC) converter. In this study, THD and input current ripple of conventional DCM boost converter are improved. Reduction of input current THD is achieved by reducing the discharge time of input inductors using magnetic switch concept. Input inductors currents are discharged with a voltage equal to twice of output voltage instead of the output voltage. Also, high input current ripple in discontinuous conduction mode (DCM) operation is solved by using an additional input inductor-capacitor (LC) filter in the conventional converter. This will result in extra weight and volume of the converter. To eliminate the required additional inductors for implementation of the mentioned input LC filter, a ripple cancellation cell using coupled inductors is used and by adjusting mutual inductance in a proper manner, very low input current ripple is achieved. Results from a 400 W prototype converter are presented. Input current THD is below 8% for a wide range of input voltage. Furthermore, the efficiency of the proposed converter is compared with conventional DCM boost PFC converter under the same input current THD. Although the proposed converter applies two switches, the total switching and conduction losses are reduced considerably.

PMSG-based Wind Turbine Torque Harmonic Reduction Through LPV Control of EKF-Based Disturbance Estimation

Torque disturbance is imposed by the non-stationary wind profile, tower shadow, and wind shear propagate along the drive train to reach wind turbine generators. This is the main cause of several detrimental effects to several mechanical components specifically bearings, gearboxes, drive train, generators, etc. This paper applies Linear Parameter Varying (LPV) control technique based on harmonic estimation and torque reconstruction using the Extended Kalman filter for wind turbine torque ripple cancellation.

A Spur-Reduction DC–DC Converter With Active Ripple Cancelation Technique

This paper presents an active ripple cancelation (ARC) technique for reducing the switching harmonics of the output voltage of a dc–dc converter. An ARC module injects an ac current to accurately cancel the inductor current ripple while the switching converter provides the dc output current. As a result, the output spur of the switching converter can be reduced effectively. However, due to the ARC module, the proposed power converter includes two complex poles. To ensure the system stability and achieve accurate ripple cancelation, a proposed control method and an adaptive phase-lock circuit are utilized. Furthermore, the ripple cancelation capability is independent of duty cycle, load current, and other converter parameters. The measurement results demonstrate that the switching spur reduction with ARC technique can achieve 28 dB while the noise floor is kept the same.

A Single-Stage Electrolytic Capacitor-Less AC-DC LED Driver

The electrolytic capacitor is the mainly component that impact the working lifetime of light-emitting diode (LED). If an ac-dc LED driver with ripple cancellation method, the electrolytic capacitor eliminate is of vital importance. Therefore, this paper present a solution with secondary side full-bridge structure for cancel the twice ac line ripple from the LED driver. In order to reduce the components cost and LED driver volume, a single-stage high efficiency electrolytic capacitor less isolate ac-dc LED driver is implement and discussed in detail, which is a discontinue conduction model (DCM) power factor correction (PFC) buck-boost converter integrated a isolate flyback converter. Finally, a 100W prototype has been built and tested. Experiment results demonstrated the effectiveness and high feasibility of the proposed LED driver.

A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range

One of the most critical attributes of low dropout regulators (LDOs) in increasingly complex systems on chip (SoCs) is high-power supply rejection ratio (PSRR), not only over a wide frequency range but also over a large load current range. This paper presents an LDO, realized in 65-nm CMOS, featuring >60-dB PSRR over a 10-MHz frequency range and a 100-mA large load current range. The high PSRR is achieved by an adaptive feed forward ripple cancellation (FFRC) technique embodying an adaptive load current tracking scheme. By means of embodying an NMOS-based power stage, the LDO also achieves very low dropout voltage of 80 mV and features very small overshoot and undershoot of 2 and 4 mV, respectively.

Torque Sensor Embedded Actuator Module for Robotic Applications

Measuring accurate torque is a core ability of advanced robotic technologies. However, embedding torque-sensing systems into robot joints are still a challenge due to limitations including size, weight, and cost. Moreover, the influence from axial forces/torques ( x - and y -axis) and the sinusoidal effect from the harmonic drive make it difficult to measure torque accurately. This paper presents a novel actuator module for robotic applications that includes a torque sensor, harmonic drive, motor, and encoder. The torque sensor adopts the capacitive sensing scheme, which can allow for self-decoupling of the axial influences through the use of a symmetric arrangement of sensing cells. Moreover, the torque ripple cancellation method, which can reduce the sinusoidal effect from the harmonic drive, is introduced. Finally, the detailed design of the actuator module is described, and its performance is experimentally evaluated.

Input-current/output-voltage ripple mitigation in the double dual boost converter

In this paper a novel switching ripple mitigation technique is developed and applied to the double dual boost converter (DDBC). Under the proposed scheme, an unconstrained selection of the voltage-gain-range at which the input-current ripple is mitigated is enabled. Furthermore, as an emerging advantage of this new strategy, we demonstrate that the elimination of the output-voltage ripple can be also achieved. The simultaneous input-current- and output-voltage ripple mitigation under a fixed but otherwise arbitrary selection of the converter's input-to-output voltage gain is the main contribution of this work, which is in sharp contrast with current switching techniques that are exclusively focused on input-current ripple cancellation at constrained duty cycles. Theoretical and experimental evidence is presented to validate the proposed scheme.

Analysis and implementation of a step–up power converter with input current ripple cancelation

SummaryThis paper proposes a power electronics converter capable of canceling the input current ripple at preselected duty cycle. The proposed converter is an extended topology of a buck–boost converter aided by a boost‐type converter that improves the quality of the current drawn from the direct current source. The voltage gain of the proposed converter is increased as well, with a minimum of extra component added to the original buck–boost power converter. These features make the proposed converter ideal for low voltage generation sources, such as photovoltaic panel and fuel cell applications. Along this paper, the state space mathematical model is developed to provide the key design guidelines. The theoretical analysis is validated through computer simulation and hardware prototyping.

Unity power factor three‐phase AC–DC converter applying two switch DCM SEPIC converter with coupled inductors

A two switch three-phase power factor correction SEPIC converter with coupled inductor operating in discontinuous current mode is presented. The switches voltage stress in this converter is related to peak of phase voltage instead of line voltage. Also, applying coupled inductor technique, not only reduces number of the magnetic cores but also with suitable design of coupling coefficient, input current ripple cancellation is achieved, so smaller inductor size can be used as input inductance. Thus, the proposed converter only applies three magnetic cores and <;5% THD is achieved with the proposed converter in a wide range of load and input voltage variations. Input phases are decoupled so converter can keep unity power factor even under unbalanced input source. Operating modes of the proposed converter is explained, and its input impedance is determined. It is verified that input impedance is pure resistive. The mathematical analysis and design procedure are discussed. Design example and experimental results from 400 W prototype with 220 V line to natural input RMS phase voltage and with 400 V output voltage operating at 40 kHz are presented to verify theoretical analysis.

Enhanced method of rotor speed and position estimation of permanent magnet synchronous Machine based on stator SRF-PLL

A stator flux oriented synchronous reference frame - phase locked loop (SRF-PLL) is proposed for the precise computation of rotor speed and position of permanent magnet synchronous machine (PMSM). A direct method of rotational speed computation based on the stator electromotive force (EMF) is initially formulated. Using the speed asa reference to the inverse Park and Clarke transformation blocks, the three-phase positive sequence stator flux is derived. A pre-stage low pass filter (LPF) is implemented to cancel out the ripples in the d-q components of the stator flux introduced by the dynamic operating conditions of inverter non-linearities and grid disturbances. The estimated three-phase positive sequence stator flux is used to compute the rotor position by aligning the total stator flux along the direct axis through a PLL block. Provision of the frequency amendment and ripple cancellation outside the PLL block results in a fast-dynamic response with an enhanced frequency adaptable capability. To validate the effectiveness of the proposed method, the sensorless vector control of grid integrated PMSM based wind-driven generator (WG) is analytically verified using the PSCAD/EMTDC simulation tool under various dynamic operating conditions such as wind speed variation and grid disturbances.

Coupled-Inductor-Based High-Step-Down-Ratio Converter with Output Current Ripple Reduction

Even though the coupled-inductor-based high-step-down-ratio converters can achieve a higher step-down voltage gain than the traditional buck converter, their output current suffer from a high output current ripple, causing a high output voltage ripple. Therefore, a bulky electrolytic output capacitor is usually used to suppress the output voltage ripple. Moreover, the longevity of the output electrolytic capacitor is highly dependent on the output current ripple. In [6–8], a passive current ripple cancellation circuit was applied to the DC–DC converters to reduce the output current ripple. However, these literatures did not mention and analyze the situations for coupled-inductor converters. Moreover, the same concept, including analysis and design, cannot be directly applied to the coupled-inductor-based converters. Therefore, in this paper, the analysis, design, and experimental results of the current ripple cancellation circuit applied to the coupled-inductor-based high-step-down-ratio converter are given to verify the effectiveness.