Ring Oscillator Circuit Research Articles

Design and Performance of Charge-Plasma-Based Schottky –FET CMOS Circuit Ring Oscillator for High Density ICs

In this work, we developed and explored the CMOS circuits ring oscillator with n- and p-channel on scaled SB-FETs for low power applications. Newly, a source-side charge plasma schottky barrier (SB) SB-FETs have been acquainted as the furthermost practical at nano-meter node technology. So, it is essential to examine the electrical characteristics of SB-FETs and their performance. Initially, we have been explored the source-side charge plasma SB-FET and its electrical characteristics has been simulated in compared with conventional SB-FET. The SILVACO simulator is used to simulate the proposed and conventional SB-FETs. In this source-side charge plasma SB-FET technique has improved resolution, and deliver outstanding concert (higher Ion/Ioff ratio) than conventional device reported in this research. Moreover, the precise exploration of the on-state performance of SB-FETs is mostly resolved by the electron and hole energy band of the channel. Additional, for the first time, source-side charge plasma SB-FET-based CMOS inverter and ring oscillator circuits have been calculated by the numerical simulator. The concentrated gate capacitance also grades in compact dynamic power degeneracy of source-side charge plasma schottky barrier SB-FET CMOS circuits and ring oscillator suggest lower voltage of process with condensed power intake, and great noise protection compared with convention device.

Compact Modeling of Capacitance Based 14 nm Triple Gate FinFET Using Verilog-A

Technology down scaling process divulges, the unveiled short channel effects (SCEs), which disrupts the behavior of bulk CMOS technology. In order to overcome these unveiled effects, the single gate controlling mechanism should be replaced with multiple gate mechanism to enhance the control of gate over the conducting channel. FinFET is a promising technology, which provides efficient gate controlling over the channel by multiple gates. Some of the multi gate FinFET devices are Double gate FinFET (DG-FinFET), Triple gate FinFET (TG-FinFET). In this paper, a charge based capacitance model has been proposed for modeling of TG-FinFET. The behavior and structure of the proposed device has been described in Verilog-A scripting language. IV characteristic of the proposed device has been observed, a three stage ring oscillator circuit is implemented with the proposed device to generate 1 GHz signal for testing purpose.

Measurement and Modeling of Ambient-Air-Induced Degradation in Organic Thin-Film Transistor

The lifetime of organic thin-film transistors (OTFTs) is known to be significantly shorter than that of silicon MOSFETs. It is therefore important to be able to predict their degradation early in the design phase. In this paper, OTFT current characteristic variation is studied in measurements of fabricated devices. In addition, we propose a drain-current simulation model that incorporates temporal parameter variation. The proposed model expresses parameter degradations as changes in threshold voltage and carrier mobility. With the extracted parameters, our proposed model successfully reproduces the temporal performance degradation observed in fabricated devices. We compared our proposed model with existing parameter variation models by fitting with measurement results. Root mean square errors (RMSEs) were calculated for each model. Our proposed model achieved an RMSE of 2.26% whereas that of the existing model was 9.80%. Oscillation frequency degradation in an organic ring oscillator (RO) circuit was also simulated to compare with the measurement results. The simulation results adequately captured the degradation trend observed in the measured results.

Reliability Characterization of Ring Oscillator Circuits for Advanced CMOS Technologies

Ring-Oscillator (RO) are most suitable to investigate the reliability of digital CMOS circuits operating up to GHz frequencies as a good correlation has been observed between RO degradation and Product Fmax degradation. In addition, the RO degradation testing can be performed with similar equipment used for discrete device reliability characterization. In this work, we discuss the role of BTI/HCI contribution in RO degradation and compare the contributions of NFET and PFET devices. To decouple BTI/HCI contribution, AC characterization on discrete devices is conducted and correlated to the RO degradation under diverse testing conditions. Additionally, specially designed reliability RO are used to quantify device type contribution under RO stress.

High-Speed Complementary Integrated Circuit with a Stacked Structure Using Fine Electrodes Formed by Reverse Offset Printing

A reverse offset-printed stacked-structure complementary ring oscillator and operational amplifier (OPA) circuits were constructed on a large-area substrate. Uniform and fine electrodes were fabric...

Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications

This article investigates the performance of a vertically grown GaSb/Si tunnel field effect transistor (V-TFET) with a source pocket to enhance the performance of the device. The commercially available Silvaco TCAD has been used for simulating the proposed V-TFET structure. A low bandgap material, GaSb, is used in the source region for the first time to enhance the carrier tunneling through the source (GaSb)-channel (Si) heterojunction. The proposed V-TFET with a pocket shows the improved subthreshold swing (SS) of 26 mV/decade at ${V}_{{\textit {DS}}}= 0.5$ V over the V-TFET without any pocket. The effects of temperature on SS and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio along with the analog/RF figures of merit (FOMs) are also analyzed for V-TFETs with and without a pocket. The results are also compared with some recently reported TFETs. The dc and analog/RF performances of V-TFET with a pocket are shown to be better than those of the V-TFET without a pocket and other reported TFET structures. Finally, the applications of V-TFETs with and without a pocket in designing inverter and ring oscillator circuits have been demonstrated. The dc and transient responses of the V-FET-based inverter and ring oscillator circuits have been analyzed using the Verilog-A model in the CADENCE tool.

Modeling of HCD Kinetics Under Full VG – VD Space, Different Experimental Conditions and Across Different Device Architectures

A SPICE compatible compact modeling framework is discussed for Hot Carrier Degradation (HCD) stress spanning the entire drain (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) and gate (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) voltage space and wide range of temperature (T). It can model the HCD time kinetics measured using different methods such as shift in threshold voltage (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ), linear (Δ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IDLIN</sub> ) and saturation (Δ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IDSAT</sub> ) drain current and charge pumping current (Δ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ICP</sub> ), for off and on-state stress. The model is validated using measured data from conventional, Lightly Doped Drain (LDD) and Drain Extended (DE) MOSFETs, FinFETs and Gate All Around Nano Sheet (GAA-NS) FETs. Parametric drift due to Bias Temperature Instability (BTI) stress in the presence of VD is included. Impact due to Self-Heating (SH) and BTI-HCD coupling are considered. SPICE compatibility is shown by cycle-by-cycle simulation of various Ring Oscillator (RO) circuits.

Nonquasi-Static Capacitance Modeling and Characterization for Printed Inorganic Electrolyte-Gated Transistors in Logic Gates

Printed electronics can benefit from the deployment of electrolytes as gate insulators, which enables a high gate capacitance per unit area (1– $10\,\,\mu \text {F}\,\text {cm}^{-2}$ ) due to the formation of electrical double layers (EDLs). Consequently, electrolyte-gated field-effect transistors (EGFETs) attain high-charge carrier densities already in the subvoltage regime, allowing for low-voltage operation of circuits and systems. This article presents a systematic study of lumped terminal capacitances of printed electrolyte-gated transistors under various dc bias conditions. We perform voltage-dependent impedance measurements and separate extrinsic components from the lumped terminal capacitance. The proposed Meyer-like capacitance model, which also accounts for the nonquasi-static (NQS) effect, agrees well with experimental data. Finally, to verify the model, we implement it in Verilog-A and simulate the transient response of an inverter and a ring oscillator circuit. Simulation results are in good agreement with the measurement data of fabricated devices.

A Low-Power Sensitive Integrated Sensor System for Thermal Flow Monitoring

Thermal-based flow monitoring has found widespread applications due to its noncontact measurement, high sensitivity, low flow resistance, miniaturization, ease of integration, and low-power consumption. In this work, a low-cost and affordable inkjet-printed graphene-based thermal sensor is integrated with a low-power CMOS circuit for flow rate monitoring. The custom inkjet-printed sensor consists of a silver nanoparticle interdigitated pattern with a coating of graphene, all printed on a glossy photo-paper substrate. The sensor read-out circuit is an energy-efficient current-starved ring oscillator. The sensor current controls the bias current of a current-starved ring oscillator and modulates the output frequency. A driver circuit then transforms the output to a square wave pulse signal. The scheme is designed and fabricated using the 0.13- $\mu \text{m}$ standard CMOS process and occupies an area of 1.5 mm $\times1.7$ mm. Test results indicate that the prototype ring oscillator circuit consumes 19– $90~\mu \text{W}$ for an oscillation frequency variation of 517 kHz–6.45 MHz. The output frequency variation with sensor current shows linear performance with ${R}^{2} = 0.9966$ .

Yield Learning Methodologies and Failure Isolation in Ring Oscillator Circuit for CMOS Technology Research

We detail the use of ring oscillators (ROs) for yield learning during the research phase of a CMOS technology generation. Failing circuits are located and classified based on electrical analysis of ROs and FETs (Field Effect Transistor) wired out from RO environments. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto. Inline defect monitoring can help to estimate RO yield and is essential in CMOS technology research.

Low‐Voltage Operation of Ring Oscillators Based on Room‐Temperature‐Deposited Amorphous Zinc‐Tin‐Oxide Channel MESFETs

AbstractSchottky diode FET logic (SDFL) ring oscillator circuits comprising metal‐semiconductor field‐effect transistors (MESFETs) based on amorphous zinc‐tin‐oxide (ZTO)n‐channels are presented. The ZTO channel layers are deposited entirely at room temperature by long‐throw magnetron sputtering. Best MESFETs exhibit on/off current ratios as high as 8.6 orders of magnitude, a sub‐threshold swing as low as 250 mV dec−1, and a maximum transconductance of 205 µS. Corresponding inverters show peakge gain magnitude (pgm) values of 83 with uncertainty levels as low as 0.5 V at an operating voltage of 5 V. Single stage delay times down to 277 ns are measured for three‐stage ring oscillators, corresponding to oscillation frequencies as high as 451 kHz. Oscillations are observed at operating voltages as low as 3 V. These results prove the feasibility of room‐temperature‐deposited, amorphous semiconducting oxide based integrated circuits with SDFL layout. The presented approach provides more efficient as well as fail‐safe device fabrication and similar oscillation frequencies at significantly lower operating voltages compared to conventional, high‐temperature processed logic circuits based on insulating gates.

CNT Electronics: Advances in High‐Performance Carbon‐Nanotube Thin‐Film Electronics (Adv. Electron. Mater. 8/2019)

The center of the image shows the device structure of a typical top-gate field-effect transistor based on aligned carbon nanotube (CNT) arrays, which, as discussed by Zhiyong Zhang, Lian-Mao Peng, and co-workers in article number 1900122, is a key component for future high-performance digital applications. The background shows examples of such an application–5-stage carbon nanotube ring oscillator circuits with an oscillation frequency of 5.54 GHz.

Design and Analysis of Gate All Around Tunnel FET based Ring Oscillator Circuit

In this work, we have designed and simulated a Gate All Around TFET (GAATFET) based 3 stage ring oscillator circuit and compared its performance with the CMOS based counterpart. The results of SPICE simulations indicate that GAATFET based ring oscillator circuit consumes 3.5 times lower power consumption in active mode than CMOS based ring oscillator. However, 0.43 ns and 0.17 ns of propagation delay is observed for GAATFET based ring oscillator and CMOS based ring oscillator circuit respectively. The obtained output waveform frequency for CMOS based ring oscillator is 2.5 times higher than the GAAATFET based ring oscillator. Further, undershoot is also investigated and it is found that the amplitude of undershoot in case of GAATFET based oscillator is roughly 6.5 times more as compared to CMOS based counterpart. The undershoot and delay observed in case of GAATFET based ring oscillator can be over-shaded by the fact that it has lower active power consumption than the CMOS based ring oscillator. Simulation results signify that GAATFET based ring oscillator can be deployed in future low power VLSI circuits and systems.

Design and analysis of nano-scaled SOI MOSFET-based ring oscillator circuit for high density ICs

This paper presents the design and analysis of ring oscillator circuit based on nano-scaled SOI MOSFETs for low power applications. Recently, fully depleted silicon-on-insulator (FD SOI) MOSFETs have been recognised as the most viable technology at nanometer nodes. Therefore, it is necessary to analyze the electrical performance of SOI technology MOSFETs and their switching characteristics. In this contribution, firstly we have investigated the short channel immunity of dual metal insulated gate (DMIG) technique-based FD SOI MOSFET and its electrical characteristics has been compared and contrasted with the available state-of-arts. The device has been designed and simulated using numerical ATLAS SILVACO simulator. FD SOI technology along with DMIG technique found to be a better solution, and provide excellent performance (higher Ion/Ioff ratio, and lower sub-threshold slope) than other techniques reported at this node. Additionally, the detailed analysis of surface potential profile, electric field, electron concentration, and the contour plot of conduction current density have been taken into account. Further, for the first time, DMIG FD SOI MOSFET-based CMOS inverter and ring oscillator circuits have been designed using the same numerical simulator. DC and transient analysis itself explains that the designed CMOS inverter and ring oscillator offer lower voltage of operation with reduced power consumption, and high noise immunity. The oscillation frequency of ring oscillator is found as 84.18 GHz at 50 nm channel length.

Static and Quasi-Static Drain Current Modeling of Tri-Gate Junctionless Transistor With Substrate Bias-Induced Effects

In this paper, a surface potential-based drain current model is developed to explore the static and quasi-static performance of substrate-biased tri-gate junctionless field-effect-transistors (TGJLFETs). The effects of substrate bias voltage on surface potential, charge density, and drain current are analyzed. The 2-D Poisson’s equation is solved to obtain front and back surface potentials incorporating the effect of substrate bias voltage for a long-channel TGJLFET. The front and back surface potentials are subsequently utilized to obtain total conduction charge density and drain current. Further, short-channel and quantum mechanical corrections are incorporated in the model to use it for scaled devices. Moreover, the terminal charges calculated using Ward–Dutton’s charge partitioning scheme are utilized to model the transcapacitances and quasi-static drain current for TGJLFET. Further, an equivalent large-signal transient model of the device is implemented in SPICE using Verilog-A, and the transient behavior of inverter and ring oscillator circuits are simulated and studied. The models are validated using a 3-D Visual TCAD device simulator from Cogenda Pvt. Ltd.

Impact of different localized trap charge profiles on the short channel double gate junctionless nanowire transistor based inverter and Ring Oscillator circuit

In this paper, the reliability issues due to localized charges on Double Gate Junctionless Nanowire Transistor (DG-JNT) based circuits are investigated. The localized/fixed charges come into existence at the interface of substrate and oxide in the device during the manufacturing due to radiation, stress, process and hot carriers damage which significantly alters various characteristics of the device. The damage due to different profiles of localized charges on several parameters of DG-JNT based P-MOSFET is analyzed. Also, for analog circuit application, this work explicitly reports the comprehensive analysis of localized charge profiles on DG- JNT based CMOS inverter and three Stage Ring Oscillator circuit at 20 nm Gate length. The simulated results are obtained using Silvaco Atlas, TCAD device simulator.

Speeding up carbon nanotube integrated circuits through three-dimensional architecture

Semiconducting carbon nanotube (CNT) field effect transistor (FET) is attractive for constructing three-dimensional (3D) integrated circuits (ICs) because of its low-temperature processes and low power dissipation. However, CNT based 3D ICs reported usually suffered from lower performance than that of monolayer CNT ICs. In this work, we develop a 3D IC technology through integrating multi-layer high performance CNT film FETs into one chip, and show that it promotes the operation speed of CNT based 3D ICs considerably. We also explore the advantage on ICs of 3D architecture, which brings 38% improvement on speed over two-dimensional (2D) one. Specially, we demonstrate the fabrication of 3D five-stage ring-oscillator circuits with an oscillation frequency of up to 680 MHz and stage delay of 0.15 ns, which represents the highest speed of 3D CNT-based ICs.

Atmospheric-pressure plasma oxidation of aluminum for large-area electronics

We developed an atmospheric pressure plasma (APP) process for forming metal oxides and self-assembled monolayers (SAMs) without a vacuum process. SAMs are frequently utilized for surface modification. In particular, a combination of aluminum oxide (AlOx) and alkylphosphonic acid is used as the gate dielectric in flexible electronics, with a low operating voltage of 2 V because of its simple fabrication process at room temperature in air. However, when using a combination of SAMs and AlOx as the gate dielectric, it is necessary to form a metal oxide with sufficient thickness using a vacuum plasma process to reduce the leakage current, which is not suitable for use in flexible large-area electronics. In this study, we resolved this problem by utilizing an APP process and substrate heating instead of the vacuum plasma process. Heating a substrate above 100 °C forms a sufficient AlOx layer. The leakage current of plasma-processed AlOx with SAMs was reduced by three orders of magnitude compared to that of natural AlOx with SAMs. X-ray photoelectron spectroscopy revealed a time dependence of the thickness of AlOx. An exposure time of 100 s was sufficient to form an AlOx layer with a thickness of 4 nm. An organic transistor with this APP treatment of AlOx and SAMs showed a mobility of 1.4 cm2/V s and an on/off ratio of 104 within 2 V. We also fabricated an inverter and a ring oscillator circuit with an inverter gain of more than 300 and an oscillation frequency of 40 Hz.

Process-Induced Power-Performance Variability in Sub-5-nm III–V Tunnel FETs

We examine the power-performance variability of a projected sub-5-nm GaAsSb/InGaAs vertical tunnel FET considering various process control tolerances in the state-of-the-art device integration and propose countermeasures in device design. Nominal and three-sigma-corner device characteristics generated in quantum-mechanical/TCAD simulations are used to calibrate a semiempirical compact model, based on which the nominal and variability-inclusive energy-delay landscapes are extracted from ring-oscillator circuit simulations at sub-500-mV supply voltages. Variations in four parameters are identified as of major impact on the worst-case speed loss and iso-speed energy penalty: dopant pocket thickness, gate work function, hetero-band offset, and body thickness (in descending order). Variability-resilient device options are explored against pocket thickness variation, including: 1) pocket desensitization with increased thickness and reduced doping concentration and 2) broken-gap tunnel FET with a negative effective band gap. Reengineered devices achieve $ speed loss and $ energy penalty for (0.1–1) ns gate delay with respect to the nominal corner.

Sub‐3 V ZnO Electrolyte‐Gated Transistors and Circuits with Screen‐Printed and Photo‐Crosslinked Ion Gel Gate Dielectrics: New Routes to Improved Performance

AbstractA facile, high‐resolution patterning process is introduced for fabrication of electrolyte‐gated transistors (EGTs) and circuits using a photo‐crosslinkable ion gel and stencil‐based screen printing. The photo‐crosslinkable gel is based on a triblock copolymer incorporating UV‐sensitive terminal azide functionality and a common ionic liquid. Using this material in conjunction with conventional photolithography and stenciling techniques, well‐defined 0.5–1 μm thick ion gel films are patterned on semiconductor channels as narrow as 10 μm. The resulting n‐type ZnO EGTs display high electron mobility (&gt;2 cm2 Vs−1) and on/off current ratios (&gt;105). Further, EGT‐based inverters exhibit static gains &gt;23 at supply voltages below 3 V, and five‐stage EGT ring oscillator circuits display dynamic propagation delays of 50 μs per stage. In general, the screen printing and photo‐crosslinking strategy provides a clean room‐compatible method to fabricate EGT circuits with improved sensitivity (gain) and computational power (gain × oscillating frequency). Detailed device analysis indicates that significantly shorter delay times, of order 1 μs, can be obtained by improving the ion gel conductance.