Ring Oscillator Circuit Research Articles

Progress Report on "From Printed Electrolyte-Gated Metal-Oxide Devices to Circuits".

Printed electrolyte-gated oxide electronics is an emerging electronic technology in the low voltage regime (≤1 V). Whereas in the past mainly dielectrics have been used for gating the transistors, many recent approaches employ the advantages of solution processable, solid polymer electrolytes, or ion gels that provide high gate capacitances produced by a Helmholtz double layer, allowing for low-voltage operation. Herein, with special focus on work performed at KIT recent advances in building electronic circuits based on indium oxide, n-type electrolyte-gated field-effect transistors (EGFETs) are reviewed. When integrated into ring oscillator circuits a digital performance ranging from 250 Hz at 1 V up to 1 kHz is achieved. Sequential circuits such as memory cells are also demonstrated. More complex circuits are feasible but remain challenging also because of the high variability of the printed devices. However, the device inherent variability can be even exploited in security circuits such as physically unclonable functions (PUFs), which output a reliable and unique, device specific, digital response signal. As an overall advantage of the technology all the presented circuits can operate at very low supply voltages (0.6 V), which is crucial for low-power printed electronics applications.

A high-resolution and glitch-free all-digital variable length ring oscillator design on an FPGA

This paper proposes an all-digital variable length ring oscillator (VLRO) circuit that is capable of easily controlling its output frequency without generating glitches at the frequency transitions on a field programmable gate array (FPGA). It includes two main blocks: 1) A coarse-tuning block is to widen the frequency range and 2) A fine-tuning block which is based on a dedicated high-speed carry chain is devised to improve the frequency resolution. Thanks to the use of high-speed carry chain, our circuit achieves a fine-grained delay resolution of 50 ps in average, which has a finer resolution than that of the state-of-the-art VLRO design in which the glitch problem has been solved with “lookup table” based coarse-grained delay lines. The proposed VLRO has been implemented on a Xilinx Spartan-6 FPGA for verifying its functional/timing correctness. It switches correctly between 22 different coarse-grained frequencies and 21 different fine-grained frequencies under different supply voltages.

Design of High Speed and Low-Power Ring Oscillator Circuit in Recessed Source/Drain SOI Technology

In this paper, switching speed of CMOS inverter and Ring Oscillator is analyzed for the first time using Triple-Metal-Gate (TMG) Recessed-Source/Drain (Re-S/D) SOI MOSFET. Re-S/D SOI MOSFET has the capability to reduce the series resistance of the device due to the extended depth of source and drain into buried oxide layer. So the current drive capability of this device is improved which in turn improves the input/output switching in the inverter and ring oscillator. In this paper, transfer characteristics, delay and frequency is analyzed for inverter as well as for ring oscillator with TMG Re-S/D SOI MOSFET. DC and transient analysis such as transfer characteristics, noise margin, power dissipation, delay, and frequency is done for CMOS inverter and ring oscillator. Also, the Voltage Transfer Characteristic (VTC) has been compared with the available SMG and DMG structures of Re-S/D FD SOI MOSFET for the analysis switching behavior. This DC and transient simulation are performed using 2-dimensional numerical TCAD simulator ATLAS from Silvaco.

Total Ionizing Dose Effect on Ring Oscillator Frequency in 28-nm FD-SOI Technology

The total ionizing dose (TID) is a mechanism that threatens the reliability of transistors under radiation. In the literature, we found contradictory TID experimental results between device and circuit studies of fully depleted silicon-on-insulator (FD-SOI) technology. To resolve that conflict, we designed a special ring oscillator (RO) circuit in which the n-FET and p-FET gate-potentials can be programmed. The RO circuits were fabricated using 65-nm bulk-CMOS and 28-nm FD-SOI foundry baseline technologies and were dosed with 60Co gamma radiation up to 200 krad (SiO2). In addition, we measured drive current variations in the 28-nm FD-SOI after irradiation. Traditionally, there has been a belief that the TID of n-FETs is more dominant than that of p-FETs. However, we found that in FD-SOI, the TID effect of p-FET governs circuit performance degradation.

Realization and AC modeling of electronic circuits with water-gated field effect transistors (WG-FETs) based on gate probe distance

We present AC modeling of WG-FET devices based on gate probe distance. Small- and large-signal models are proposed. It is shown that unity gain frequency is inversely proportional to gate distance. Also, common source amplifier, inverter, and ring oscillator circuits are fabricated with WG-FET devices, which use 16 nm-thick mono-Si film as channel layer, for the first time. Circuit simulations are performed based on AC models. Results are verified with experimental measurements using de-ionized (DI) water. For common source amplifier, fUG is measured as 21 Hz for 2 mm gate distance, and it is increased to 1.2 kHz when gate distance is decreased to 200 μm. For inverter, rail-to-rail operation is observed with tPLH of 24 ms and tPHL of 58 ms for 1 square-wave input signal at 1 Hz. Gain is measured as −11 V/V at switching threshold. Ring oscillator is realized with five inverters. A square-wave output signal with amplitude of 840 and frequency of 2.6 Hz is obtained. AC modeling of WG-FET enables realization of advanced circuits which are inherently compatible with fluidic systems. Therefore, they can be valuable assets especially in microfluidic applications.

Duty-Cycle-Based Controlled Physical Unclonable Function

Physical unclonable functions (PUFs) provide a unique signature based on the variations during the fabrication process of the integrated circuits. The additional features of controllability and reconfigurability to a PUF implementation enable the reuse of the existing hardware as a new modified PUF, enhancing the capabilities of a PUF for more versatile security applications. In this paper, a variable duty-cycle-based ring oscillator circuit is proposed as a controlled and reconfigurable PUF primitive. One of the distinguishing features of the proposed PUF is that duty cycle comparisons are used, instead of the conventional frequency comparisons to generate the output bit response. The advantages of the utilizing duty cycle over the conventional frequency-based comparisons are investigated. The feasibility of the proposed PUF is evaluated using existing figures of merit providing a uniqueness of 49.3%, temperature reliability greater than 92% between 0 and 100 °C, and supply voltage reliability greater than 96% between 0.9 and 1 V.

Printed Organic Complementary Inverter with Single SAM Process Using a p-type D-A Polymer Semiconductor

The demonstration of the complementary integrated circuit using printing processes is indispensable for realizing electronic devices using organic thin film transistors. Although complementary integrated circuits have advantages such as low power consumption and a wide output voltage range, complementary integrated circuits fabricated by the printing method have problems regarding driving voltage and performance. Studies on fabrication processes of electronic circuits for printing technology, including optimization and simplification, are also important research topics. In this study, the fabrication process of the printed complementary integrated circuit was simplified by applying a p-type donor-acceptor (D-A) polymer semiconductor, which is not strongly affected by the electrode work function. An inverter circuit and the ring oscillator circuit were demonstrated using this process. The fabricated ring oscillator array showed excellent performance, with low voltage operation and low performance variation.

Frequency equation for the submicron CMOS ring oscillator using the first order characterization

By utilizing the first order behavior of the device, an equation for the frequency of operation of the submicron CMOS ring oscillator is presented. A 5-stage ring oscillator is utilized as the initial design, with different Beta ratios, for the computation of the operating frequency. Later on, the circuit simulation is performed from 5-stage till 23-stage, with the range of oscillating frequency being 3.0817 and 0.6705 GHz respectively. It is noted that the output frequency is inversely proportional to the square of the device length, and when the value of Beta ratio is used as 2.3, a difference of 3.64% is observed on an average, in between the computed and the simulated values of frequency. As an outcome, the derived equation can be utilized, with the inclusion of an empirical constant in general, for arriving at the ring oscillator circuit’s output frequency.

Networked hardware assisted key image and chaotic attractors for secure RGB image communication

In multimedia communication, significance of the images for data representation is noteworthy. In this context, secure transmission of images over open channel has become a challenging task. Creation of different strategies in improving the secure image transmission always has a demand. The proposed work suggests an RGB image encryption with the confluence of attractors and hardware triggered key image in which confusion and diffusion were accomplished by Lorenz, Lu and Cellular Automata attractors. The uniqueness of proposed encryption scheme is a key image generation module through cascaded Ring Oscillator circuit which creates M × N key image for diffusion of pixels. Facilitating the authenticated networked access to key image generation hardware enables the secure server-client architecture for a variety of secure image transfer applications. The proposed approach is a hardware – software codesign which possesses a good keyspace, improved key sensitivity and satisfies the various statistical parameters thus offering substantial resistance to differential, occlusion and chosen plaintext attacks on RGB images.

Impact of Process Variations on Negative Capacitance FinFET Devices and Circuits

We report on the impact of process variations on short-channel negative capacitance (NC)-based FinFETs through statistical Monte Carlo simulations using a physics-based model of NC-FinFETs. We find that relative to regular FinFETs, the impact of geometrical variability can be lesser or higher in NC-FinFETs in different regimes of device operation and is strongly dependent on the nominal ferroelectric (FE) thickness ( ${t}_{\text{fe}}$ ). The contribution of the FE layer to the overall variability behaves non-monotonically with increase in the nominal ${t}_{\text {fe}}$ . While the OFF-current and threshold voltage variabilities scale down, the ON-current variability does not follow a monotonic trend with increase in the nominal ${t}_{\text{fe}}$ . We also show that although relative to the regular FinFET-based ring oscillator (RO) circuit, the NC-FinFET-based RO (NC-RO) circuit displays increased immunity to process variation induced delay variability, the trend is non-monotonic with regard to ${t}_{\text{fe}}$ scaling.

Device Process and Circuit Application Interaction for Harsh Electronics: Hf–In–Zn–O Thin Film Transistors as an Example

The effects of Hf content on the radiation hardness of Hf–In–Zn–O thin-film transistors (HIZO TFTs) and HIZO TFT-based circuits are systemically examined. The evaluated circuits, including current-starved ring oscillator, energy harvesting, and RF circuits, are essential for space electronic systems. It is shown that HIZO TFTs with low Hf concentration have better initial performance while TFTs with high Hf concentration are more stable against radiation. On the other hand, for circuit application, the stable HIZO TFTs are not necessarily preferred for all circuits. This letter demonstrates that understanding the device-circuit interactions is necessary for device optimization and circuit reliability improvements for harsh electronic systems.

A Nano-Electro-Mechanical Switch Based Power Gating for Effective Stand-by Power Reduction in FinFET Technologies

In this letter, we show that using the experimentally demonstrated nano-electro-mechanical-switches (NEMS) and our design methodology, the standby power dissipation can be reduced to negligible levels in 14-nm bulk FinFET technologies. Using two realistic NEMS structures, demonstrated in the literature for power gating applications, a design window is derived for achieving the targeted specifications without compromising on the performance and area. Cantilever NEMS requires less area as compared with the suspended NEMS, but reliability is a concern. We demonstrate that for a 17-stage ring oscillator circuit, the NEMS power gating will perform better than the FinFET-based power gating when the ${T}_{\mathrm{\scriptscriptstyle ON}}/{T}_{\mathrm{\scriptscriptstyle OFF}}$ ratio is less than 0.002.

Performance evaluation metrics for ring-oscillator-based temperature sensors on FPGAs: A quality factor

Due to the aggressive scaling of process technologies, ultra-logic densities on integrated circuits, and also the complexity of designs, which in turn lead to a drastic increase of power density, thermal issues have become a bottleneck in electronics designs, result in a new focus for much researches over last years. To address this issue, various dynamic thermal management (DTM) techniques have been proposed to maintain the operation of systems safe and reliable. To effectively apply DTM techniques, providing a precise and reliable network of temperature sensors is highly required to measure local temperatures and provide an accurate thermal map of the chip. While many designers have utilized ring-oscillator (RO) circuits as temperature sensors in a network for measuring the thermal distribution and predicting the thermal behavior of a field programmable gate array (FPGA), a high-level study of the temperature sensors' design space is still missing. In this paper, a novel concept of the RO-based temperature sensor based on four basic evaluation metrics is presented. We introduce four useful evaluation metrics (i.e. the area, thermal, and power overheads, and thermal map error) and some measurement methods for exploring and comparing the relative performance of different temperature sensor's designs. Then, in order to make an optimal choice based on the metrics obtained, we propose a figure of merit (FOM) to characterize the efficiency of these designs. The proposed performance evaluation metric, the quality factor (QF), is based on the overheads and measurement accuracy trade-offs between different designs of the RO-based temperature sensor. Consequently, the proposed QF metric is a quantity value representing a measure of effectiveness, efficiency, and performance of a temperature sensor network, which can help the designer to make a proper decision. Moreover, in this work, a compact and ultra-sensitive RO-based temperature sensor is presented that utilizes only 5 look-up tables (LUTs), occupies 37.5% fewer resources than the most compact sensor, and provides 2.72 times higher sensitivity than the best sensitive design. Also, in this paper, several designs of the RO-based temperature sensor are explored in a network, in terms of various sensor's configurations, RO length, and counter width, and compared with each other in order to investigate their influences on the efficiency of the sensor network. According to the QF metric and experimental results, the sensor network based on the proposed sensor has the best efficiency among other alternative designs.

Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction

Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS technologies for digital, analogue and RF designs. However, it has been demonstrated by several researchers that TFET circuits face increased on-state Miller capacitance effect, which leads to poor transient characteristics with large overshoots and undershoots. This would minimise the reliability of TFET circuits though energy efficient. This work gives more design insights (optimal sizing, number of stages, supply voltage) into TFET circuit reliability and proposes a TFET based circuit interaction design approach for ultra-low power and reliable ring oscillator circuit design. It has been shown that TFET circuit designs without proper reliability enhancement techniques such as circuit interaction or co-design approach exhibits very large undershoots/overshoots (∼20–50%). The proposed TFET circuit co-design approach (i.e. differential topology based design in comparison with the complementary static TFET logic designs) enhances the TFET circuit reliability by minimising the undershoots/overshoots to less than 0.5% with a trade-off in operating frequency and power consumption.

A Compact SPICE Model for Organic TFTs and Applications to Logic Circuit Design

This work introduces a compact DC model developed for organic thin film transistors (OTFTs) and its SPICE implementation. The model relies on a modified version of the gradual channel approximation that takes into account the contact effects, occurring at nonohmic metal/organic semiconductor junctions, modeling them as reverse biased Schottky diodes. The model also comprises channel length modulation and scalability of drain current with respect to channel length. To show the suitability of the model, we used it to design an inverter and a ring oscillator circuit. Furthermore, an experimental validation of the OTFTs has been done at the level of the single device as well as with a discrete-component setup based on two OTFTs connected into an inverter configuration. The experimental tests were based on OTFTs that use small molecules in binder matrix as an active layer. The experimental data on the fabricated devices have been found in good agreement with SPICE simulation results, paving the way to the use of the model and the device for the design of OTFT-based integrated circuits.

Efficient Modeling of Distributed Dynamic Self-Heating and Thermal Coupling in Multifinger SiGe HBTs

In this paper, we propose an efficient model for dynamic self-heating and thermal coupling in a multifinger transistor system. Essentially, the proposed model is an improvement over a state-of-the-art existing model from the viewpoint of simulation time. Verilog-A implementation of the proposed model does not require to use any voltage controlled voltage source. In a multifinger transistor system, with $n$ emitter fingers, our model uses $3n$ extra nodes in Verilog-A implementation whereas it is $2n^{2}-n$ for the state-of-the-art model. Note that our model requires no extra nodes for implementing the thermal coupling effects. We present that the transient simulation results of our model are identical with those of the state-of-the-art model. Electrothermal simulation using the proposed thermal model shows good agreement with the measured data. It is found that the proposed model simulates more than 40% faster compared with the existing model for a ring oscillator circuit.

A Review on MOSFET-Like CNTFETs

Carbon Nanotube Field Effect Transistor (CNTFET) is one of the promising devices for future nanoscale technologies. In this paper, we have studied the drain characteristics of MOSFET-like CNTFETs for different device parameters like, channel length, diameter of CNT, and number of tubes. It is shown that these device parameters can be used to make important design decisions while designing nanoelectronic circuits. A buffer and ring oscillator circuits are designed using the MOSFET-like CNTFET and propagation delay, power, and power-delay-product (PDP) values are calculated and compared with the CMOS based designs. Also, the CNTFET technology based SRAM cell is compared with CMOS technology based SRAM in term of power consumption. We have shown that CNTFET can exhibit better performance in the nanoscale regime as compared to its CMOS counterparts.

Ring Oscillators Based on ZnO Channel JFETs and MESFETs

Ring oscillator circuits based on junction field‐effect transistors as well as metal–semiconductor field‐effect transistors with ZnO channels are presented. Single stage delay times down to 110 ns are observed. The experimental oscillation frequencies are related to easily measurable device properties by a simple analytical model. This work proves the feasibility of low power oxide based circuits with Schottky diode and bipolar (pn‐) diode gates since both approaches provide significantly lower operation voltages at similar frequencies compared to previously reported oxide thin film transistors based on insulating gates.

Ultraflexible and ultrathin polymeric gate insulator for 2 V organic transistor circuits

We have developed a high-yield process for fabricating organic transistors with ultraflexible and ultrathin polymeric (parylene) insulators. In a top-contact bottom-gate configuration, an oxygen plasma treatment for a Au gate surface before parylene deposition significantly improved the yield of transistors, enabling the parylene thickness to be reduced to 18 nm. Taking full advantage of the ultraflexible and ultrathin insulator, we have demonstrated 2 V ring oscillator circuits, where the yield was 97% for 360 transistors inside the area of 7 × 7 cm2. The highly reliable ultrathin insulator is useful for large-area circuits with low-voltage organic transistors.

Voltage-Controlled Ring Oscillators Based on Inkjet Printed Carbon Nanotubes and Zinc Tin Oxide.

A voltage-controlled ring oscillator is implemented with double-gate complementary transistors where both the n- and p-channel semiconductors are deposited by inkjet printing. Top gates added to transistors in conventional ring oscillator circuits control not only threshold voltages of the constituent transistors but also the oscillation frequencies of the ring oscillators. The oscillation frequency increases or decreases linearly with applied top gate potential. The field-effect transistor materials system that yields such linear behavior has not been previously reported. In this work, we demonstrate details of a material system (gate insulator, p- and n-channel semiconductors) that results in very linear frequency changes with control gate potential. Our use of a double layer top dielectric consisting of a combination of solution processed P(VDF-TrFE) and Al2O3 deposited by atomic layer deposition leads to low operating voltages and near-optimal device characteristics from a circuit standpoint. Such functional blocks will enable the realization of printed voltage-controlled oscillator-based analog-to-digital converters.