RHBD Techniques Research Articles

A CMOS 12-Bit 3MS/s Rad-Hard Digital-to-Analog Converter Based on a High-Linearity Resistor String Poly-Matrix

This work presents a rad-hard 12-bit 3 MS/s resistor string DAC for space applications. The converter has been developed using rad-hardened techniques both at architecture and layout levels starting from a conventional topology. The design considers the different effects of the radiation that could damage the circuits in space environments. The DAC has been developed and integrated a standard CMOS 0.13 μm technology by IHP, using RHBD techniques. Low Earth Orbit (LEO) requires a TID value of around 100 krad (Si), according to the expected length of the mission. The temperature range is between −55 °C and 125 °C. The DAC power budget is similar to that of terrestrial applications. The measured INL (Integral Non-Linearity) and DNL (Differential Non-Linearity) are better than 0.2 LSB, while the ENOB (Effective Number Of Bits) at a 3 MS/s clock exceeds 9.7 bits while loading a 10 pF capacitor. The DAC has been characterized under radiation, showing a fluctuation in the analog output lower than 2 LSB (mainly due to measurement uncertainty) up to 500 krad (Si). Power consumption shows a negligible increase, too. A 10-bit version of the same DAC as the downscaled 12-bit one has been developed as well.

Exploiting Transistor Folding Layout as RHBD Technique Against Single-Event Transients

Radiation-hardening techniques can be extensively used in the design level to improve the robustness of very large-scale integration (VLSI) circuits used in space applications. Accordingly, this work analyzes the efficiency of transistor folding layout in improving the single-event transient (SET) robustness of digital circuits. Additionally, diffusion splitting is proposed to reduce the area overhead of multiple-finger designs. Besides increasing threshold linear energy transfer, results show that both techniques can also reduce the overall cross section and the in-orbit SET rate for protons and heavy ions in low-earth orbit (LEO) and international space station (ISS) orbits.

RHBD Techniques to Mitigate SEU and SET in CMOS Frequency Synthesizers

This paper presents a thorough study of radiation effects on a frequency synthesizer designed in a 0.18 μ m CMOS technology. In CMOS devices, the effect of a high energy particle impact can be modeled by a current pulse connected to the drain of the transistors. The effects of SET (single event transient) and SEU (single event upset) were analyzed connecting current pulses to the drains of all the transistors and analyzing the amplitude variations and phase shifts obtained at the output nodes. Following this procedure, the most sensitive circuits were detected. This paper proposes a combination of radiation hardening-by-design techniques (RHBD) such as resistor–capacitor (RC) filtering or local circuit-redundancy to mitigate the effects of radiation. The proposed modifications make the frequency synthesizer more robust against radiation.

The orientational dependence of single event upsets and multiple-cell upsets in 65 nm dual DICE SRAM

The impact of different orientational angle of ion incidence on SEU and MCU are studied in dual DICE SRAM according to directionality of different sensitive pairs. The results show the worst orientational angle for SEU and MCU in dual DICE SRAM is incident with large tilting angle along the well even if nodal spacing of N/P sensitive pairs is the smallest. Ion tilt incidence with this orientational angle will greatly decrease SEU threshold and increase SEU cross section. At high LET, SEU saturation cross-sections in dual DICE design only has a small improvement by 40% over 6-T design whether ion incidence is normal or tilt due to charge sharing. Based on MCU topological pattern in dual DICE and 6-T design, the extent of charge diffusion and pararistic bipolar effect is quantified. Implications and application of the results for heavy ion SEU testing and RHBD technique in nanometer technology are presented.

Single event transients mitigation techniques for CMOS integrated VCOs

Single event transients (SETs) in analog integrated circuits result from the interaction of a heavy ion or high-energy proton with a sensitive p-n junction. SETs induce electron-hole pairs that can lead to current spikes, which propagate through the integrated circuit and can result in substantial transient peaks at the output voltage. This paper proposes techniques to mitigate SETs in CMOS voltage controlled oscillators (VCOs) without affecting circuit specifications. A VCO was designed to meet the IEEE 802.15.4 specifications. First, the weakest nodes were detected, and then particle strikes with a LET ranging from 14.47 to 57.86 MeV cm2 mg−1 were applied at these nodes. Amplitude variation, recovery time and phase shift were obtained at the output nodes. RHBD techniques are discussed and applied to redesign the VCO. The proposed mitigation techniques reduce the recovery time by approximately 59%, the output phase displacement by 74.2% and the amplitude variation by 96.7%.

Heavy-Ion Micro Beam and Simulation Study of a Flash-Based FPGA Microcontroller Implementation

Flash-based FPGAs are frequently used in space applications and it is now common for such designs to include a small microcontroller. In this paper, we present the results of a detailed study of two implementations of an ARM® Cortex®-M0+ processor. The first implementation uses a standard design flow while the second implementation is protected with RHBD techniques including TMR flip-flops. Both designs were tested using a heavy-ion micro-beam using a methodology which enables individual ions to be localized both in space and time. The rate of silent data corruption (SDC) was only reduced by 5x in the protected version. Many, but not all, of the error scenarios were reproduced using simulation based fault injection. Overall, the results suggest that the contribution of single event transients (SETs) can not be neglected and the results show the limitations of flip-flop based TMR.

Analysis and RHBD technique of single event transients in PLLs

Single-event transient susceptibility of phase-locked loops has been investigated. The charge pump is the most sensitive component of the PLL to SET, and it is hard to mitigate this effect at the transistor level. A test circuit was designed on a 65 nm process using a new system-level radiation-hardening-by-design technique. Heavy-ion testing was used to evaluate the radiation hardness. Analyses and discussion of the feasibility of this method are also presented.

The off-state gate isolation technique to improve ASET tolerance in differential analog design

A novel off-state gate RHBD technique to mitigate the single-event transient (SET) in the differential data path of analog circuit is demonstrated in this paper. Simulation results present that this off-state gate technique could exploit charge sharing in differential circuits and reduce differential mode voltage perturbation effectively. It is indicated that this technique is more effective to mitigate SET than the differential charge cancellation (DCC) technique with less penalty.

RHBD Technique for Single-Event Charge Cancellation in Folded-Cascode Amplifiers

A novel RHBD technique that exploits charge sharing is implemented in the single-ended gain stage of a folded-cascode operational amplifier to mitigate single-event transients (SETs). The efficacy of the technique is demonstrated via two-photon laser experiments. Using settling time as the primary metric for SET severity, the proposed layout technique achieves sensitive area reductions ranging from 41% to 95% with an overall area penalty of less than 1%.

Differential Charge Cancellation (DCC) Layout as an RHBD Technique for Bulk CMOS Differential Circuit Design

A novel RHBD technique utilizing charge sharing to mitigate single-event voltage transients in differential circuits is demonstrated experimentally. Differential charge cancellation (DCC) layout leverages the inherent common-mode rejection of differential circuits to mitigate voltage transients induced by ion strikes. A simple layout variation transforms normally single-ended error signals into common-mode signals that are mitigated by the differential signal path. This layout change maintains the matching achieved via a standard common-centroid layout but incurs negligible area penalty.

Single-Event-Hardened CMOS Operational Amplifier Design

Novel RHBD techniques are described that utilize charge sharing to mitigate single-event voltage transients in a folded cascode operational amplifier. These techniques are analyzed using a new layout aware single-event model with the Cadence Spectre circuit simulator. The techniques are applied in each of the three stages of an operational amplifier (op amp). The sensitive node active charge cancellation (SNACC) technique is applied to the bias circuit and extended to protect multiple sensitive nodes. This technique is shown to provide a 5X reduction in error energy measured at the amplifier output at the cost of increased sensitive area. The differential input stage and the high-gain single-ended cascode output stage of the amplifier are hardened using differential charge cancellation (DCC) layout techniques that promote charge sharing. These hardening techniques are shown to provide up to orders of magnitude reductions in single-event error energies as measured at the op amp output and reductions in sensitive area of more than 15% across all LETs simulated.

Non-TMR SEU-Hardening Techniques for SiGe HBT Shift Registers and Clock Buffers

We report new results from both broad-beam, heavy-ion and proton experiments for circuit-level RHBD techniques in SiGe digital logic. Redundant circuit elements within the latches are used to significantly reduce single-event upset rates in shift registers and clock paths, without resorting to TMR techniques.

Proton-induced SEU in SiGe digital logic at cryogenic temperatures

We present the first experimental results confirming the increased SEE sensitivity of SiGe digital bipolar logic circuits operating in a 63 MeV proton environment at cryogenic temperatures. A 3× increase in both the error-event and bit-error cross sections is observed as the circuits are cooled from 300 K to 77 K, with error signature analyses indicating corresponding increases in the average number of bits-in-error and error length over data rates ranging from 50 Mbit/s to 4 Gbit/s. Single-bit-errors dominate the proton-induced SEU response at both 300 K and 77 K, as opposed to the multiple-bit-errors seen in the heavy-ion SEU response. Temperature dependent substrate carrier lifetime measurements, when combined with calibrated 2 D DESSIS simulations, suggest that the increased transistor charge collection at low temperature is a mobility driven phenomenon. Circuit-level RHBD techniques are shown to be very efficient in mitigating the proton- induced SEU at both 300 K and 77 K over the data rates tested. These results suggest that the circuit operating temperature must be carefully considered during component qualification for SEE tolerance and indicate the need for broad-beam heavy-ion testing at low temperatures.

An Evaluation of Transistor-Layout RHBD Techniques for SEE Mitigation in SiGe HBTs

We investigate transistor-level layout-based techniques for SEE mitigation in advanced SiGe HBTs. The approach is based on the inclusion of an alternate reverse-biased pn junction (n-ring) designed to shunt electron charge away from the sub-collector to substrate junction. The inclusion of the n-ring affects neither the DC nor AC performance of the SiGe HBT and does not compromise its inherent multi-Mrad TID tolerance. The effects of ion strike location and angle of incidence, as well as n-ring placement, area, and bias on charge collection are investigated experimentally using a 36 MeV O2 microbeam. The results indicate that charge shunting through the n-ring can result in up to a 90% reduction in collector collected charge for strikes outside the DT and a 18% reduction for strikes to the emitter center. 3-D transient strike simulations using NanoTCAD are used to verify the experimental observations, as well as shed insight into the underlying physical mechanisms. Circuit implications for this RHBD technique are discussed and recommendations made.

RHBD techniques for mitigating effects of single-event hits using guard-gates

Hardening-by-design techniques to mitigate the effect of single-event transients (SET) using guard-gates are developed. Design approaches for addressing combinational logic hits and storage cell hits are presented. Simulation results show that the designs using guard-gates are less susceptible to single-event hits. Area, power, and speed penalty for guard-gate designs for combinational logic are found to be minimal. For latches, the area penalty is higher but speed penalty is minimal.