RF Transconductance Research Articles

Design and Analysis of a Highly Efficient Linearized CMOS Subharmonic Mixer for Zero and Low-IF Applications

This paper presents the distortion analysis of a linearized CMOS subharmonic mixer (SHM) based on a Volterra series analysis. The second- and third-order intermodulation distortions are reduced by a modified second-harmonic reinjection in the RF transconductance stage. An injected IM2 is mixed with an RF input signal and generates an IM3 signal with the same amplitude and opposite phase of a main path for the cancellation of the intrinsic IM3 signal. In order to cancel the second-order intermodulation component, a signal with the same IM2 amplitude and opposite phase of the main path is generated. Closed-form expressions of the conversion gain along with the second-and third-order distortions are derived using a Volterra series analysis to facilitate an optimal design and provide an insight into the nonlinearity of SHM. An inductive connection between RF and local oscillator stages implementing a $\pi $ -network is employed to improve the linearity and enhance the gain and bandwidth of the mixer. Simulation results performed in Taiwan Semiconductor Manufacturing Company 0.18- $\mu \text{m}$ CMOS process at 2.4-GHz RF frequency and 1.6 V supply voltage. The results show that the proposed mixer without the $\pi $ -network, in comparison with the conventional mixer, exhibits up to 15 and 14 dB improvements in IIP2 and IIP3, respectively. The improvements obtained over 1–20 MHz two-tone spacing range without gain reduction or noise penalty. Moreover, in the presence of the $\pi $ -network, the mixer exhibits up to 25 and 7 dB improvements in IIP2 and IIP3, respectively; the gain, bandwidth, and noise figure are also improved. The simulation results demonstrate good accuracy in comparison with the analytical results.

RF Transconductor Linearization Robust to Process, Voltage and Temperature Variations

Software-defined radio receivers increasingly exploit linear RF V-I conversion, instead of RF voltage gain, to improve interference robustness. Unfortunately, the linearity of CMOS inverters, which are often used to implement V-I conversion, is highly sensitive to Process, Voltage and Temperature variations. This paper proposes a more robust technique based on resistive degeneration. To mitigate third-order IM3 distortion induced by the quadratic MOSFET I-V characteristic, a new linearization technique is proposed which exploits a floating battery by-pass circuit and replica biasing to improve IIP3 in a robust way. This paper explains the concept and analyzes linearity improvement. To demonstrate operation, an LNTA with current domain mixer is implemented in a 45 nm CMOS process. Compared to a conventional inverter based LNTA with the same transconductance, it improves IIP3 from 2 dBm to a robust P IIP3 of 8 dBm at the cost of 67% increase in power consumption.

Second harmonic rejection based on feedback technique in CMOS mixer for multi-band DCR application

This paper presents a broadband linearization technique for CMOS Gilbert-based mixer in zero IF receivers. In the proposed mixer the second order distortion is reduced by using feedback technique in the RF transconductance stage. Creating a negative feedback loop is better suited for achieving broadband IIP2 improvement compared to other technique. Moreover, the added circuit increases the conversion gain of the mixer. Simulation results, using 0.13 μm CMOS TSMC model, show that the proposed technique improves IIP2 of more than 20 dB in the 900 MHz---6 GHz RF input frequency rang for 100 MHz output bandwidth in comparison with the conventional mixer. So this technique is suitable for multi-band DCR application. The total power consumption is 3.3 mW and the excess power consumption due to additional circuits used to implement cancellation mechanism is less than 1 mW.

High performance AlGaN/GaN HEMTs with AlN/SiNx passivation**Project supported by the National Natural Science Foundation of China (No. 60890192).

AlGaN/GaN high electron-mobility transistors (HEMTs) with 5 nm AlN passivation by plasma enhanced atomic layer deposition (PEALD) were fabricated, covered by 50 nm SiNx which was grown by plasma enhanced chemical vapor deposition (PECVD). With PEALD AlN passivation, current collapse was suppressed more effectively and the devices show better subthreshold characteristics. Moreover, the insertion of AlN increased the RF transconductance, which lead to a higher cut-off frequency. Temperature dependence of DC characteristics demonstrated that the degradations of drain current and maximum transconductance at elevated temperatures for the AlN/SiNx passivated devices were much smaller compared with the devices with SiNx passivation, indicating that PEALD AlN passivation can improve the high temperature operation of the AlGaN/GaN HEMTs.

Codesign of Mixer-VGA Downconverter Blocks

Two radio frequency integrated circuit (RFIC) downconverters are presented, each consisting of an active mixer and a variable gain amplifier (VGA). The downconverter blocks (DCBs) have identical mixing stages but different VGA topologies. The mixers use a commutating switching network and a low-noise RF transconductance stage to reduce the system noise figure (NF). VGA gain control in one DCB (DCB-1) is done using a current-steering approach, while the second DCB (DCB-2) employs a transistor-based attenuator. Both RFICs were designed and fabricated using a standard 130-nm CMOS process and they were tested over the RF band covering 1-6 GHz and at an IF of 140 MHz. Measurements show that the conversion gain (CG) of DCB-1 ranges from 9.6 to 25.3 dB, and for DCB-2, the CG ranges from 10.7 to 23.7 dB. The minimum double-sideband NF for both the downconverters is 3.8 dB but their maximum NFs are different: 1) 14.2 dB for DCB-1 and 2) 11.5 dB for DCB-2.

A 75–85 GHz down‐conversion mixer with integrated Marchand baluns in 90 nm CMOS with excellent matching and port‐to‐port isolation for automotive radars

ABSTRACTA 75–85 GHz double‐balanced down‐conversion mixer for automotive radars using standard 90 nm CMOS technology is reported. The down‐conversion mixer comprises a double‐balanced Gilbert cell with inductive source‐degeneration RF transconductance stage for RF‐port input matching bandwidth and conversion gain (CG) enhancement, a Marchand balun for converting the single RF input signal to differential signal, a Marchand balun for converting the single LO input signal to differential signal, and a baseband amplifier. The mixer consumes 13 mW and achieves excellent RF‐port input reflection coefficient of −13.1 to −19.4 dB and LO‐port input reflection coefficient of −9.1 to −11.8 dB for frequencies of 75–85 GHz. In addition, for frequencies of 75–85 GHz, the mixer achieves CG of −1 to 1.5 dB, LO‐RF isolation of 43.5–49.2 dB, LO‐IF isolation of 56.5–64.5 dB and RF‐IF isolation of 35.9–39.4 dB, one of the best CG and port‐to‐port isolation results ever reported for a CMOS down‐conversion mixer with operation frequency around 80 GHz. Furthermore, the mixer achieves an excellent input third‐order intercept point of 2.7 dBm at 79 GHz. These results demonstrate the proposed down‐conversion mixer architecture is promising for W‐band transceivers. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:73–80, 2015

RF and DC Analysis of Stressed InGaAs MOSFETs

A complete reliability study of the DC and RF characteristics for InGaAs nMOSFETs with Al2O3/HfO2 dielectric is presented. The main stress variation at high frequencies is related to a threshold voltage shift, whereas no decrease is found in the maximum of the cutoff frequency and RF transconductance. Constant gate stress leads to a charge build up causing a threshold voltage shift. Furthermore, electron trapping at the drain side degrades the performance after hot carrier stress. The maximum DC transconductance is reduced following constant gate bias stress, by an increase in charge trapping at border defects. These border defects at the channel/high-κ interface are filled by cold carrier trapping when the transistor is turned on, whereas they do not respond at high frequencies.

(Invited) Extraction of Oxide Traps in III-V MOSFETs Using RF Transconductance Measurements

We here present simulations of the effect of border traps on the behavior of a III-V FET's transconductance with respect to frequency. We also compare simulations with a recently developed analytical model for extracting the border trap distribution through measurements of the transconductance, find good agreement between the extracted and simulated transconductance.

Design of a Low-Voltage and Low-Distortion Mixer Through Volterra-Series Analysis

The factors that impact the intermodulation distortion performance of an active downconverting mixer are investigated. Through a Volterra-series analysis of the RF transconductor stage of the mixer, design principles are formulated to maximize the mixer's IIP3. To verify the theoretical analysis, a 0.3-1.2-GHz low-voltage mixer operating from a 0.9-V supply was designed, fabricated, and tested. The mixer employs a common-gate common-source RF transconductor stage with simultaneous distortion and noise cancellation. Experimental results reveal that the mixer can yield an IIP3 of - 0.8 dBm, a double-sideband noise figure below 4.8 dB, and a maximum conversion gain of 8.8 dB.

Design and Analysis of a 21–29-GHz Ultra-Wideband Receiver Front-End in 0.18-$\mu$m CMOS Technology

This paper reports the design and analysis of 21-29-GHz CMOS low-noise amplifier (LNA), balun and mixer in a standard 0.18-μm CMOS process for ultra-wideband automotive radar systems. To verify the proposed LNA, balun, and mixer architectures, a simplified receiver front-end comprising an LNA, a double-balanced Gilbert-cell-based mixer, and two Marchand baluns was implemented. The wideband Marchand baluns can convert the single RF and local oscillator (LO) signals to nearly perfect differential signals over the 21-29-GHz band. The performance of the mixer is improved with the current-bleeding technique and a parallel resonant inductor at the differential outputs of the RF transconductance stage. Over the 21-29-GHz band, the receiver front-end exhibits excellent noise figure of 4.6±0.5 dB, conversion gain of 23.7±1.4 dB, RF port reflection coefficient lower than -8.8 dB, LO-IF isolation lower than -47 dB, LO-RF isolation lower than -55 dB, and RF-IF isolation lower than -35.5 dB. The circuit occupies a chip area of 1.25×1.06 mm2, including the test pads. The dc power dissipation is only 39.2 mW.

A Low-Voltage, Low-Power, and Low-Noise UWB Mixer Using Bulk-Injection and Switched Biasing Techniques

This paper presents a low-voltage, low-power, low-noise, and ultra-wideband (UWB) mixer using bulk-injection and switched biasing techniques. The bulk-injection technique is implemented for a low supply voltage, thus resulting in low power consumption. This technique also allows for a flat conversion gain over a wide range of frequencies covering the full UWB band; this is a result of the integration of the RF transconductance stage and the local oscillator switching stage into a single transistor that is able to eliminate parasitic effects. Moreover, since the bulk-injection transistors of the mixer are designed to operate in the subthreshold region, current dissipation is reduced. A switched biasing technique for the tail current source, in place of static biasing, is adopted to reduce noise. The effects of modulated input signals, such as AM and FM, are simulated and measured to demonstrate the robustness of the switched biasing technique. The proposed mixer offers a measured conversion gain from 7.6 to 9.9 dB, a noise figure from 11.7 to 13.9 dB, and input third-order intercept point from - 10 to - 15.5 dBm, over 2.4 to 11.9 GHz, while consuming only 0.88 mW from a 0.8-V supply voltage. The chip size including the test pads is 0.62×0.58 mm2 using a 0.18-μm RF CMOS process.

A 1-V 5-GHz Self-Bias Folded-Switch Mixer in 90-nm CMOS for WLAN Receiver

A 5 GHz double balanced mixer (DBM) is implemented in standard 90 nm CMOS low-power technology. A novel low-voltage self-bias current reuse technique is proposed in the RF transconductance stage to obtain better third-order intermodulation intercept point (IIP3 ) and conversion gain (CG) when considering the process variations. The DBM achieves a CG of 12 dB, a noise figure (NF) of 10.6 dB and port-to-port isolations of better than 50 dB. The input second-order (IIP 2) and IIP 3 are 48 dBm and 4 dBm, respectively. Two I/Q DBMs are then integrated with a differential low-noise amplifier (DLNA) and a poly-phase filter, to from a direct-conversion receiver (DCR). The DCR achieves a CG of 26 dB with an NF of 2.7 dB at 21 mW power consumption from a 1 V supply voltage. The port-to-port isolations are better than 50 dB. The IIP2 and the IIP3 of the DCR are 33 dBm and -12 dBm, respectively.

A 60 GHz Current-Reuse LO-Boosting Mixer in 90 nm CMOS

This letter presents a 60 GHz direct down-conversion mixer in a 90 nm CMOS. The mixer consists of an RF transconductance stage, a switching stage, an LO amplification stage, a balun and a buffer amplifier, and employs a current-reuse LO-boosting technique for low power consumption with small LO input power. The measured conversion gain of the differential IF output is 12 dB at an input LO power of -13 dBm. The mixer consumes 8.8 mW and the measured 3 dB IF bandwidth is greater than 1.2 GHz. To the best of our knowledge, this mixer achieves the highest conversion gain with the lowest LO input power of all published 60 GHz band CMOS mixers.

An Ultra-Low-Voltage and Low-Power $\times$2 Subharmonic Downconverter Mixer

An 8.6 GHz <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\times$</tex> </formula> 2 subharmonic mixer with complementary current-reuse to enable ultra-low-voltage and low-power operation is presented. The RF transconductance stage of the mixer uses inductive source degeneration and the mixing core uses four transistors that are driven by a quadrature LO signal. A Volterra series analysis is carried out to determine the optimal gate biasing of the transconductor circuit to maximize the third-order intercept point <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$({\hbox{IIP}}_{3})$</tex></formula> performance of the RF stage and of the entire mixer. Experimental results show that the mixer has a conversion gain of 6.0 dB and an <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\hbox{IIP}}_{3}$</tex> </formula> of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 8.0 dBm. The entire circuit draws 0.6 mW from a 0.6 V supply. The chip was fabricated in a standard 130 nm CMOS process.

An Ultra-Low Voltage, Low-Noise, High Linearity 900-MHz Receiver With Digitally Calibrated In-Band Feed-Forward Interferer Cancellation in 65-nm CMOS

We present an ultra-low voltage, highly linear, low noise integrated CMOS receiver operating from a 0.6-V supply. The receiver incorporates programmable, in-band feed-forward interferer cancellation at the baseband to obtain high linearity and low noise operation at ultra-low supply voltages. Being able to reject adjacent channel or far-out blockers, the digitally calibrated interferer cancellation improves the IIP3 and IIP2 by more than 13 dB and 8 dB respectively with very little impact on the receiver noise figure. As such, it breaks the trade-off between linearity and noise figure, making it possible to use a high-gain RF front-end to achieve low noise figure without affecting the linearity of the ultra-low voltage baseband circuits. The 0.6-V 900-MHz direct-conversion receiver prototype integrates a differential LNA, RF transconductors, linear quadrature current driven passive mixers, feed-forward interferer cancellation circuits, baseband variable gain transimpedance amplifiers and second-order channel-select filters. It has a nominal conversion gain of 56.4 dB, noise figure of 5 dB, IIP3 of -9.8 dBm and IIP2 of 21.4 dBm. The receiver operates reliably from 0.55-0.65 V, consumes 26.4 mW and occupies an active area of 1.7 mm2 in a 65-nm low-power CMOS process, of which the feed-forward interferer cancellation circuits consume 11.4 mW and occupies 0.43 mm2 .

A 12 GHz-Bandwidth CMOS Mixer With Variable Conversion Gain Capability

A broadband downconverter mixer using an operational transconductance amplifier (OTA) in the RF transconductor stage is presented in this paper. By changing the OTA's transconductance through a dc control voltage, the mixer's conversion gain is varied. Experimental results show that the mixer's conversion gain can vary from 17 dB down to 1.2 dB over a 12 GHz bandwidth. The maximum IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> of the mixer is -3.7 dBm and its maximum IIP3 is + 8.6 dBm. Meanwhile, the maximum OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> is +7 dBm and the maximum OIP3 is +21 dBm. The circuit consumes a maximum of 5.9 mW of power from a 1.2 V supply. The chip occupies an area of 0.105 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> excluding bonding pads.

245-GHz InAlN/GaN HEMTs With Oxygen Plasma Treatment

We report lattice-matched In0.17Al0.83N/GaN high-electron mobility transistors on a SiC substrate with a record current gain cutoff frequency (fT). The key to this performance is the use of an oxygen plasma treatment to form a thin oxide layer on the InAlN barrier and to reduce the gate leakage current by more than two orders of magnitude. In addition, the RF transconductance (gm) collapse is reduced in the O2-treated devices, which results in a significant improvement in the fT . In a transistor with a gate length of 30 nm, an fT of 245 GHz is achieved, the highest value ever reported in GaN-based field-effect transistors.

Impact of the self-generated heat on the scalability of HEMTs

This work is aimed at studying the influence of the self-heating effect on the scalability of HEMTs from an experimental point of view. To accomplish that, we analyze the DC and microwave performance of devices having scaled gate widths. Our experimental results show that the DC transconductance does not scale linearly with the gate periphery under high power dissipation condition. The observed degradation of the transconductance in larger devices can be explained by a reduction of the average carrier velocity due to the occurrence of self-heating. Thermal phenomena even affect the RF small signal performance of the devices under test as they influence the DC operating point. Therefore, the RF transconductance and the forward transmission coefficient are degraded when the dissipated power increases so that all the self-generated heat cannot be completely removed.

Cancellation of second-order intermodulation distortion and enhancement of IIP2 in common-source and common-emitter RF transconductors

In this paper, a biasing technique for cancelling second-order intermodulation (IM2) distortion and enhancing second-order intercept point (IIP2) in common-source and common-emitter RF transconductors is presented. The proposed circuit can be utilized as an RF input transconductor in double-balanced downconversion mixers. By applying the presented technique, the achievable IIP2 of the mixer is limited by the linearity of the switching devices, component mismatches, and offsets. The proposed circuit has properties similar to the conventional differential pair transconductor in that it ideally displays no IM2 distortion. However, the presented circuit is more suitable for operation at low supply voltages because it has only one device stacked between the transconductor input and output. In the conventional differential pair, two devices consume the voltage headroom. The noise performance of the proposed transconductor is similar to the noise performance of the traditional common-source (emitter) and differential pair transconductors at given bias and device dimensions. On the other hand, the third-order intercept point (IIP3) of the presented transconductor is slightly higher than the IIP3 of the differential pair transconductor at given bias. Finally, the proposed circuit can also be employed as a current mirror, the ratio of which is very insensitive to the voltage swings at the gate or base of the current mirrored transistor.

Monolithic InGaP-GaAs HBT receiver front-end with 6 mW DC power consumption for 5 GHz band WLAN applications

A very low power consumption (6 mW) 5 GHz band receiver front-end using InGaP-GaAs HBT technology is reported. The receiver front-end is composed of a cascode low noise amplifier followed by a double-balanced mixer with the RF transconductor stage placed above the Gilbert quad for direct-coupled connection. The RF band of this receiver front-end is set to be 5.2 GHz, being downconverted to 1 GHz IF frequency. Input-return-loss (S11) in RF port smaller than −12 dB and excellent power-conversion-gain of 35.4 dB are achieved. Input 1 dB compression point (P1dB) and input third-order intercept point (IIP3) of −24 and −3 dBm, respectively, are also achieved.