RF Receiver Front-end Research Articles

9-GHz Wideband CMOS RX and TX Front-Ends for Universal Radio Applications

Wideband receiver (RX) and transmitter (TX) RF front-ends for wireless universal radio applications are presented. The RX is comprised of a two-stage low-noise amplifier (LNA) applying feedback and shunt peaking, a combiner buffer for performance boosting, and an inverter-based in-phase/quadrature (IQ) down-conversion mixer. The wideband LNA provides input matching of better than -10 dB from dc to beyond 10 GHz. The conversion gain (CG) of the RX front-end has a peak value of 31 dB with a 3-dB bandwidth up to 9 GHz. The minimal noise figure is 6 dB and kept below 9 dB within the entire operational bandwidth. The RX has a linearity in terms of intermodulation distortion of better than -12 dBm. The direct conversion TX involving inverter-based IQ modulator and Darlington-type pre-power amplifier features operation up to 9 GHz with 10-dB mean CG and an average output power of 4 dBm at 1-dB compression level. Excluding buffers and local oscillator generation, the RX and TX dissipate 54 and 84 mW, respectively, from a 1.2-V voltage supply. The circuit prototypes have been fabricated in a standard 65-nm CMOS low-power process without any additional RF options and occupy an area of only 0.77 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.53 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.

A CMOS adaptive RF front-end receiver for wireless applications

Design and implementation of an image-rejection double-quadrature radio frequency front-end receiver based on tunable polyphase filters (PPF) are presented in this article. The front-end consists of two sets of PPFs and a double-quadrature down-converter. The design contains devices that allow process spread and frequency drift control, making it suitable for multi-standard applications. Formal analysis and statistical method leading to the polyphase filter optimal sizing have been dealt with in this article. The effects of parasitic capacitances and component mismatch are also considered and discussed. Steps within CMOS polyphase filter design flow are then provided to guarantee high image rejection ratio (IRR) performance. The front-end receiver exhibits more than 60 dB IRR and good linearity in high-frequency applications.

Analysis and design of a high-linearity receiver RF front-end with an improved 25%-duty-cycle LO generator for WCDMA/GSM applications

A fully integrated receiver RF front-end that meets WCDMA/GSM system requirements is presented. It supports SAW-less operation for WCDMA. To improve the linearity in terms of both IP3 and IP2, the RF front-end is comprised of multiple-gated LNAs with capacitive desensitization, current-mode passive mixers with the proposed IP2 calibration circuit and reconfigurable Tow-Thomas-like biquad TIAs. A new power-saving multi-mode divider with low phase noise is proposed to provide the 4-phase 25%-duty-cycle LO. In addition, a constant-gm biasing with a non-chip resistor is adopted to make the conversion gain invulnerable to the process and temperature variations of the transimpedance. This RF front-end is integrated in a receiver with an on-chip frequency synthesizer in 0.13 μm CMOS. The measurement results show that owing to this high-linearity RF front-end, the receiver achieves −6 dBm IIP3 and better than +60 dBm IIP2 for all modes and bands.

0.6–3-GHz Wideband Receiver RF Front-End With a Feedforward Noise and Distortion Cancellation Resistive-Feedback LNA

A novel wideband receiver RF front-end, including a resistive negative feedback wideband low-noise amplifier (LNA) with feedforward noise and distortion cancellation and a current commutating down conversion passive mixer with biquad trans-impedance amplifier, is presented in this paper. In comparison to conventional resistive negative feedback LNAs, theory analysis and experimental results for the proposed LNA circuit shows improved performance parameters, including voltage gain, noise figure (NF), and input-referred third-order intercept point (IIP3), especially helpful for wideband LNA design in modern deep-submicrometer CMOS. A wideband receiver RF front-end fabricated in 0.13-μm CMOS, based on the proposed feedforward noise and distortion-cancellation resistive-feedback LNA, has 42-48-dB conversion gain with 0.8-12-MHz tunable IF -3-dB bandwidth and 12-dB adjacent channel selectivity at 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> , -14-dBm IIP3, and 3-dB NF double-sideband with 10-kHz flicker-noise corner frequency.

Wideband VHF and UHF RF Front-End Receiver for DVB-H Application

This paper presents a wideband and low-noise direct conversion front-end receiver supporting VHF and UHFbands simultaneously. The receiver iscomposed of a low-noise amplifier (LNA), a down conversion quadrature mixer, and a frequency divider by 2. The cascode configuration with the resistor feedback is exploited in the LNA to achieve a wide operating bandwidth. Four gainstep modesare employed using a switched resistor bank and a capacitor bank in the signal path to cope with wide dynamic input power range. The verticalbipolar junction transistors are used as the switching elements in the mixer to reduce 1/f noise corner frequency. The proposed front-end receiver fabricated in 0.18 <TEX>${\mu}m$</TEX> CMOS technology shows very low minimum noise figureof 1.8 dB and third order input intercept pointof -12dBm inthe high-gain mode of 26.5 dBmeasured at 500 MHz.The proposed receiverconsumeslow current of 20 mA from a 1.8 V power supply.

A CMOS MedRadio Receiver RF Front-End With a Complementary Current-Reuse LNA

An ultra-low-power 401-406-MHz Medical Device Radiocommunications Service receiver RF front-end for biomedical telemetry applications is implemented using 0.18-μm CMOS technology. A single-ended complementary current-reuse low-noise amplifier (CCRLNA) is proposed that achieves a power gain of 20 dB, noise figure (NF) of 2.8 dB, IIP3 of -8.1 dBm, and second-order intercept point of +34 dBm while consuming only 150 μW at 1-V supply voltage. The total receiver RF front-end, including the proposed CCRLNA, in-phase/quadrature folded mixers, and local oscillator buffers, achieves a conversion gain of 28.7 dB, NF of 5.5 dB, and third-order intercept point of -25 dBm while consuming less than 500 μW from a 1-V supply voltage and occupying 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of core die area.

A 250 mV, 352 $\mu$W GPS Receiver RF Front-End in 130 nm CMOS

A fully integrated CMOS GPS receiver RF front-end is presented. Systematic circuit optimizations for ultra-low voltage operation including subthreshold biasing, a novel mixer-VCO interface, and charge neutralization enable the supply voltage to be dramatically reduced as a means to save power. The 250 mV supply is the lowest ever reported for any integrated receiver RF front-end to date. Its 352 μW power consumption represents a three times power savings compared to the prior lowest GPS receiver RF front-ends reported in the literature. The prototype was fabricated in a 1P8M 130 nm CMOS process and includes a variable gain LNA, a quadrature VCO, quadrature mixers, and all required bias circuitry. The system has a measured gain of 42 dB, a noise figure of 7.2 dB, and an oscillator phase noise of - 112.4 dBc/Hz at a 1 MHz offset, resulting in a VCO FoM of 187.4 dBc/Hz.

Design of a 0.18 μm CMOS multi-band compatible low power GNSS receiver RF frontend

This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band. A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section, which mainly consists of a low noise amplifier (LNA), a down-converter, polyphase filters and summing circuits. An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage. Also, a re-designed wideband double balance mixer is implemented in the down conversion stage, which provides better gain, noise figure and linearity performances. Using a TSMC 0.18 μm 1P4M RF CMOS process, a compact 1.27 GHz/1.575 GHz dual-band GNSS frontend is realized in the proposed low-IF topology. The measurements exhibit the gains of 45 dB and 43 dB, and noise figures are controlled at 3.35 dB and 3.9 dB of the two frequency bands, respectively. The frontend model consumes about 11.8–13.5 mA current on a 1.8 V power supply. The core occupies 1.91 × 0.53 mm2 while the total die area with ESD is 2.45 × 2.36 mm2.

A differential low-voltage high gain current-mode integrated RF receiver front-end

A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (Gm-LNA) and a differential current-mode down converted mixer. The single terminal of the Gm-LNA contains just one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors, Cx1 and Cx2, can not only reduce the effects of gate-source Cgs on resonance frequency and input-matching impedance, but they also enable the gate inductance Lg1,2 to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 μm CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of −7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations.

A low-power multi-band CMOS RF receiver front-end for ubiquitous sensor network applications

This paper presents the design and experimental results of a low-power multi-band RF receiver including a multi-band low-noise amplifier (LNA) and a down-conversion mixer based on the IEEE 802.15.4 standard for sensor node applications. A multi-band LNA with two inputs is tuned to two resonant frequencies by controlling the voltage on a switched MOS. The implemented RF receiver front-end achieves a maximum voltage conversion gain of 38 and 30 dB, NF of 6.2 and 9.2 dB at the 868/915 MHz and the 2.45 GHz bands, respectively. The RF receiver front-end dissipates total 3.0 mA (including I/Q mixers) under supply voltage of 1.8 V at both operation bands.

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 µm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and ?2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.

An Active Feedback Interference Cancellation Technique for Blocker Filtering in RF Receiver Front-Ends

A feedback interference cancellation circuit is presented that uses a control loop to reject blockers in wireless receivers. The concept is based on a feedback translational loop which subtracts a blocker replica from the original blocker signal. In contrast to feedforward methods loop selectivity does not depend on exact gain matching of two paths but on the open loop gain which is easier to adjust. The concept is described including the theoretical derivations of the transfer function and stability. Nonidealities like I/Q mismatch and noise mechanisms are discussed. Finally, measurements from a prototype chip in 65-nm CMOS are presented showing the feasibility of active feedback cancellation. In a desensitization scenario, gain drops by more than 12 dB for a -15 dBm blocker at 20 MHz offset without feedback interference cancellation while a gain degradation of merely 3 dB is measured with feedback interference cancellation enabled.

RF receiver front end for 28.5 GHz applications on a 70 GHz FT SiGe BiCMOS process

AbstractThis article presents the design and test of a receiver front end aimed at LMDS applications at 28.5 GHz. It presents a system‐level design after which the receiver was designed. The receiver comprises an LNA, quadrature mixer and quadrature local oscillator. Experimental results at 24 GHz center frequency show a conversion voltage gain of 15 dB and conversion noise figure of 14.5 dB. The receiver operates from a 2.5 V power supply with a total current consumption of 31 mA. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 736–740, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25010

The blocker challenge when implementing software defined radio receiver RF frontends

Key blocker requirements of software defined radio receivers are identified from first principles. Three challenges are derived from these requirements, the need for passive filter banks or tunable passive filters, a very highly linear RF front-end and a high performance analog-to-digital converter. Each of these challenges is analyzed regarding possible solutions in the context of state-of-the art technology.

A 60-GHz Phased Array Receiver Front-End in 0.13-$\mu {\hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.

A dual-band reconfigurable direct-conversion receiver RF front-end

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the direct-conversion principle and consists of a low noise amplifier (LNA) and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm2.

A fully integrated 2.4‐GHz CMOS RF transceiver for low‐rate wireless sensor networks

AbstractThis article describes a low‐power and low‐cost fully integrated 2.4 GHz IEEE 802.15.4 RF transceiver for low‐rate wireless sensor networks. The RF transceiver adopts the single‐IF direct‐conversion architecture. For the high linearity, the RF receiver front end utilizes the current mirror amplifier as well as the transconductance linearization technique. The single‐IF I/Q modulation transmitter is integrated with the current‐mode analog baseband circuit and up‐mixer using the current mirror amplifier. The frequency synthesizer based on an integer‐N PLL topology offering 1.92 GHz differential and 0.48 GHz quadrature LO signals is also integrated on the RF transceiver. The fully integrated transceiver is fabricated in a 0.18‐μm CMOS technology and its die size is 3.7 mm × 3.6 mm including ESD I/O pads. It achieves the −94 dBm receiver sensitivity, 8 dB receiver chain noise figure, and maximum transmitter output power of 1 dBm while drawing power consumption of 31 mW in the receive mode and 42 mW in the transmit mode with the 1.8 V supply. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1481–1487, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24349

A low power 3–5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3–5 GHz UWB is presented. Designed in the 0.13 μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below −8.5 dB across the 3.1–4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of −11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.

Smart Antenna UKM Testbed for Digital Beamforming System

A new design of smart antenna testbed developed at UKM for digital beamforming purpose is proposed. The smart antenna UKM testbed developed based on modular design employing two novel designs of L-probe fed inverted hybrid E-H (LIEH) array antenna and software reconfigurable digital beamforming system (DBS). The antenna is developed based on using the novel LIEH microstrip patch element design arranged into uniform linear array antenna. An interface board is designed to interface to the ADC board with the RF front-end receiver. The modular concept of the system provides the capability to test the antenna hardware, beamforming unit, and beamforming algorithm in an independent manner, thus allowing the smart antenna system to be developed and tested in parallel, hence reduces the design time. The DBS was developed using a high-performance floating-point DSP board and a 4-channel RF front-end receiver developed in-house. An interface board is designed to interface to the ADC board with the RF front-end receiver. A four-element receiving array testbed at 1.88–2.22 GHz frequency is constructed, and digital beamforming on this testbed is successfully demonstrated.

A Linearization Technique for RF Receiver Front-End Using Second-Order-Intermodulation Injection

A linearization technique is proposed in which low-frequency second-order-intermodulation (IM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) is generated and injected to suppress the third-order intermodulation (IM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ). The proposed linearization technique is applied to both a low-noise amplifier (LNA) and a down-conversion mixer in an RF receiver front-end (RFE) working at 900 MHz. Fabricated in a 0.18 mum CMOS process and operated at 1.5 V supply with a total current of 13.1 mA, the RFE delivers 22 dB gain with 5.3 dB noise figure (NF). The linearization technique achieves around 20 dB IM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> suppression and improves the RFE's IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> from -10.4 dBm to 0.2 dBm without gain reduction and noise penalty while requiring only an extra current of 0.1 mA.