Reverse Gate Bias Research Articles

Evaluation of p-GaN HEMTs degradation under high temperatures forward and reverse gate bias stress

In this study, the degradation behavior and physical mechanism of the p-GaN HEMT devices under high-temperature gate bias (HTGB) with +5 V and −5 V were investigated. The DC characteristics show that the device after forward HTGB stress exhibits an obvious negative threshold voltage (Vth ) shift, while the device after reverse HTGB exhibits a negligible shift. The following explanations could be given for the deterioration mechanism: a portion of the two-dimensional hole gas (2DHG) accumulated in the p-GaN layer at the p-GaN/AlGaN interface under long-term forward bias may fill the trap in the AlGaN layer through the tunneling effect. In addition, the drain-source on-resistance of the device had increased after +5 V HTGB stress, and a distinct decrease of accumulated capacitance was observed in the Cg -Vg curve. It indicates a degradation of the gate quality of the device after applying a forward-biased HTGB stress.

Persistent charge storage and memory operation of top-gate transistors solely based on two-dimensional molybdenum disulfide

We fabricate top-gate transistors on the three-layer molybdenum disulfide (MoS2) with three, two, and one layers in the source and drain regions using atomic layer etching (ALE). In the presence of ALE, the device at zero gate voltage can exhibit high and low levels of drain current under the forward and reverse gate bias, respectively. The hysteresis loop on the transfer curve of transistor indicates that two distinct charge states exist in the device within a range of gate bias. A long retention time of the charge is observed. Unlike conventional semiconductor memories with transistors and capacitors, the two-dimensional (2D) material itself plays two parts in the current conduction and charge storage. The persistent charge storage and memory operation of the multilayer MoS2 transistors with thicknesses of a few atomic layer will further expand the device application of 2D materials with reduced linewidths.

Investigation of the Gate Degradation Induced by Forward Gate Voltage Stress in p-GaN Gate High Electron Mobility Transistors.

In this work, we investigated the degradation of the p-GaN gate stack induced by the forward gate voltage stress in normally off AlGaN/GaN high electron mobility transistors (HEMTs) with Schottky-type p-GaN gate. The gate stack degradations of p-GaN gate HEMTs were investigated by performing the gate step voltage stress and the gate constant voltage stress measurements. In the gate step voltage stress test, the positive and negative shifts of threshold voltage (VTH) depended on the range of the gate stress voltage (VG.stress) at room temperature. However, the positive shift of VTH in the small gate stress voltage was not observed at 75 and 100 °C and the negative shift of VTH was started from a lower gate voltage at a high temperature compared to room temperature. In the gate constant voltage stress test, the gate leakage current increased with three steps in the off-state current characteristics as the degradation progressed. To investigate the detailed breakdown mechanism, we measured the two terminal currents (IGD and IGS) before and after the stress test. The difference between the gate-source current and the gate-drain current in the reverse gate bias indicated that the increase of the leakage current was attributed to the degradation between the gate and the source while the drain side was not affected.

Remarkable Reduction in IG with an Explicit Investigation of the Leakage Conduction Mechanisms in a Dual Surface-Modified Al2O3/SiO2 Stack Layer AlGaN/GaN MOS-HEMT.

We demonstrated the performance of an Al2O3/SiO2 stack layer AlGaN/GaN metal-oxide semiconductor (MOS) high-electron-mobility transistor (HEMT) combined with a dual surface treatment that used tetramethylammonium hydroxide (TMAH) and hydrochloric acid (HCl) with post-gate annealing (PGA) modulation at 400 °C for 10 min. A remarkable reduction in the reverse gate leakage current (IG) up to 1.5×10-12 A/mm (@ VG = -12 V) was observed in the stack layer MOS-HEMT due to the combined treatment. The performance of the dual surface-treated MOS-HEMT was significantly improved, particularly in terms of hysteresis, gate leakage, and subthreshold characteristics, with optimized gate annealing treatment. In addition, an organized gate leakage conduction mechanism in the AlGaN/GaN MOS-HEMT with the Al2O3/SiO2 stack gate dielectric layer was investigated before and after gate annealing treatment and compared with the conventional Schottky gate. The conduction mechanism in the reverse gate bias was Poole-Frankel emission for the Schottky-gate HEMT and the MOS-HEMT before annealing. The dominant conduction mechanism was ohmic/Poole-Frankel at low/medium forward bias. Meanwhile, gate leakage was governed by the hopping conduction mechanism in the MOS-HEMT without gate annealing modulation at a higher forward bias. After post-gate annealing (PGA) treatment, however, the leakage conduction mechanism was dominated by trap-assisted tunneling at the low to medium forward bias region and by Fowler-Nordheim tunneling at the higher forward bias region. Moreover, a decent product of maximum oscillation frequency and gate length (fmax × LG) was found to reach 27.16 GHz∙µm for the stack layer MOS-HEMT with PGA modulation. The dual surface-treated Al2O3/SiO2 stack layer MOS-HEMT with PGA modulation exhibited decent performance with an IDMAX of 720 mA/mm, a peak extrinsic transconductance (GMMAX) of 120 mS/mm, a threshold voltage (VTH) of -4.8 V, a higher ION/IOFF ratio of approximately 1.2×109, a subthreshold swing of 82 mV/dec, and a cutoff frequency(ft)/maximum frequency of (fmax) of 7.5/13.58 GHz.

Low-temperature characteristics and gate leakage mechanisms of LPCVD-SiNx/AlGaN/GaN MIS-HEMTs

In this paper, we systematically investigated the static properties and gate current mechanism of low-pressure chemical vapor deposition-SiNx/AlGaN/GaN metal–insulator–semiconductor-high-electronmobility-transistor (MIS-HEMTs) at cryogenic temperature range from 10 K to 300 K. It is found that the threshold voltage of the device shows a positive shift due to the decreased carrier concentration at low temperature, and both the maximum transconductance and ON-resistance are improved at the low temperatures because of the enhanced electron mobility. Under very low electric field, the gate leakage exhibits ohmic conduction. With increasing forward gate bias, the dominant gate leakage mechanism at temperature below150 K gradually transits into trap-assisted tunneling, participating with a deep trap energy level of 0.73 eV in the SiNx dielectric, to Fowler–Nordheim (FN) tunneling. In contrast, the dominant gate leakage mechanism at temperature above 150 K transits from Poole–Frenkel emission, showing a low trap barrier height of 56 meV in the SiNx dielectric, to Fowler–FN tunneling with increasing forward gate bias. Under high reverse gate bias, carrier-limited gate current becomes the dominated gate leakage mechanism.

Reverse gate leakage mechanism of AlGaN/GaN HEMTs with Au-free gate

The reverse gate leakage mechanism of W-gate and TiN-gate AlGaN/GaN high-electron-mobility transistors (HEMTs) with N2 plasma surface treatment is investigated using current–voltage (I–V) and capacitance–voltage (C–V) characteristics and theoretical calculation analysis. It is found that the main reverse gate leakage mechanism of both devices is the trap-assisted tunneling (TAT) mechanism in the entire reverse bias region (–30 V to 0 V). It is also found that the reverse gate leakage current of the W-gate AlGaN/GaN HEMTs is smaller than that of the TiN gate at high reverse gate bias voltage. Moreover, the activation energies of the extracted W-gate and TiN-gate AlGaN/GaN HEMTs are 0.0551 eV–0.127 eV and 0.112 eV–0.201 eV, respectively.

Comparison of Hydrogen-Induced Oxide Charges Among GaN Metal-Oxide-Semiconductor Capacitors with Al2O3, HfO2, or Hf0.57Si0.43Ox Gate Dielectrics

The effect of hydrogen on GaN metal-oxide-semiconductor (MOS) capacitors with Al2O3, HfO2, or Hf0.57Si0.43O x gate dielectrics was studied using capacitance–voltage (C–V) measurements. Hydrogen exposure shifted all the C–V curves toward the negative bias direction, and the hydrogen response of the devices was reversible. When the hydrogen-containing ambient atmosphere was changed to N2, the C–V characteristics were found to gradually revert to the initial values in N2. Application of a reverse gate bias accelerated the reversion compared with that in the absence of a bias, indicating that hydrogen was absorbed into the dielectric (Hf0.57Si0.43O x ) as positive mobile charges. This result is consistent with the direction of the shift of the C–V curves; positively charged hydrogen absorbed into a dielectric can cause a flatband voltage shift. The hydrogen-induced shift of the C–V curves varied depending on the dielectric. MOS devices with HfO2-based high-k dielectrics were found to have approximately two to four times more incorporated charges than devices with Al2O3. Under the hypothesis that oxygen vacancies (VOs) trap hydrogen, the obtained results imply that the number of VOs in HfO2-based high-k dielectrics is much larger than that in Al2O3-based dielectrics.

Time-Resolved Threshold Voltage Instability of 650-V Schottky Type p-GaN Gate HEMT Under Temperature-Dependent Forward and Reverse Gate Bias Conditions

A research on time-resolved threshold voltage instability of 650-V Schottky type p-GaN gate Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.2</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.8</sub> N/GaN high electron mobility transistor (HEMT) under high-temperature gate bias (HTGB) conditions has been carried out. Both forward and reverse bias conditions are applied. We found that the threshold voltage of p-GaN AlGaN/GaN HEMT shifts negatively under high-temperature forward gate bias (HTFB), while shifts positively under high-temperature reverse gate bias (HTRB). Negative threshold voltage shifts under forward gate bias are largely due to the trapped positive charges (holes) caused by existing defects in the AlGaN layer. The holes are from the accumulated 2-D hole gas (2DHG) in the p-GaN layer near the p-GaN/AlGaN interface, which may be partially filled into the AlGaN layer by tunneling effect. Therefore, negative threshold voltage shifts under HTFB are temperature-independent. Positive threshold voltage shifts under reverse gate bias are from the hole emission in the p-GaN layer and the trapped negative charges (electrons) in the AlGaN layer. The electrons are trapped by defects resulted from the created hot holes in high temperature. The positive threshold voltage shift under HTRB is temperature-dependent, where higher temperature leads to a larger positive threshold voltage shift.

Neutron-Induced Failure Dependence on Reverse Gate Voltage for SiC Power MOSFETs in Atmospheric Environment

The mechanisms responsible for neutron-induced single-event burnout (SEB) in commercial silicon carbide power MOSFETs under atmospheric-like neutron spectrum were investigated and analyzed. The combined effect of applied reverse gate voltage and drain voltage was evaluated. First, local analysis of the packaged device at the wafer level is performed to reveal the failure mechanism inside the semiconductor lattice. Second, based on gate stress testing of surviving devices and looking at the influence of reverse gate bias during irradiation, an enhanced failure sensitivity especially for drain voltage values close to the safe operating area was demonstrated. In addition to support this assumption, TCAD simulations with damage sites were performed in order to address physical mechanisms related to gate leakage degradation and SEB.

High voltage carrier stored trench bipolar transistor with common anode polysilicon diodes gate structure for low Miller capacitance and low electromagnetic interference noise

A novel 3300 V high voltage carrier stored trench bipolar transistor (CSTBT) with common anode polysilicon diodes gate structure (CAPD-CSTBT) is proposed. The PN junctions and N+ emitter region in the polysilicon gate structure are beneficial for reducing the Miller capacitance by 88.1% and the input capacitance by 26.0%, while due to the polysilicon PN junction barrier, the forward and reverse gate bias voltage will not be affected. As a result, the transient energy loss could be decreased by 32.2% with the same range of R g. Since the displacement current is shielded by the embedded emitter on the bottom of the CAPD gate structure, the (dI CE /dt)max/I Load is lower than that of the Fin-P-CSTBT by 81.8% on average with the same range of turn-on energy loss. Furthermore, the proposed structure features a 58.7% lower (dV KA /dt)max/V cc value for the free-wheeling diode on average. By Fourier transformation, the proposed structure represents lower amplitudes for the I CE and V KA spectrums during the turn-on period, which is a drastic suppression of electromagnetic interference noise.

Analysis on degradation mechanisms of normally-off p-GaN gate AlGaN/GaN high-electron mobility transistor* *Project supported by the Equipment Developing Advanced Research Program of China (Grant No. 6140A24030107).

The degradation mechanisms of enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistor was analyzed extensively, by means of drain voltage stress and gate bias stress. The results indicate that: (i) High constant drain voltage stress has only a negligible impact on the device electrical parameters, with a slightly first increase and then decrease in output current; (ii) A negative shift of threshold voltage and increased output current were observed in the device subjected to forward gate bias stress, which is mainly ascribed to the hole-trapping induced by high electric field across the p-GaN/AlGaN interface; (iii) The analyzed device showed an excellent behavior at reverse gate bias stress, with almost unaltered threshold voltage, output current, and gate leakage current, exhibiting a large gate swing in the negative direction. The results are meaningful and valuable in directing the process optimization towards a high voltage and high reliable enhanced AlGaN/GaN high-electron mobility transistor.

Mechanisms of a Rectifying TiN Gate Contact for AlGaN$/$GaN HEMTs on Silicon Substrate

Rectifying Titanium Nitride (TiN) gate contact technology is developed for AlGaN $/$ GaN based micro and nanometer HEMTs. A high compressive strain occurring in thinner TiN films (ranging from 5 nm to 60 nm), deposited by sputtering, leads to a reduction in tensile strain at the surface of AlGaN barrier. The diminution in tensile strain forms a pseudo- $p$ -type layer (diode-like). This strain reduction has no effect on the bandgap of the AlGaN barrier layer, allowing the gate to withstand a reverse gate bias larger than 100 V. Characterization using the high-resolution transmission electron microscopy combined with the X-ray photoelectron spectroscopy reveals a good TiN $/$ AlGaN interface quality and no diffusion of TiN into AlGaN. The effective energy barrier of the rectifying nanoscale TiN gate contact has a relatively large height of 1.1 eV associated with an ideality factor of 1.4. A dramatic drop of the reverse-bias leakage current down to 11 pA $/$ mm is measured at −30 V. In addition, electrical measurements show very low gate and drain lag effects of 4.2 ${\%}$ and 6.7 ${\%}$ , respectively.

Threshold Voltage Instability of Diamond Metal–Oxide–Semiconductor Field‐Effect Transistors Based on 2D Hole Gas

Recent marked advances in diamond metal–oxide–semiconductor field‐effect transistors (MOSFETs) have raised the issue of gate reliability. Herein, the threshold voltage stability of MOSFETs based on hydrogen‐terminated diamond surface conductivity is examined. The electrical output characteristic curves are characterized by cyclic gate sweeping from reverse to forward gate bias (RF) and from forward to reverse gate bias (FR), respectively. The characteristics of drain current versus drain voltage are affected by the gate bias sweeping direction. Marked hysteresis is also observed in the transfer curves for the RF and FR gate sweeping. The different gate sweeping directions induce threshold voltage variation and hole mobility change. The facts that 1) no extra interface states are generated due to gate sweeping and 2) the trapped charge density depends on the gate oxide thickness, reveal that charge trapping occurs at the border of the gate oxide.

Short Circuit Capability and Short Circuit Induced $V_{\mathrm{TH}}$ Instability of a 1.2-kV SiC Power MOSFET

The withstand capability and threshold voltage ( $V_{\mathrm {TH}}$ ) instability of 1.2-kV silicon carbide (SiC) MOSFETs under repetitive short circuit (SC) tests are investigated. An SC test system is constructed to apply repetitive SC stress to SiC MOSFETs and measure the transfer $I$ – $V$ characteristics and gate-to-source leakage current ( $I_{\mathrm {GSS}}$ ) after each set of SC tests. To evaluate the SC capability, repetitive SC tests with different SC durations ( $t_{p}$ ) are conducted until device failure. The SC withstand time (SCWT) at 1000 SC cycles is found to be $\sim 3.3~\mu \text{s}$ . $V_{\mathrm {TH}}$ instability under repetitive SC tests prior to the device failure is characterized. A bidirectional $V_{\mathrm {TH}}$ shift behavior, i.e., negative shift at shorter $t_{p}$ and positive shift at longer $t_{p}$ , was revealed. The $V_{\mathrm {TH}}$ shifts under repetitive SC tests are attributed to the SC pulse process according to the results of high-temperature reverse bias (HTRB) and dynamic high-temperature gate bias (HTGB) tests. The underlying mechanisms of the complex $V_{\mathrm {TH}}$ shift behavior are explained in a unified framework by taking into account the junction temperature ( $T_{j}$ ) increase with longer $t_{p}$ . TCAD device simulation is used to help analyze the mechanisms.

Spin Filtering and Rectification in Lateral Heterostructures of Zigzag-Edge BC3 and Graphene Nanoribbons: Implications for Switching and Memory Devices

Heterostructures of different atomically thin nanomaterials provide an ideal platform of admixing their unique properties to achieve new functionalities. Here, we study the lateral heterostructures of graphene and BC3 nanoribbons with zigzag edge terminations within first-principles calculations. These heterostructures show localization of one kind of spin along the open graphene zigzag edge, whereas the other edge does not show any spin polarization. Therefore, the systems stabilize in the ferromagnetic ground state, inducing net magnetization and broken time reversal symmetry in each valley. Owing to this asymmetric spin distribution, the system shows spin-polarized current that is confirmed by further first-principles-based quantum transport calculations. The conduction behavior can be tuned further by changing the polarity of the side-gates in either sides of the ribbon edges. We observe higher spin polarization of current under forward gate bias but lower spin polarization of current under reverse gate bias. This functionality provides a unique way of spin filtering and rectification by changing the electrode polarity, which can find major applications in switching and memory storage devices.

Impact of carrier injections on the threshold voltage in p-GaN gate AlGaN/GaN power HEMTs

We investigated the threshold voltage (VTH) shift in p-GaN gate AlGaN/GaN power HEMTs under both forward and reverse gate bias conditions at different temperatures. With increasing forward gate bias, the VTH first positively shifted and then decreased. While at the reverse gate bias, VTH shifts monotonically increased towards the positive direction. Positive VTH shifts were due to electron trapping while its decrease was attributed to the optical pumping by the internal electroluminescence (EL). The EL emission from the p-GaN gate region was captured. A light illumination test was performed to verify the effectiveness of optical pumping.

Gate leakage mechanisms in normally off p-GaN/AlGaN/GaN high electron mobility transistors

In this letter, gate leakage mechanisms in different gate contact normally off p-GaN/AlGaN/GaN high electron mobility transistors (HEMTs) have been studied by the temperature-dependent current-voltage (IG-VG) measurement. It is found that two-dimensional variable range hopping is responsible for gate leakage current at the reverse gate bias and low forward gate bias in both high-leakage and low-leakage Schottky gate contact devices. At high forward gate bias, in the case of high-leakage Schottky contact, the dominant current conduction mechanism is found to be thermionic field emission while it is Poole–Frenkle emission (PFE) for the case of low-leakage Schottky contact and the activation energy of trap states for PFE current is derived as 0.6 eV. Besides, related models are also proposed to describe the gate leakage current in p-GaN gate HEMTs and they match well with the experimental gate leakage current within a wide range of temperatures and gate biases.

Role of AlGaN/GaN interface traps on negative threshold voltage shift in AlGaN/GaN HEMT

This article reports negative shift in the threshold-voltage in AlGaN/GaN high electron mobility transistor (HEMT) with application of reverse gate bias stress. The device is biased in strong pinch-off and low drain to source voltage condition for a fixed time duration (reverse gate bias stress), followed by measurement of transfer characteristics. Negative threshold voltage shift after application of reverse gate bias stress indicates the presence of more carriers in channel as compared to the unstressed condition. We propose the presence of AlGaN/GaN interface states to be the reason of negative threshold voltage shift, and developed a process to electrically characterize AlGaN/GaN interface states. We verified the results with Technology Computer Aided Design (TCAD) ATLAS simulation and got a good match with experimental measurements.

Gate Leakage Mechanisms in AlInN/GaN and AlGaN/GaN MIS-HEMTs and Its Modeling

Gate leakage mechanisms in AlInN/GaN and AlGaN/GaN metal insulator semiconductor high-electron-mobility transistors (MIS-HEMTs) with SiNx as gate dielectric have been investigated. It is found that the conduction in the reverse gate bias is due to Poole-Frenkel emission for both MIS-HEMTs. The dominant conduction mechanism in low to medium forward bias is trap-assisted tunneling while it is Fowler–Nordheim tunneling at high forward bias. However, conduction near zero gate bias is dominated by defect-assisted tunneling for both sets of MIS-HEMTs. The gate leakage current is primarily dependent on the properties of the gate dielectric material and dielectric/ semiconductor interface rather than the barrier layer. A model is proposed for the gate leakage current in GaN-based MIS-HEMTs, and the method to extract the related model parameters is also presented in this paper. The proposed gate current model matches well with the experimental results for both AlInN/GaN and AlGaN/GaN MIS-HEMTs over a wide range of gate bias and measurement temperature.

ALD TiN Schottky Gates for Improved Electrical and Thermal Stability in III-N Devices

AlGaN/GaN high electron mobility transistors (HEMTs) are useful devices for next-generation RF and power electronics systems1,2. Traditional Ni-based Schottky gates in these devices have been shown to degrade when subjected to electrical stress, thermal stress, and radiation due to Ni migration into adjacent metal or semiconductor layers3,4. The instability of these Ni-based gates limits device reliability, rendering the search for replacement gate materials that are electrically- and thermally-stable a topic of tremendous importance. Of the transition metal nitrides, TiN is a particularly promising material, due to its near-metallic conductivity, suitable Schottky barrier heights and ideality factors on GaN and AlGaN, and high temperature stability. This work investigates the performance of atomic layer deposited (ALD) TiN gates and directly compares them to traditional Ni/Au gates. ALD TiN gates (15-75nm thick) were deposited on AlGaN/GaN HEMTs and diodes at 150-350°C using Tetrakis(dimethyamido)titanium (TDMA-Ti) and a 300W N2/H2 plasma as precursors with a growth rate of 0.6 Å/cy. Increasing the growth temperature, while remaining in a linear ALD regime, reduced the oxygen content by a factor of two and eliminated carbon impurities within the film resulting in 7x lower film resistivity. The plasma gas chemistry and pressure (8-80 mTorr) had an even greater impact on the electrical properties of these films. An exponential decrease in resistivity was achieved by increasing the N2/H2 ratio from 0.1-1.6 at a constant temperature. The lowest resistivity (120 µΩ-cm) was attained using a N2-only plasma at 7 mTorr at 350°C. While this resistivity is higher than typical bulk values (10-30 µΩ-cm), it is similar to PVD (30-100 µΩ-cm) and lower than many CVD films, which can vary widely (200-10,000 µΩ-cm). Using this growth parameter knowledge, a series of TiN gates were deposited on GaN diodes with varying oxygen content from 3-12 at%. TiN films with lower oxygen content also exhibited lower barrier heights in Schottky barrier diodes, suggesting a way to tailor the properties for different applications. ALD TiN gates (75nm) also exhibited improved static and dynamic on-state characteristics when directly compared to identical Ni/Au-gated AlGaN/GaN HEMTs. Reverse bias gate stressing indicated a higher critical voltage (VgsTiN = -210V, VgsNi/Au = -120V) and a higher breakdown voltage (VgsTiN = -270 ± 10 V, VgsNi/Au = -240 ± 30V) for the TiN gates. Furthermore, the TiN gates exhibited a decrease in reverse leakage current after stressing suggesting enhanced stability. Gate thermal stability was assessed through sequential device annealing from 400-800°C in 100°C increments. The TiN gated devices exhibited stable DC operation up to 800°C, while the Ni/Au gates showed significant degradation after annealing above 500°C and failed above 700°C. This suggests that ALD TiN gates are a strong candidate for reliable HEMT gate metallization and other applications where increased stability is required at higher temperatures. 1 R.S. Pengelly, et al., IEEE Trans. Microwave Theory Tech. 60 [6], 1764 (2012). 2 S.J. Pearton, et al., J. Vac. Sci. Technol. A 31 [5], 050801 (2013). 3 Y.H. Choi, et al., Materi. Res. Soc. Symp. Proc. 1167, 1167-O05-06 (2009). 4 A.D. Koehler, et al., IEEE Elect. Dev. Lett. 35 [12], 1194 (2014).