Reverse Bias Stress Research Articles

Design Optimization and Reliability Evaluation in 1.2 kV SiC Trench MOSFET with Deep P Structure

In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), charge to breakdown (QBD), and time dependent dielectric breakdown (TDDB) tests were conducted. Also, high temperature gate bias (HTGB) and high temperature reverse bias (HTRB) stress tests were carried out for assembled samples to compare device reliability depending on different designs. For the target design, the promising reliability results were confirmed in both wafer level and assembled samples.

4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses.

This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO2 interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler-Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔVth and ΔVFN variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔVth and ΔVFN, while HTRB showed only a 4% variation in both ΔVth and ΔVFN. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration.

Synergistic effect of electrical bias and proton irradiation on the electrical performance of β-Ga2O3 p–n diode

The synergistic impact of reverse bias stress and 3 MeV proton irradiation on the β-Ga2O3 p–n diode has been studied from the perspective of the defect in this work. The forward current density (JF) is significantly decreased with the increase in proton irradiation fluence. According to the deep-level transient spectroscopy results, the increase in the acceptor-like trap with an energy level of EC-0.75 eV within the β-Ga2O3 drift layer, which is most likely to be Ga vacancy-related defects, can be the key origin of the device degradation. The increase in these acceptor-like traps results in the carrier concentration reduction, which in turn leads to a decrease in JF. Furthermore, compared with the case of proton irradiation with no bias, the introduction of −100 V electrical stress induced a nearly double decrease in JF. Based on the capacitance–voltage (C–V) measurement, with the support of the electric field, the carrier removal rate increased from 335 to 600 cm−1. Similar to the above-mentioned phenomenon, the trap concentration also increased significantly. We propose a hypothesis elucidating the synergistic effect of electrical stress and proton irradiation through the behavior of recoil nuclei under the electric field.

On the insignificance of dislocations in reverse bias degradation of lateral GaN-on-Si devices

The role of threading dislocations in the intrinsic degradation of lateral GaN devices during high reverse bias stress tests (RBSTs) is largely unknown. We now present the results on lateral p-GaN/AlGaN/2DEG heterojunctions with a width of 200 μm in GaN-on-Si. A time-dependent permanent degradation of the heterojunction under high reverse bias and elevated temperatures can be observed, ultimately leading to a hard breakdown and device destruction. By using an integrated series p-GaN resistor, the device is protected from destruction and, consequently, the influence of dislocations on the degradation mechanism could be studied. Localization by emission microscopy could show that the transient current increase during a RBST is the result of the creation of a limited amount of highly localized leakage paths along the whole device width. We could establish a 1:1 correlation of leakage sites with a structural material degradation within the AlGaN barrier for nine individual positions on two different devices by planar transmission electron microscopy analysis. To unambiguously show whether dislocations in GaN-on-Si even should be considered a potential trigger for the RBST degradation in lateral heterojunctions, a combined planar and cross-sectional lamella approach was used for the first time for larger devices. This enabled the visualization of the three-dimensional propagation path of the dislocations close to the degradation sites. It was found that there is no statistically significant link between the material degradation and pre-existing dislocations. Our findings offer new insights into the GaN-on-Si material system, upon which upcoming power technologies are built upon.

Evaluation of p-GaN HEMTs degradation under high temperatures forward and reverse gate bias stress

In this study, the degradation behavior and physical mechanism of the p-GaN HEMT devices under high-temperature gate bias (HTGB) with +5 V and −5 V were investigated. The DC characteristics show that the device after forward HTGB stress exhibits an obvious negative threshold voltage (Vth ) shift, while the device after reverse HTGB exhibits a negligible shift. The following explanations could be given for the deterioration mechanism: a portion of the two-dimensional hole gas (2DHG) accumulated in the p-GaN layer at the p-GaN/AlGaN interface under long-term forward bias may fill the trap in the AlGaN layer through the tunneling effect. In addition, the drain-source on-resistance of the device had increased after +5 V HTGB stress, and a distinct decrease of accumulated capacitance was observed in the Cg -Vg curve. It indicates a degradation of the gate quality of the device after applying a forward-biased HTGB stress.

Test concept for a direct correlation between dislocations and the intrinsic degradation of lateral PIN diodes in GaN-on-Si under reverse bias

Although often discussed, the role of threading dislocations (TDs) in the degradation of lateral GaN-on-Si p-GaN HEMTs under reverse bias stress test (RBST) has never been clearly shown in experiment until today. Here we present a novel test concept to establish a direct correlation between dislocations and degradation sites in RBST and demonstrate it on lateral p-GaN/AlGaN/GaN PIN diodes. By scaling down structures down to ~500 nm width, the point of degradation is always forced to be located at a defined position, independent of the local position of TDs. Furthermore, an integrated serial p-GaN resistor has been implemented with the PIN diode, which effectively limits the current and protects the device from a large meltdown due to parasitic capacitances and enables TEM analysis of structural degradation. A large quantity of lateral PIN devices exhibit a similar time-to-breakdown under RBST, indicating the intrinsic nature of this failure mode. Planar TEM analysis of a degraded and failed device clearly reveals structural damages and a breakdown of the AlGaN barrier as the failure signature. A combined planar and cross-sectional TEM lamella analysis approach of the expected failure site was introduced and applied. The results unambiguously show, that the observed degradation in the AlGaN barrier, which is attributed to the intrinsic failure mode, is not directly linked to the position of a dislocation.

Investigation of trap characteristics under the inverse piezoelectric effect in AlGaN/GaN HEMT devices at room temperature and low temperature

Changes in the electrical properties and the trap characteristics of AlGaN/GaN high electron mobility transistors under the application of reverse bias stress at both room temperature and low temperature were investigated. When the critical stress voltage was reached, the gate current, which complied with the Poole–Frenkel conduction conditions, showed an abrupt increase. Furthermore, the magnitude of the critical stress voltage for occurrence of the inverse piezoelectric effect can be increased at 83 K. The transient current method was used to establish that the detrapping peak amplitudes of the traps increased, but the trap activation energy remained unchanged. The changes observed in both the time constant spectra and the pulsed current–voltage curves confirmed that the trap densities in the AlGaN barrier layer increased as a result of the inverse piezoelectric effect. However, the different degrees to which the numbers of traps increased at room temperature and at 83 K contributed to the occurrence of different degradations in the device.

Investigation on the threshold voltage instability mechanism of p-GaN gate AlGaN/GaN HEMTs under high-temperature reverse bias stress

In this Letter, threshold voltage instability of p-GaN gate AlGaN/GaN HEMTs under high-temperature reverse bias (HTRB) stress has been investigated in detail. The experimental results show that the threshold voltage increases by 0.62 V after 100 ks stress at 200 °C. Especially, the degradation phenomenon is unrecoverable. A deep-level transient spectroscopy (DLTS) technique is used to characterize the defect evolution process during the stress. Two kinds of electron traps within the p-GaN layer were proposed to explain the degradation, which were generated by the injected high-energy electrons from the gate electrode. One is referred to as fixed charge trap, and another is trap E3 (EC-0.7 eV). With the aid of high temperature, more electrons are injected and trapped in the fixed charge trap, which causes the permanent threshold voltage increase. In addition, the concentration and capture cross section of trap E3 were extracted as well, which are considered to dominate the recoverable degradation of the device due to the relatively shallower energy level.

Study of the influence of gate etching and passivation on current dispersion, trapping and reliability in RF 0.15 μm AlGaN/GaN HEMTs

In this paper we examine the effect of passivation and gate etching processes on the current dispersion and reliability of AlGaN/GaN HEMTs for RF applications. We compared the performance of HEMTs with a standard gate etching and passivation processes (reference wafer) with the performances of HEMTs with improved etching process (etching variant wafer) and improved passivation process (passivation variant wafer). In order to study the trapping behavior, we performed dispersion measurements in off-state conditions and drain current transients (DCT) and we found that:1)The use of improved passivation process determines a decrease of current dispersion, in particular at the knee voltage, where current collapse depends on both threshold voltage and on-resistance variation,2)The trapping process linked to surface states is influenced by the gate etching and passivation processes; the use of improved passivation slows down the trapping/de-trapping kinetics, resulting in a lower impact on dynamic performance.The study of reliability is based on high-temperature reverse bias (HTRB) stresses. The gate-drain diodes are biased in the same voltage stress conditions (VGS,Stress = -7 V, VDS,Stress = 50 V) at high temperatures (175 °C) for 24 h. We demonstrated that the improved passivation limits the increase of gate leakage current during HTRB stress and prevents the belly shape effect linked to the presence of donor traps in the surface between SiN and GaN cap.We performed gate step stress increasing the negative voltage applied to the Schottky contact. The electroluminescence images performed during the stress show spots along the gate finger that are the responsible of the failure of the devices. The results presented in the paper provide information on the optimization of GaN HEMTs for RF applications.

Degradation mechanisms of Mg-doped GaN/AlN superlattices HEMTs under electrical stress

GaN-based high electron mobility transistors (HEMTs) have exhibited great application prospects in power and radio frequency devices, thanks to the superior properties of GaN. Despite the significant commercialization progress, the reliability of GaN-based HEMTs remains a challenge. This work experimentally investigates the time-dependent degradation of Mg-doped GaN/AlN superlattice HEMTs under both OFF-state and SEMI-ON-state bias conditions and proposes that GaN/AlN superlattices as a barrier can solve the Vth instability issues of GaN HEMTs under OFF-state and SEMI-ON-state bias conditions. On the one hand, in the SEMI-ON-state, the hot electron effect leads to the degradation of Ig, gm,max, and Id,sat to varying degrees. However, the as-prepared GaN-based HEMTs exhibit excellent Vth stability (almost no change) under hot electron injection, on the account of the excellent two-dimensional electron gas confinement in the GaN/AlN superlattice structure. On the other hand, in the OFF-state, positive Vth shift (about 0.12 V) is induced by the hole emission in the GaN/AlN superlattice structure under reverse bias stress. In addition, the stress-induced destruction of MgO gate dielectric gives rise to the gate leakage, which increases by 2 orders of magnitude and triggers an irreversible degradation (about 10%) of the gm,max. These results are expected to provide a solution to the Vth instability of GaN HEMTs.

Evaluation on Temperature-Dependent Transient VT Instability in p-GaN Gate HEMTs under Negative Gate Stress by Fast Sweeping Characterization.

In this work, temperature-dependent transient threshold voltage (VT) instability behaviors in p-GaN/AlGaN/GaN HEMTs, with both Schottky gate (SG) and Ohmic gate (OG), were investigated systematically, under negative gate bias stress, by a fast voltage sweeping method. For SG devices, a concave-shaped VT evolution gradually occurs with the increase in temperature, and the concave peak appears faster with increasing reverse bias stress, followed by a corresponding convex-shaped VT recovery process. In contrast, the concave-shaped VT evolution for OG devices that occurred at room temperature gradually disappears in the opposite shifting direction with the increasing temperature, but the corresponding convex-shaped VT recovery process is not observed, substituted, instead, with a quick and monotonic recovery process to the initial state. To explain these interesting and different phenomena, we proposed physical mechanisms of time and temperature-dependent hole trapping, releasing, and transport, in terms of the discrepancies in barrier height and space charge region, at the metal/p-GaN junction between SG and OG HEMTs.

Study of the reverse I–V in component subcells of III–V multijunction space solar cells

AbstractThe reverse bias operation of triple‐junction solar cells (GaInP/Ga(In)As/Ge), typically used for space photovoltaics, is poorly understood. In this work, we conduct reverse bias stress tests on both isotype subcells (GaInP, Ga(In)As and Ge) as well as in the complete triple‐junction solar cell. After each reverse bias step, forward dark and lighted I–Vs are measured and modelled using Shockley and Spirito and Albergamo models to fit the characteristic parameters of each individual subcell and quantify the variations evolution caused by the stress. The changes in these parameters are thoroughly analysed in order to comprehend the basic physical processes behind the degradation observed after the reverse bias is applied. Finally, we demonstrate that the individual parameters obtained from each subcell can be combined to simulate the final I–V curve of the complete triple junction and understand how it is affected when reverse bias is applied, linking the changes observed to a sudden degradation of the GaInP top subcell at low reverse voltages.

Increase of reverse leakage current at homoepitaxial GaN p-n junctions induced by continuous forward current stress

Reliability tests involving the application of high electrical stresses were employed to assess GaN-based vertical p-n junctions fabricated on freestanding GaN substrates with threading dislocation densities less than 104 cm−2. Electric field crowding at the device edges was eliminated by employing a shallow bevel mesa structure, thus allowing an evaluation of the reliability of the internal p-n junctions. The p-n diodes exhibited reproducible avalanche breakdown characteristics over the temperature range of 25–175 °C. No degradation was observed even during tests in which the devices were held under a reverse bias near the breakdown voltage. Despite this high degree of reliability in response to reverse bias stress, a small number of diodes were degraded during continuous forward current tests, although the majority of diodes remained unchanged. The reverse leakage current exhibited by degraded diodes was increased with an increase in the forward current density within the range of 50–500 A/cm2, while the breakdown voltages were unchanged in response to current stress. The leakage level increased exponentially with an increase in the total amount of injected carriers but eventually plateaued. In the degraded p-n diode, a luminous point in an emission microscope corresponded to one of the threading dislocations observed in the synchrotron x-ray topography, indicating that a specific dislocation played as a leakage path after injecting carriers.

Analysis of degradation mechanisms in GaN-based light-emitting diodes under reverse-bias stress: effects of defects and junction-temperature increase

Degradation phenomena of GaN-based blue LEDs are investigated from comprehensive electrical, optical, and thermal analyses. After constant reverse-bias stress, the LED sample under investigation shows permanent degradations indicated by increases both in the tunneling/sidewall leakage current in the low-current region and the nonradiative current in the high-current region. A subsequent decrease in series resistance and increase in junction temperature are also observed. The degradation at high currents is analyzed in terms of the radiative recombination current utilizing the information of the internal quantum efficiency (IQE), which has been rarely attempted. All of the observed degradations can be attributed to the increase in defect density in the active layer of the LED chip under reverse-bias stress. This work emphasizes that many important reliability-related features of LEDs are functions of defects and the junction temperature and that the IQE can provide crucial information in the analysis. The increased junction temperature would have further detrimental effects on the device performance and eventually lead to device failure. The analyses presented in this work shed more light on understanding the degradation phenomena in the GaN-based LEDs under reverse-bias stress.

Time-Dependent Threshold Voltage Instability Mechanisms of p-GaN Gate AlGaN/GaN HEMTs Under High Reverse Bias Conditions

In this article, we experimentally investigate the degradation mechanisms of GaN high-electron mobility transistors (HEMTs) with p-type gate during long-term hightemperature reverse bias (HTRB) stress and negative bias temperature instability (NBTI) stress. Based on a number of stress/recovery experiments, we demonstrate that HTRB stress could lead to hole emission in the p-GaN layer, making threshold voltage (Vth) positively shift, while NBTI stress could result in detrapping at the AlGaN/GaN interface or the AlGaN layer and make Vth negatively shift. It is also found that the temperature rise can suppress the positive Vth shift and accelerate its recovery process in HTRB experiments.

Analysis on degradation mechanisms of normally-off p-GaN gate AlGaN/GaN high-electron mobility transistor* *Project supported by the Equipment Developing Advanced Research Program of China (Grant No. 6140A24030107).

The degradation mechanisms of enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistor was analyzed extensively, by means of drain voltage stress and gate bias stress. The results indicate that: (i) High constant drain voltage stress has only a negligible impact on the device electrical parameters, with a slightly first increase and then decrease in output current; (ii) A negative shift of threshold voltage and increased output current were observed in the device subjected to forward gate bias stress, which is mainly ascribed to the hole-trapping induced by high electric field across the p-GaN/AlGaN interface; (iii) The analyzed device showed an excellent behavior at reverse gate bias stress, with almost unaltered threshold voltage, output current, and gate leakage current, exhibiting a large gate swing in the negative direction. The results are meaningful and valuable in directing the process optimization towards a high voltage and high reliable enhanced AlGaN/GaN high-electron mobility transistor.

Improved the C–V Curve Shift, Trap State Responsiveness, and Dynamic R ON of SBDs by the Composite 2-D–3-D Channel Heterostructure Under the OFF-State Stress

In this article, the C-V curve shift, trap densities responsiveness,and dynamic R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> of AlGaN/GaN/GaN:C (SH:C) and AlGaN/GaN/graded-AlGaN:Si/GaN:C (DH:Si/C) heterostructure Schottky barrier diodes (SBDs) have been systematically analyzed. Due to additional 3-D electrons in graded-AlGaN:Si layer, the composite 2-D-3-D channel of DH:Si/C has a higher carrier concentration. Reducing the OFF-state electric field strength through AlGaN:Si insert layer, a smaller positive shift of C-V curve is achieved under OFF-state stress. Due to the charge shielding effect of AlGaN:Si insert layer, trapping/detrapping effects in GaN:C buffer under the OFF-state stress are well suppressed. Compared with SH:C heterostructure, the trap density responsiveness of DH:Si/C heterostructure under OFF-state stress is significantly reduced. At the same time, trap density responsiveness of the upper channel is immune to OFF-state electric stress time. In addition, the proposed SBDs show lower ON-resistance with on reverse bias stress and better dynamic performance with on reverse stress time.

Impact of Residual Carbon on Avalanche Voltage and Stability of Polarization-Induced Vertical GaN p-n Junction

We demonstrate that the residual carbon concentration in the drift region can have a significant impact on the reverse leakage, breakdown voltage, and breakdown stability of GaN-on-GaN vertical diodes. Two generations (Gen1, Gen2) of polarization-doped p-n junctions with different C concentrations were compared, in terms of avalanche voltage, avalanche instability, and deep-level concentration. The original results collected within this paper show that: 1) both generations of devices can safely reach the avalanche regime; diodes with a lower residual CN have a higher reverse leakage and a lower avalanche voltage, due to an uneven distribution of the electric field; 2) the presence of residual carbon can lead to breakdown walkout, i.e. a recoverable increase in breakdown voltage under reverse-bias stress. Specifically, devices with higher C concentration show a fully-recoverable breakdown walkout, whereas the breakdown voltage is stable in devices with lower C concentration; and 3) steady-state photocapacitance measurements confirm the presence of CN in both generations, and are used to assess the relative difference in concentration between Gen1 and Gen2, even for levels below secondary ion mass spectroscopy (SIMS) sensitivity. The results described in this paper indicate the existence of a trade-off between breakdown voltage (increasing by improving compensation) and breakdown stability (improving by reducing CN concentration) and are of fundamental importance for the optimization of GaN power devices.

Commercialization of Highly Rugged 4H-SiC 3300 V Schottky Diodes and Power MOSFETs

In this paper, we present a new family of 3300 V silicon carbide (SiC) Schottky barrier diodes (SBDs) and power MOSFETs. The main design requirements are discussed with an emphasis on the design rules to improve the long-term reliability. Basic static and dynamic performance demonstrates low conduction and switching losses. Long-term tests such as high-temperature reverse bias (HTRB) and body diode forward bias stress were performed to evaluate the devices’ reliability. An emission microscopy (EMMI) study was conducted to assess the quality of the gate oxide. Outstanding surge and avalanche capabilities are reported with UIS ruggedness of 11.4 and 20.8 J.cm-2 for SBDs and MOSFETs, respectively.

Nanoscale Insights on the Origin of the Power MOSFETs Breakdown after Extremely Long High Temperature Reverse Bias Stress

In this work, the origin of the dielectric breakdown of 4H-SiC power MOSFETs was studied at the nanoscale, analyzing devices that failed after extremely long (three months) of high temperature reverse bias (HTRB) stress. A one-to-one correspondence between the location of the breakdown event and a threading dislocation propagating through the epitaxial layer was found. Scanning probe microscopy (SPM) revealed the conductive nature of the threading dislocation and a local modification of the minority carriers concentration. Basing on these results, the role of the threading dislocation on the failure of 4H-SiC MOSFETs could be clarified.