Reverse Bias Stress Research Articles

High-Temperature Reliability Analysis of 1200V/100A 4H-SiC Junction Barrier Schottky Diodes

The high-temperature (up to 200 °C) reliability analysis of 1200V/100A 4H-SiC JBS under 168 hours of high-temperature storage stress (HTSS), high-temperature reverse bias (HTRB) and high-humidity HTRB (H3TRB) stress test are reported. Results show that, all the statistical distribution of the data consistency is more dispersed after HTSS, HTRB and H3TRB test, which suggests that there are more degradation in the forward voltage and leakage current characteristics of JBS device under high temperature (up to 423K) stress. The increased reverse leakage currents after HTSS and HTRB stresses at different test temperatures are mainly due to the thermionic emission with the image force barrier height lowering. However, it is not the same phenomenon after HTRB stress. And the stability of VR under HTRB test is better than the one under HTSS test, which may be due to the migration and accumulation of charge during exposure to HTRB.

Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress

The origin of dielectric breakdown was studied on 4H-SiC MOSFETs that failed after three months of high temperature reverse bias stress. A local inspection of the failed devices demonstrated the presence of a threading dislocation (TD) at the breakdown location. The nanoscale origin of the dielectric breakdown was highlighted with advanced high-spatial-resolution scanning probe microscopy (SPM) techniques. In particular, SPM revealed the conductive nature of the TD and a local increase of the minority carrier concentration close to the defect. Numerical simulations estimated a hole concentration 13 orders of magnitude larger than in the ideal 4H-SiC crystal. The hole injection in specific regions of the device explained the failure of the gate oxide under stress. In this way, the key role of the TD in the dielectric breakdown of 4H-SiC MOSFET was unambiguously demonstrated.

Hole-Induced Degradation in ${E}$ -Mode GaN MIS-FETs: Impact of Substrate Terminations

We conducted reliability characterization under reverse-bias stress (i.e., stress at OFF-state with high ${V}_{\text {DS}}$ ) on the ${E}$ -mode GaN metal–insulator–semiconductor field-effect-transistors (MIS-FETs) with various substrate terminations. The MIS-FETs with floating substrate (FS) show worse threshold voltage ( ${V}_{\text {TH}}$ ) stability than that with a grounded substrate. A non monotonic dependence of ${V}_{\text {TH}}$ shifts and OFF-state time-to-breakdown ( ${t}_{\text {BD}}$ ) on the positive substrate bias ( ${V}_{\text {sub}}$ ) was also observed. The underlying mechanisms are the different impacts of positive ${V}_{\text {sub}}$ on the drift of electrons and holes during the long-term stress. An important indication is that positive-biased and FS terminations should be restricted at OFF-state in order to obtain good ${V}_{\text {TH}}$ stability in applications of the GaN MIS-FET.

Hysteresis effect in current–voltage characteristics of Ni/n-type 4H-SiC Schottky structure**Project supported by the National Natural Science Foundation of China (Grant Nos. 61804118, 61774117, and 61774119), the Fundamental Research Funds for the Central Universities, China (Grant Nos. 20101185935 and 20106186647), the National Key Basic Research Program of China (Grant No. 2015CB759600), the Shaanxi Key Research and Development Program, China (Grant No.

Hysteresis current–voltage (I–V) characteristics are often observed in a highly non-ideal (n > 2) as-deposited nickel (Ni)/4H-SiC Schottky contact. However, we find that this kind of hysteresis effect also exists in an as-deposited Ni/n-type 4H-SiC Schottky structure even if the ideality factor (n) is less than 1.2. The hysteresis I–V characteristics is studied in detail in this paper by using the various measurements including the hysteresis I–V, sequential I–V sweeping, cycle I–V, constant reverse voltage stress (CRVS). The results show that the hysteresis I–V characteristics are strongly dependent on the sweeping voltage and post-deposition annealing (PDA). The high temperature PDA (800 °C) can completely eliminate this hysteresis. Meanwhile, the magnitude of the hysteresis effect is shown to decrease in the sequential I–V sweeping measurement, which is attributed to the fact that the electrons tunnel from the 4H-SiC to the localized states at the Ni/n-type 4H-SiC interface. It is found that the application of the reverse bias stress has little effect on the emission of those trapped electrons. And a fraction of the trapped electrons will be gradually released with the time under the condition of air and with no bias. The possible physical charging mechanism of the interface traps is discussed on the basis of the experimental findings.

Degradation mechanisms of bias stress on nitride-based near-ultraviolet light-emitting diodes in salt water vapor ambient

Degradation mechanisms of nitride-based near-ultraviolet (near-UV) light-emitting diodes (LEDs) were systematically analyzed by applying forward- and reverse-bias stresses to them in a salt water vapor ambient. The surface temperature of the forward-bias stress sample was higher than that of the reverse-bias stress sample. The high temperature of the forward-bias stress sample accelerated the chemical reaction of the device structure with salt water vapors and led to faster degradation. Composition analyses of the sample surface and cross-section were conducted to investigate the failure mechanism. The analyses results indicated that the erosion of the indium–tin–oxide layer enhanced the diffusion of the conducting metal into the LED crystal. The proposed method can effectively characterize the quality of near-UV LEDs in a short duration.

Time-dependent characteristics and physical mechanisms of AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors under different bias conditions

We experimentally investigate the time-dependent degradation of AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors subjected to different bias conditions. By means of the combined performance under OFF/SEMI-ON/ON state bias conditions, the dependence of threshold voltage (Vth), maximum transconductance (gm) and saturation drain current (Idsat) on stress mode are revealed. In the OFF-state, with the high temperature reverse bias stress, the main mechanism is the charge-trapping in the gate dielectric layer, leading to the recoverable negative shift of the Vth. In the SEMI-ON-state, because of the hot-carrier injection, the hot electrons could break the Si–H bonds, resulting in the generation of interface states and can also be captured by the trap states in the AlGaN barrier or GaN buffer. This effect will cause the decrease of saturation drain current and an unrecoverable Vth negative shift. In the ON-state, due to the attenuation of hot electrons effect, Vth hardly changes, while Idsat has a dramatic decrease caused by the self-heating effect. Low frequency noise characteristics were used to extract the defect state density, which then increases by about three orders of magnitude after SEMI-ON-state stress.

Reverse-Bias Stress-Induced Electrical Parameters Instability in 4H-SiC JBS Diodes Terminated Nonequidistance FLRs

In this article, the breakdown voltage ( ${V}_{\text {BR}}$ ) shift of 4H-SiC Junction Barrier Schottky (JBS) diodes terminated by optimum nonequidistant field limiting rings (FLRs) subject to reverse-bias stress (RBS) has been investigated, and the corresponding mechanisms are studied in-depth. It can be observed that ${V}_{\text {BR}}$ gradually increases with increasing stress time, but there is no obvious shift of the forward voltage ( ${V}_{F}$ ). The increment in the magnitude of ${V}_{\text {BR}}$ induced by RBS testing is shown to depend strongly on the degree of applied reverse-bias voltage. The physical mechanism of ${V}_{\text {BR}}$ shift has been investigated and explained by means of numerical technical computer-aided design (T-CAD) simulations. Our analysis shows that the hole injection and trapping into SiO2 at the FLR terminal area are identified to be the main cause, resulting in the increase of ${V}_{\text {BR}}$ . Besides, a simple model is proposed to explain the behavior of ${V}_{\text {BR}}$ instability.

Reversible Efficiency Variation of Tandem Amorphous/Microcrystalline Si Photovoltaic Modules in Outdoor Operation

The Staebler-Wronski effect in amorphous silicon based photovoltaic devices is responsible for degradation of their power conversion efficiency, within approximately the first one thousand hours of light soaking. Several experimental studies led to highlight the performance instability phenomena for the mentioned devices, underling that recovery and improvement of such performance are observable, by subjecting such devices (both of single-junction and tandem types) to DC reverse bias stresses under illumination, or to operation in the Maximum Power Point (MPP) under variable conditions of temperature and illumination. In this work, we present and discuss the results of novel recent outdoor tests on stabilized specimens (i.e., exposed to 1000 h extended light soaking, before our tests) of tandem amorphous/microcrystalline Si (a-Si/µc-Si) photovoltaic (PV) minimodules operating in their MPP, by analyzing the causes of the performance instability effects, systematically observed on a daily scale. During the mentioned tests, we have monitored the solar cell operating temperature and the incident solar spectrum at various times in different days to verify the effect of cell temperature and solar spectrum changes on the cell performances. The experimental results show a clear correlation between performance improvements of the photovoltaic modules and their thermal history during the outdoor tests, proving the interplay between defect build-up at a lower temperature and defect annealing at a higher temperature, taking place in the solar cells operated in MPP during conventional outdoor operation.

Reliability concern of quasi-vertical GaN Schottky barrier diode under high temperature reverse bias stress

Abstract In this paper, the reliability of quasi-vertical GaN Schottky barrier diodes under high temperature reverse bias (HTRB) stress has been investigated. The test results indicate that the stress applied on the devices makes reverse leakage current decrease, but the forward performance, capacitance and reverse recovery performance show negligible changes. With the help of experiments and T-CAD simulations, it is demonstrated that there is trapping process of hot electrons along vertical sidewall of the device under high reverse voltage stress, which leads to the decrease of reverse leakage current. An empirical model can be used to predict the variations and good coincidences can be observed based on the acquired experiment data. Moreover, long time over voltage stress on the device leads to the direct failure. By using the infrared thermography analysis and T-CAD simulations, the failure mechanism has been also illustrated.

Enhanced Gate Reliability in GaN MIS-FETs by Converting the GaN Channel into Crystalline Gallium Oxynitride

We demonstrated the enhanced threshold voltage (VTH) stability and gate reliability of the enhancement-mode (E-mode) GaN-based MIS-FETs under reverse-bias stress (i.e., stress at off-state with high drain voltage), which is achieved by converting the conventional GaN (Eg ∼ 3.4 eV) channel into a crystalline GaOxN1–x (Eg ∼ 4.1 eV) layer. In the MIS-FETs stressed at off-state with a large drain voltage, holes will be generated in the high-electric-field region by impact ionization, and subsequently, degradation of the gate dielectric is caused by the holes passing through the dielectric film. As the valence band offset between the GaOxN1–x and GaN is ∼0.6 eV, an energy barrier for holes will be formed surrounding the gate, which can prevent holes from flowing to the gate side and therefore reduce the hole-induced gate dielectric degradation. The crystalline gallium oxynitride layer converted from GaN could also be a promising method to improve channel reliability for many GaN-based structures and processes.

Reliability and lifetime estimations of GaN-on-GaN vertical pn diodes

This work presents the first lifetime estimation of vertical GaN-on-GaN pn diodes using a step stress measurement technique with analysis not previously applied to GaN. The failure mechanism is surface breakdown, indicating that the lifetime is not yet limited by intrinsic material properties but by device design. As such, the mean time to failure depends on the peripheral length of the device. An estimated operating MTTF of 10 years at a reverse bias stress of 260 V was calculated for a 126 μm diameter diode.

Hole-Induced Threshold Voltage Shift Under Reverse-Bias Stress in E-Mode GaN MIS-FET

Under reverse-bias stress (i.e., OFF-state stress with ${V} _{\text {GS}} ) with high drain voltage, ultraviolet (UV) illumination and larger negative gate bias are found to accelerate the positive shift in threshold voltage ( ${V}_{\text {TH}}$ ) of enhancement-mode GaN MIS-FETs with fully recessed gate. These results suggest a hole-induced degradation mechanism. In the absence of UV illumination, holes could be generated by impact ionization in the high electric-field region, which is initiated by electrons injected from the source through the buffer layer. With a larger negative gate bias, more holes will flow to the gate side and pass through the silicon nitride (SiN x ) gate dielectric, as SiN x does not present any energy barrier to holes. The enhanced hole transport through the dielectric under large negative gate bias could accelerate new defects generation and therefore result in the larger positive threshold voltage shifts.

Performance increase of tandem amorphous/microcrystalline Si PV devices under variable illumination and temperature conditions

Wear out in the maximum power point condition of tandem microcrystalline Si/amorphous Si thin film PV modules due to extended light soaking is a well-known effect due to the Staebler–Wronski mechanism [1]. However, several studies [2–8] on a-Si:H single junction and tandem solar cells, have shown that, under suitable conditions of electric field in reverse bias, illumination, especially at well-defined wavelengths (700–800 nm), and temperature conditions, an improvement of the cell main electric parameters is possible. In this work, we report on new stress tests performed on tandem amorphous Silicon PV devices (both non-stabilized and stabilized), highlighting the improvement of their electrical performances, founded both in the tests performed on non-stabilized samples (essentially due to the reverse bias stresses carried out in these tests) and in the outdoor tests on stabilized samples (not subjected to reverse bias stresses) going from morning to afternoon illumination. In the latter tests, the efficiency improvement observed in the afternoon is stable overnight and observed also in the early stages of the morning outdoor test in the following day. Possible causes of such effect are discussed.

Effects of surface plasma treatment on threshold voltage hysteresis and instability in metal-insulator-semiconductor (MIS) AlGaN/GaN heterostructure HEMTs

In a bid to understand the commonly observed hysteresis in the threshold voltage (VTH) in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors during forward gate bias stress, we have analyzed a series of measurements on devices with no surface treatment and with two different plasma treatments before the in-situ Al2O3 deposition. The observed changes between samples were quasi-equilibrium VTH, forward bias related VTH hysteresis, and electrical response to reverse bias stress. To explain these effects, a disorder induced gap state model, combined with a discrete level donor, at the dielectric/semiconductor interface was employed. Technology Computer-Aided Design modeling demonstrated the possible differences in the interface state distributions that could give a consistent explanation for the observations.

Dependence of ${V}_{\text {TH}}$ Stability on Gate-Bias Under Reverse-Bias Stress in E-mode GaN MIS-FET

In this letter, we investigated the threshold voltage ${V}_{\text {TH}}$ stability under reverse-bias step-stress in the E-mode LPCVD-SiNx/PECVD-SiNx/GaN MIS-FET. Under the OFF-state reverse-bias stress with the same net gate-to-drain voltage ( ${V}_{\text {GD}}$ ), the ${V}_{\text {TH}}$ shift shows an obvious dependence on the negative gate bias. With a ${V}_{\text {GS}}$ of 0 V, the ${V}_{\text {TH}}$ shift is small and recoverable, while the ${V}_{\text {TH}}$ shifts are substantially larger with more negative gate bias ( ${V}_{\text {GS}}=-20$ V). This larger ${V}_{\text {TH}}$ shifts caused by the negative ${V}_{\text {GS}}$ can be explained with a hole-induced degradation model. An important indication revealed by this model is that negative gate bias should be well confined in high-power switching applications of GaN E-mode MIS-FET for a stable ${V}_{\text {TH}}$ .

Role of AlGaN/GaN interface traps on negative threshold voltage shift in AlGaN/GaN HEMT

This article reports negative shift in the threshold-voltage in AlGaN/GaN high electron mobility transistor (HEMT) with application of reverse gate bias stress. The device is biased in strong pinch-off and low drain to source voltage condition for a fixed time duration (reverse gate bias stress), followed by measurement of transfer characteristics. Negative threshold voltage shift after application of reverse gate bias stress indicates the presence of more carriers in channel as compared to the unstressed condition. We propose the presence of AlGaN/GaN interface states to be the reason of negative threshold voltage shift, and developed a process to electrically characterize AlGaN/GaN interface states. We verified the results with Technology Computer Aided Design (TCAD) ATLAS simulation and got a good match with experimental measurements.

On the Understanding of Cathode Related Trapping Effects in GaN-on-Si Schottky Diodes

Cathode related current collapse effect in GaN on Si Schottky barrier diodes is investigated in this paper. Capacitance and current relaxation measurements on diodes and gated-Van Der Pauw are associated with temperature dependent dynamic ${R_{\mathrm{ ON}}}$ transients analysis to identify the parasitic trapping locations in the devices. We show here that the main part of the current collapse at the cathode comes from a combination of electron trapping in the passivation layer and in a carbon related trap in the GaN buffer layers ( ${E_{A}} = \mathrm {E_{T}} - {E_{V}} \simeq 0.9 \,\mathrm {eV}$ ) that can be studied independently by using the appropriate stress configurations. These two parasitic effects can lead to long recovery time (>1 ks) after reverse bias stress.

Progressive current degradation and breakdown behavior in GaN LEDs under high reverse bias stress**Project supported by the National Natural Science Foundation of China (Grant Nos. 61504050 and 11604124), the Natural Science Foundation of Jiangsu Province, China (Grant Nos. BK20140168 and BK20150158), and the Fundamental Research Funds for the Central Universities, China (Grant Nos. JUSRP51628B and JUSRP51510).

The progressive current degradation and breakdown behaviors of GaN-based light emitting diodes under high reverse-bias stress are studied by combining the electrical, optical, and surface morphology characterizations. The current features a typical “soft breakdown” behavior, which is linearly correlated to an increase of the accumulative number of electroluminescence spots. The time-to-failure for each failure site approximately obeys a Weibull distribution with slopes of about 0.67 and 4.09 at the infant and wear-out periods, respectively. After breakdown, visible craters can be observed at the device surface as a result of transient electrostatic discharge. By performing focused ion beam cuts coupled with scan electron microscope, we observed a local current shunt path in the surface layer, caused by the rapid microstructure deterioration due to significant current heating effect, consistent well with the optical beam induced resistance change observations.

Characterization of HTRB stress effects on SiC MOSFETs using photon emission spectral signatures

This paper presents a reliability study of a 1.2kV SiC MOSFET under HTRB (High Temperature Reverse Bias stress by the photon emission (PE) and the spectral photon emission (SPE) techniques. The electrical characteristics analysis suggests failures related to the PN junction degradation. This hypothesis is confirmed by the PE and SPE techniques.

A robust and area-efficient guard ring edge termination technique for 4H-SiC power MOSFETs

A robust and area efficient adjusted multi-section guard rings (AMS) edge termination structure is employed to a 4H-SiC power MOSFET device rated at 1.7kV and fabricated without extra process steps or masks in this paper. The lightly doped p-type guard ring with adjusted multi-section spacing, which is similar with varied lateral doping technology widely used in silicon edge termination, creates a smoother and more uniform surface electric field distribution across all rings, resulting in a higher reverse blocking voltage with minimal edge termination area. The fabricated AMS-MOSFET devices with an active area of 2.5mm2 have reverse blocking voltage up to 2.5kV at room temperature. Compared to the conventional SiC MOSFETs with the uniform ring spacing, the AMS-MOSFET with the same edge termination area shows more than a 25% increase in the reverse blocking voltage. Furthermore, high-temperature reverse bias stress test is performed to verify junction and termination robustness of the AMS-MOSFET device. A small variation in the reverse blocking voltage and drain-source leakage current are achieved under 168h high-temperature reverse bias stress with the drain bias of 1360V at ambient temperature of 175°C, which suggests an expected robustness in high power application for the fabricated SiC MOSFET with the AMS structure.