Test concept for a direct correlation between dislocations and the intrinsic degradation of lateral PIN diodes in GaN-on-Si under reverse bias

Abstract

Although often discussed, the role of threading dislocations (TDs) in the degradation of lateral GaN-on-Si p-GaN HEMTs under reverse bias stress test (RBST) has never been clearly shown in experiment until today. Here we present a novel test concept to establish a direct correlation between dislocations and degradation sites in RBST and demonstrate it on lateral p-GaN/AlGaN/GaN PIN diodes. By scaling down structures down to ~500 nm width, the point of degradation is always forced to be located at a defined position, independent of the local position of TDs. Furthermore, an integrated serial p-GaN resistor has been implemented with the PIN diode, which effectively limits the current and protects the device from a large meltdown due to parasitic capacitances and enables TEM analysis of structural degradation. A large quantity of lateral PIN devices exhibit a similar time-to-breakdown under RBST, indicating the intrinsic nature of this failure mode. Planar TEM analysis of a degraded and failed device clearly reveals structural damages and a breakdown of the AlGaN barrier as the failure signature. A combined planar and cross-sectional TEM lamella analysis approach of the expected failure site was introduced and applied. The results unambiguously show, that the observed degradation in the AlGaN barrier, which is attributed to the intrinsic failure mode, is not directly linked to the position of a dislocation.