Reverse bias stress test of GaN HEMTs for high-voltage switching applications

Abstract

The degradation of packaged GaN HEMTs for high power applications has been studied under long term reverse bias step stress tests. Increases of leakage current and dynamic R on resistance have been found. This degradation is possibly caused by the formation of localized defects which have been observed by backside electroluminescence imaging. In addition the effect of device layout and substrate material on the dynamic R on as well as its temperature, recovery behavior, and drain voltage dependence have been investigated on wafer-level. The recovery behavior and the temperature dependence indicate that the dynamic R on resistance increase is caused by surface or buffer carrier trapping. By reducing the buffer trap density the dynamic R on resistance was reduced. A slightly higher dynamic R on of GaN HEMTs on silicon compared to transistors on SiC substrate has been observed.