Retention Errors Research Articles

Enhancing Data Integrity with Efficient Retention-Refilling Programming Schemes

The retention error has become one of the most challenging reliability issues of flash memory due to the shrinking of the technology nodes. To enhance data integrity by resolving the retention error issues for 3D MLC flash memory devices (e.g., SSDs and SD cards), many excellent works that exploited in-place reprogramming and data refreshing concepts have been proposed in recent years. However, these approaches could result in additional issues, such as programming disturbance and performance overhead (e.g., unavoidable data refreshing and a larger amount of program and verify shots). This work is motivated by the need to explore a low-cost solution to resolve retention error issues without incurring negative impacts caused by conventional refresh-based and in-place reprogramming approaches. As a result, this work exploits the characteristics of the cell's V t distribution and proposes the novel concept of "retention-refilling" to enhance data integrity. With such an idea, a retention-refillable programming scheme is proposed to improve flash reliability and mitigate performance overheads by trading data refreshing with retention-refilling. The capability of the proposed scheme is evaluated by a series of experiments, for which we have very encouraging results.

Body Water Compartment and Sympathovagal Balance: Association with Visuomotor Retention in Young Adults

Cognitive functions are important for visuomotor learning and are associated with physiological factors such as body fluid compartment and cardiovascular reactivity. Previous studies found that body fluid compartment is associated with brain blood flow, which is regulated via sympathovagal balance. However, more evidence is needed to determine whether body fluid compartment and cardiovascular reactivity are associated with visuomotor learning. The purpose of this study was to explore the relationship of body fluid compartment and cardiovascular reactivity to visuomotor learning. We hypothesized that these physiological factors are associated with overall learning retention using upper extremity (including feedforward, volitional, and feedback conditions). Methods: Thirty young adults (12 males, 24.6 ± 3.9 years, right hand dominant) participated in this study. Participants tracked a sinusoidal wave with left arm at pre-test, learning, and post-test sessions on the first visit and at retention test session on the second visit seven days later. Participants performed one set of nine trials during each test and five sets of three trials during learning. Resistance and wave velocity were different in each trial. Learning error was calculated by the averaged absolute distance between the tracking line and the target line. Heart rate (HR), systolic blood pressure (SBP), and low to high frequency power ratio of heart rate variability (LF/HF) were continuously recorded during baseline before pre-test and during tests and learning. We analyzed participants’ extracellular to intracellular body water ratio (ECW/ICW) using an InBody body composition analyzer and tested their cognitive function with Picture Sequence Memory (PSMT), Pattern Comparison Processing Speed, Dimensional Change Card Sort, Flanker Inhibitory Control and Attention, and List Sorting Working Memory Tests from NIH Cognitive Toolbox. Data were statistically analyzed using linear regression analysis and quartile analysis. Results: ECW/ICW was associated with young adults’ ability to retain visuomotor learning after one week (R2 = 0.138, p = 0.043), whereas HR, SBP, and LF/HF at each session were not significantly associated with visuomotor retention. No differences were found in pre-test error among quartiles of five cognitive tests. Significant differences in retention error among quartiles were only found in PSMT, with participants scoring in the highest quartile of PSMT having lower SBP during the first visit and lower retention error compared to the lowest quartile. This finding suggests that young adults with better episodic memory were less stressed during learning and had better visuomotor retention. Conclusion: These findings support that ECW/ICW is associated with not only cognitive function but also visuomotor retention. In addition, cardiovascular reactivity during visuomotor learning may provide information for retention behavior. Relationship of body water compartment and sympathovagal balance to feedforward and feedback conditions in learning will be further discussed. Research Support: This study was funded by the Eunice Kennedy Shriver National Institute of Child Health and Human Development: R01HD084645, R01HD082109. This is the full abstract presented at the American Physiology Summit 2024 meeting and is only available in HTML format. There are no additional versions or additional content available for this abstract. Physiology was not involved in the peer review process.

Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement

Considering 3D NAND flash has a new property of process variation (PV) , which causes different raw bit error rates (RBER) among different layers of the flash block. This paper builds a mathematical model for estimating the retention errors of flash cells, by considering the factor of layer-to-layer PV in 3D NAND flash memory, as well as the factors of program/erase (P/E) cycle and retention time of data. Then, it proposes classifying the layers of flash block in 3D NAND flash memory into profitable and unprofitable categories, according to the error correction overhead. After understanding the retention error variation of different layers in 3D NAND flash, we design a mechanism of data placement, which maps the write data onto a suitable layer of flash block, according to the data hotness and the error correction overhead of layers, to boost read performance of 3D NAND flash. The experimental results demonstrate that our proposed retention error estimation model can yield a R 2 value of 0.966 on average, verifying the accuracy of the model. Based on the estimated retention error rates of layers, the proposed data placement mechanism can noticeably reduce the read latency by 29.8 % on average, compared with state-of-the-art methods against retention errors for 3D NAND flash memory.

Accelerated Editing Method for Vehicle Durability Fatigue Load Spectrum Based on Wigner-Ville Transform.

A Wigner-Ville transform-based (WVT-based) load spectrum fast editing method for vehicle parts is proposed to improve the efficiency of durability tests. In this method, the instantaneous energy spectrum (IES) of the original time-domain signal is obtained via the Wigner-Ville transform, which is used as a criterion to identify time-domain points of ineffective damage contribution. A genetic algorithm (GA) based threshold optimization model is also proposed to automatically set the threshold of the IES under consideration of the relative damage requirements and statistical parameters of the signal. The effectiveness of the above proposed editing method is demonstrated by compiling an SUV's suspension coil spring signal obtained from physical sensor-based measurements. Meanwhile, the same spectrum is also processed using time-domain editing, Short-time Fourier-transform, and S-transform methods for comparison. The results show that the WVT-based edited spectrum has a time-duration retention ratio of about 76.30%, which is significantly superior to other methods, with the same pseudo-damage retention and statistical parameter error constraints. Moreover, in combination with the fatigue simulation analysis, it verifies that the load effect of the edited spectrum matches well with that of the original. Thus, the proposed method is considered more effective for compiling component load signals in vehicle acceleration durability tests.

DNN-based error level prediction for reducing read latency in 3D NAND flash memory

3D NAND Flash memory still suffers from many reliability issues in practice, such as endurance and data retention errors. Meanwhile, due to process variation, pages with different layers show different error characteristics even in the same block. In this paper, we firstly propose a deep neural network-based codeword error level prediction model that can effectively predict the level of codeword errors, and we consider all the main factors that affect the codeword errors, including the P/E cycles and retention time, the location information of the codeword. The new network structure can effectively reduce the weight size by approximately 27% without loss of accuracy compared to traditional neural network. Based on this prediction model, we further propose an optimized scheme to reduce the read latency of the system. The results of the model prediction can help the controller to choose a suitable decoding scheme, thus reducing the overall read latency. Experiments show that the proposed network can predict the error level of the codeword to over 97% accuracy, and also significantly help to improve the average read performance with a maximum latency reduction of 45.3%.

Characteristic time of transition from write error to retention error in voltage-controlled magnetoresistive random-access memory

Voltage controlled magnetoresistive random access memory (VC MRAM) is a promising candidate for a future low-power high-density memory. The main causes of bit errors in VC MRAM are write error and retention error. As the size of the memory cell decreases, the data retention time decreases, which causes a transition from the write-error-dominant region to the retention-error-dominant region at a certain operating time. Here we introduce the characteristic time of the transition from the write-error-dominant region to the retention-error-dominant region and analyze how the characteristic time depends on the effective anisotropy constant, K0. The characteristic time is approximately expressed as tc=2wτ, where w is the write error rate, and τ is the relaxation time derived by Kalmkov (2004). We show that for large K0, tc increases with increase of K0 similar to τ. The characteristic time is a key parameter for designing the VC MRAM for the variety of applications such as machine learning and artificial intelligence.

Temperature Estimation of HBM2 Channels with Tail Distribution of Retention Errors in FPGA-HBM2 Platform

High-bandwidth memory 2 (HBM2) vertically stacks multiple dynamic random-access memory (DRAM) dies to achieve a small form factor and high capacity. However, it is difficult to diagnose HBM2 issues owing to their structural complexity and 2.5D integration with heterogeneous chips. The effects of the temperature at the base logic die (TL), and the refresh interval at the stacked DRAM dies, were experimentally investigated by counting the dynamic retention errors in the eight channels in an HBM2. TL was indirectly controlled by the heatsink temperature (TS). The lognormal distribution represents the distribution of the cell counts with varying refresh times. All Z-magnitudes (multiples of the distribution standard deviation) over the various refresh cycle times (RCTs) up to 2.045 s in a single channel at TL of 70 °C appeared below 4.4, which means that the error bits belong to the tail distribution. The Z-differences in the eight channels were distinctively larger than the Z-differences of the same channels at a constant temperature, demonstrating that the temperature difference in the stacked dies resulted in larger Z-differences. The largest Z-difference was 0.091 for all the channels at an RCT of 1.406 s, which was approximately 4.82 times smaller than the Z-difference between the TL temperatures of 70 °C and 80 °C in a single channel. The Z-difference between the TL temperatures of 70 °C and 72 °C in a single channel was approximately the same as the Z-difference in all the channels at an RCT of 2.045 s.

A shared page-aware machine learning assisted method for predicting and improving multi-level cell NAND flash memory life expectancy

NAND flash memory is widely used in consumer electronics, personal computers, and enterprise data storage servers. The most prevalent source of flash memory errors is retention errors, which are mainly caused by leakage of charges. It has been observed that inside the chip, some flash memory blocks exhibit greater endurance to the retention errors than others. In an effort to prolong life expectancy, previous studies focus on improving the Raw Bit Error Rate (RBER) metric at page and block levels, without due consideration of the geometry of shared pages. In this paper, the first insight we provide is that groups of shared pages have different RBER values, and should be analyzed separately. We use this insight to construct a machine learning model to predict the blocks which have less endurance, using the characterization data of new unused flash memory chip(s). This is accomplished by extracting location-sensitive and value-sensitive features from the shared pages group, and engineering them into more sophisticated and explainable features. Furthermore, we describe how our proposed prediction model can be used in combination with the existing flash translation layer (FTL) wear-leveling algorithm to increase lifetime. We evaluated the proposed prediction and lifetime improvement method for four different machine learning techniques, among which Support Vector Machine (SVM) achieved superior accuracy up to 85% at a lower computational overhead.

Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory

Owing to the effect of data retention noise in multi-level-cell NAND flash memory, the initial threshold-voltage distributions and read voltages can no longer be used to accurately calculate log-likelihood ratios (LLRs) as the retention time increases, thus causing retention errors. To solve this problem, we first utilize the so-called “correction factors” to optimize the LLR accuracy by maximizing the achievable rate of a flash-memory system without introducing extra memory-sensing operations. We further prove that the optimization of the correction factors is a convex optimization problem and can be solved analytically. To obtain the optimal correction factors, we propose two retention-error correction schemes, referred to as offline maximum-achievable-rate correction (MARC) algorithm and online MARC algorithm, which enable the flash-memory controller to utilize the corrected LLRs that are stored in a look-up table and correct the inaccurate LLRs in real time, respectively. Motivated by the variation characteristics of the threshold-voltage distributions, we also propose an enhanced expectation–maximization (EM) algorithm to reestimate their corresponding parameters, and then adjust the read voltages. By combining the enhanced EM algorithm with the MARC algorithms, an enhanced EM-based correction strategy is developed to further boost the retention-error endurance of flash memory while avoiding excessive memory-sensing overhead. Theoretical analyses and simulation results illustrate the superiority of the proposed correction mehtods in terms of the robustness against retention errors.

Differential Evolution Algorithm With Asymmetric Coding for Solving the Reliability Problem of 3D-TLC CT Flash-Memory Storage Systems

In recent years, NAND flash memory has been widely used in mobile devices, laptops, desktops, and data center storage systems due to its low-power consumption, high performance, high density, lightweight, shock resistance, and high-reliability natures. However, as the stacked layers and the storage density increase, flash memory also suffers from a higher raw bit error rate (RBER) and shorter lifetime. Observing that reliable cell states suffer from less data retention errors and program disturbance, we propose a differential evolution coding scheme to increase the probability of storing data in more reliable cell states, thereby reducing the RBER. We conducted the experiments over a development platform of SSD storage device with 3D-TLC charge trap (CT) NAND flash memory. The experimental results showed that the proposed differential evolution algorithm with asymmetric coding scheme could averagely reduce RBER by 48.88%, 65.45%, 52.61%, 61.99%, 80.19%, and 33.18% compared with baseline, asymmetric coding algorithm, asymmetric coding scheme with stripe-pattern elimination algorithm, UAC- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> LC, word-line batch score modulation programming, and SCB schemes.

On removing conflicts for machine learning

A Machine Learning (ML) system learns from a set of samples called the training set. In some cases, the training set may have learning conflicts that affect the performance of the machine learning system. A learning conflict is produced when two or more samples in a dataset have similar input values but different target values. We propose a method to remove learning conflicts from a dataset in this work. Our method is based on a genetic algorithm tries to keep those samples that free of conflicts and intents to remove those samples with conflicts. Each individual in the genetic algorithm represents a possible dataset. We introduce the concept of retention error in the fitness function, which describes how many samples are kept while removing learning conflicts. Additionally, the fitness function comprises the Mean-Squared Error (MSE) that validates the machine learning performance. The algorithm is designed to keep as many samples as possible while the machine learning system exhibits the highest possible performance. Therefore, the proposal consists in cleaning first the dataset that compares and highlights the individual with the best performance in the Genetic Algorithm (GA), recommending which samples must be included for training and testing. Three different datasets with learning conflicts are used to test the proposed methodology. Besides, one artificial neural network is trained using the datasets with learning conflicts for each dataset. After removing the conflicts, a second artificial neural network is trained using the cleaned datasets. A noticeable reduction in the mean-square error is observed when the neural network is trained using the cleaned dataset.

DRAM-based Physically Unclonable Functions and the Need for Proper Evaluation

Dynamic Random-Access Memory (DRAM)-based Physically Unclonable Functions (PUFs) are a part of the Physical Layer Security (PhySec) domain. Those electrical PUFs are memory based and exhibit a high availability, Shannon Entropy, low energy consumption and high amount of Challenge Response Pairs (CRPs). Because of those properties, the DRAM PUF is a promising approach for security applications in the Industrial Internet of Things (IIoT) context as well as securing the Sixth-Generation (6G) Wireless Systems and edge computing.&#x0D; DRAM, with its most common one-Transistor one-Capacitor (1T1C) architecture, and as a volatile memory is embedded in almost every modern computing unit. Regarding the PUF security applications, four main types of applications are currently distinguished in the scientific community: Retention Error, Row Hammer, Startup and Latency PUFs. Thereby these differ in their procedure in how responses are generated as well as by the physical mechanisms. Each of them with varying properties in terms of availability, reliability, uniqueness and uniformity.&#x0D; To examine this, and to obtain comparable results, this work proposes to compare the four different DRAM-PUF types i) with the same metrics of evaluation and ii) implemented on the same DRAM cells. This represents both the difference with regard to the work done in the literature and the added value of this work presented. As far as known, there is no work to date that performs the intended evaluations using the same evaluation platform under the identical conditions. However, this is required for comparable results.&#x0D; This consistent comparison is ensured by a self-developed and implemented evaluation platform, which is accordingly equipped with a significant number of DRAMs. By an appropriate high volume of measurements, a corresponding resolution will be given. Monitoring the environmental conditions prevents from wrong interpretations caused by environmental influences but also provides useful context information. Furthermore, a detailed technical and physical background will be described. The results of this approach will assist by the consideration of which DRAM-PUF is appropriate in which (environmental) conditions and thereby provide a guideline for practitioners.

DRAM Retention Behavior with Accelerated Aging in Commercial Chips

The cells in dynamic random access memory (DRAM) degrade over time as a result of aging, leading to poor performance and potential security vulnerabilities. With a globalized horizontal supply chain, aged counterfeit DRAMs could end up on the market, posing a significant threat if employed in critical infrastructure. In this work, we look at the retention behavior of commercial DRAM chips from real-time silicon measurements and investigate how the reliability of DRAM cells degrade with accelerated aging. We analyze the retention-based errors at three different aging points to observe the design-induced variations, analyze the pattern dependency, and explore the impacts of accelerated aging for multiple DRAM vendors. We also investigate the DRAM chips’ statistical distribution to attribute the vital wear-out effects present in DRAM. We see a continuous increase in retention error as DRAM chips age and therefore infer that the aged retention signatures can be used to differentiate recycled DRAM chips in the supply chain. We also discuss the roles of device signature in DRAM aging and aging-related security implication on DRAM row-hammer error.

Retention failure recovery technique for 3D TLC NAND flash memory via wordline (WL) interference

The non-volatility of NAND flash memory is guaranteed only when data errors are within the ECC correction capability. With data errors exceeding ECC correction capability due to the retention process, the data recovery technique is a straightforward way to reduce retention errors to be correctable by ECC. In this paper, a high-efficient data recovery technique is proposed. Firstly, the WL Interference (WI) is utilized to recharge retention-failed cells. Retention errors are reduced with low operation latency. Secondly, the rewriting part in the data recovery technique is optimized by adaptively increasing the program verify voltage. Retention time is thus extended. The experimental results show that the proposed data recovery technique outperforms the state-of-the-art ADROP technique in both data recovery efficiency and capability by 12.92x and 2.28x respectively. In the 3 K PE cycles condition, the retention time is extended by 83.3x at most with proposed technique, which is 2.6x longer than the ADROP technique.

Design and Depth Control of a Buoyancy-Driven Profiling Float.

This paper presents the design and fabrication of a profiling float primarily used for thermocline observations and tracking, with an emphasis on depth control performance. The proposed float consists of a frame-type electronic chamber and a variable buoyancy system (VBS) actuator chamber. Components or sensors can be added or removed according to specific requirements. All components were off the shelf, which lowered the cost of the float. In addition, a segment PD control method is introduced. Simulink results showed that there was no need to change any parameter when carrying out tasks at different depths. This method is superior to the traditional PD control and sliding mode control (SMC). In the process of diving, the speed could be well controlled to less than 0.2 m/s. We completed depth determination and control method validation in Qiandao Lake. The final results were consistent with the simulation results, and the maximum depth retention error was less than 0.3 m. Field tests also demonstrated that the prototype float can be used for thermocline observations in the upper layer of seawater or lake water.

Computation-in-memory simulation platform to investigate inference accuracy degradation by device non-ideality interactions in deep neural network applications

This paper proposes a comprehensive computation-in-memory (CiM) simulation platform. The platform has the capability to emulate the degradation of inference accuracy caused by device non-ideality. In this paper, the effect of non-ideality by assuming non-volatile memory devices such as PRAM, ReRAM, MRAM, and FeFET in CiM were investigated. As the device is non-ideality, multi-level cell operation, conductance variation during verify-program, data retention error, sense amplifier offset, read current fluctuation, and device failure are considered. First, the acceptable amount of a single non-ideality was investigated. The results address that the conductance shift has much more of an adverse impact than conductance variation on inference accuracy in CiM. In the second place, interaction among multiple device non-idealities were also comprehensively investigated. The platform reveals paradoxical results that the inference accuracy of the combination of uniform shift and low conductance asymmetric error is higher than that of a single low conductance asymmetric error under specific conditions.

Error inconsistency does not generally inhibit saccadic adaptation: Support for linear models of multi-gainfield adaptation.

This study examined saccade adaptation induced by intrasaccadic target steps (ITS). By manipulating the ITS, we investigated potential effects of the consistency of the feedback error on saccade adaptation, which would provide evidence against the linearity of standard models of visuomotor adaptation. Previous studies addressing saccade adaptation arrived at different interpretations, but in these experiments only a single saccade amplitude was trained rather than a variety of saccade amplitudes in random order (mixed training). We extend previous studies by testing for effects of error consistency under additional control conditions described by the factors training protocol (single‐amplitude/mixed), ITS direction (onward/backward), and adaptation phase (training/washout). Adaptation dynamics were assessed using a model of “multi‐gainfield adaptation” developed by tailoring an existing linear model for visuomotor adaptation of movements with multiple target positions to gain adaptation of saccades with multiple amplitudes. The total adaptive change did not depend on the consistency of the ITS in either mixed or single‐amplitude training. The initial adaptation speed was lower with inconsistent ITS. However, the effect on adaptation speed occurred only during amplitude reduction and not during enlargement or washout. These results corroborate the linearity of saccade adaptation in that the mean error is the main factor determining the total adaptive change, independent of error consistency. The multi‐gainfield adaptation model was confirmed in that the retention rate and error sensitivity did not depend on the training protocol. The absence of effects of error consistency on saccade adaptation is relevant in the context of adaptive deficits in movement disorders.

Differentiated Protection and Hot/Cold-Aware Data Placement Policies through k-Means Clustering Analysis for 3D-NAND SSDs

3D-NAND flash memory provides high capacity per unit area by stacking 2D-NAND cells having a planar structure. However, because of the nature of the lamination process, the frequency of error occurrence varies depending on each layer or physical cell location. This phenomenon becomes more pronounced as the number of flash memory write/erase (Program/Erasure) operations increases. Error correction code (ECC) is used for error correction in the majority of flash-based storage devices, such as SSDs (Solid State Drive). As this method provides a constant level of data protection for all-flash memory pages, there is a limitation in 3D-NAND flash memory, where the error rate varies depending on physical location. Consequently, in this paper, pages and layers with varying error rates are classified into clusters using the k-means machine-learning algorithm, and each cluster is assigned a different level of data protection strength. We classify pages and layers based on the number of error occurrences measured at the end of the endurance test, and for areas vulnerable to errors, it is shown as an example of providing differentiated data protection strength by adding parity data to the stripe. Furthermore, areas vulnerable to retention errors are identified based on retention error rates, and bit error rates are significantly reduced through our hot/cold-aware data placement policy. We show that the proposed differential data protection and hot/cold-aware data placement policies improve the reliability and lifespan of 3D-NAND flash memory compared with the existing ECC- or RAID-type data protection scheme.

Assessment of Cases of Complete Denture Fracture.

Background:There are many causes and reasons associated with fractures of complete dentures. The present study assessed case of complete denture fracture.Materials and Methods:One hundred and fifty complete denture wearers reported to the department of prosthodontics for correction of complete denture fracture were examined carefully. The factors such as retention, stability, and occlusal errors were recorded. Cause of denture fracture was recorded too.Results:Out of 150 patients, males were 80 and females were 70. The site of fracture was incisor area in 25, canine area in 30, midline in 50, molar area in 10, and maxillary tuberosity/retromolar pad area in 35 cases. The etiology of denture fracture was accidental fall in 42, poor fit in 28, poor occlusion in 40, material breakage in 25, and acrylic base defect in 15 cases. The difference was statistically significant (P < 0.05).Conclusion:Most common cause of denture fracture was accidental fall, poor fit, poor occlusion, and material breakage.

An Improved LDPC ECC based on System Level Reprogramming for MLC NAND Flash

With the ever-increasing requirement for higher performance of system and memory with a huge storage capacity, Multi-Level Cell (MLC) flash memory holds a dominant position in flash memory. However, more errors are observed in flash memory as the storage size increases. Thus, various error correction techniques (e.g., Hamming, BCH, LDPC) have been adopted to maintain the reliability of data stored in flash memory. Retention error, which occurs in data that is not accessed for a long period after stored, is the major contributor of flash memory error. The incidence of retention error is highly related to p-e (program-erase) cycle of flash memory. However, in system level, flash memory should be erased before modifying data even if ECC (Error correction code) decoding is completed. This erase operation increases the p-e cycle of flash memory, resulting in high incidence of retention error. This paper introduces a safe in-place reprogramming scheme at system level to optimally correct errors without erasing. Additionally, LDPC decoding scheme uses information about the uncorrected errors to improve the performance of the LDPC decoder. Through an experiment that simulates real NAND flash memory chips, safe reprogramming scheme at system level and proposed LDPC decoding method are explicitly demonstrated. As a result of proposed in-place reprogramming, reliable retention time of data is extended. Also, proposed LDPC decoding along with safe reprogramming scheme reduced the number of average iterations up to 33% while maintaining a robust correction ability.