Retargetable Compiler Research Articles

Application-specific SIMD synthesis for reconfigurable architectures

Application-specific instruction set extensions on reconfigurable hardware open up new opportunities for the embedded system designer. Although the flexibility offered by unrestricted instruction set extensions seems strongly attractive in first place, insufficient retargetable compiler support may hamper the benefits. It is therefore useful to reduce the design space of these instruction extensions to widely accepted tools supported instruction formats in order to capitalize on the existing resources. SIMD extensions have been proposed and implemented in the general-purpose processor domain but never brought to the embedded world due to the complexity, area, and energy consumption of SIMD model of computation. In this paper, we propose an application-specific AltiVec compatible customized SIMD synthesis flow well adapted to FPGA platforms which solve both compatibility and customization issues.

Post-compilation optimization for multiple gains with pattern matching

Many existing retargetable compilers for ASIPs and domain-specific processors generate low quality code since the compiler is not able to fully utilize the intricacies of ISA of these processors. Hence, there is a need to further optimize the code produced by these compilers. In this paper, we introduce a new post-compilation optimization technique which is based on finding repeating instruction patterns in generated code and replacing them with their optimized equivalents. The instruction patterns to be found are represented by finite state machines which allow encapsulation of multiple patterns in just one representation, and instructions in a pattern to be not necessarily lexically adjacent. We also present a conflict resolution algorithm to select an optimization whenever a set of instructions fall under two or more different patterns of which only one can be applied on the basis of code size, cycle count or switching activity improvement. We tested this technique on the compiled binaries of ARM and Intel processors for code size improvement. We discuss the possible applications of this strategy in design space exploration (DSE) of embedded processors.

Retargetable compilers and architecture exploration for embedded processors

Retargetable compilers can generate assembly code for a variety of different target processor architectures. Owing to their use in the design of application-specific embedded processors, they bridge the gap between the traditionally separate disciplines of compiler construction and electronic design automation. In particular, they assist in architecture exploration for tailoring processors towards a certain application domain. The paper reviews the state-of-the-art in retargetable compilers for embedded processors. Based on some essential compiler background, several representative retargetable compiler systems are discussed, while also outlining their use in iterative, profiling-based architecture exploration. The LISATek C compiler is presented as a detailed case study, and promising areas of future work are proposed.

Retargetable code generation for application-specific processors

An approach of intelligent retargetable compiler is introduced to overcome the gap between hardware and software development and to increase performance of embedded systems. It focuses on knowledgeable treatment of code generation where knowledge about target microprocessor architecture and human-level heuristics are integrated into compiler expert system. Structure of an experimental compiler supporting code generation for DSPs and VLIW-DSPs is described. A technique to detect optimal instruction set architecture for program execution is presented. Results of code generation experiments are presented for DSPstone benchmarks.

Lcc.NET: targeting the .NET Common Intermediate Language from Standard C

AbstractThe core of the Microsoft .NET platform includes a new virtual machine (VM), the Common Intermediate Language, also known as MSIL. Unlike most other VMs, including the Java VM, MSIL is specifically designed to support a wide range of languages. While it is designed primarily for type‐safe, object‐oriented languages, it also has facilities that support both low‐level languages and very high‐level languages. For example, it accommodates unsafe pointer arithmetic and tail calls. This paper describes the implementation of a MSIL back end for lcc, a retargetable compiler for Standard C. C is at one end of the range of languages that MSIL intends to support and lcc is just about the simplest ‘real’ C compiler that is widely available. Porting lcc to MSIL thus provides a realistic test of how well MSIL supports this class of languages and provides a glimpse at its performance costs. This effort succeeded, but static initializations, function pointers, separate compilation and address arithmetic were major problem areas. These problems also suggested improvements to lcc's code‐generation interface and they exposed a long‐standing error in the lcc front end. Preliminary measurements suggest that programs compiled by the MSIL back end run two to three times slower than those compiled by lcc native Intel x86 back end, but the MSIL programs have some important diagnostic benefits. Copyright © 2003 John Wiley & Sons, Ltd.

Instruction scheduler generation for retargetable compilation

The availability of C compilers is crucial to the efficient design of embedded systems. Using virtual resources to automatically generate parts of a compiler's instruction scheduler from a formal processor description significantly reduces the overall scheduler generation time.

The design of a technology platform for custom VLIW embedded processors

The center of gravity in computing is shifting down once again, largely as a result of improving circuit density, which lowers the cost and size of computers, and enables them to be deployed in entirely new ways. Change on this scale has happened several times before, as we look back on the move from mainframes to minicomputers and then to desktop systems. Every generational change has driven an orders of magnitude increase in the range of applications and number of systems sold. We have already started the next generational move, which puts an entire system on a single chip, together with many other peripheral functions. This will make general-purpose machines even more affordable, but the really exciting thing will be the infusion of computers into a wide range of products that you do not think of as computers. The activities at HP Labs Cambridge (http://www. hpl.hp.com/cambridge) are centered on technologies at the border of CPU architectures, compilers and tools. We currently have projects on: dynamic optimization in a practical environment, embedded CPU cores customized for their intended use, retargetable ILP compiler backends in a product environment. This paper explores the design aspects of Lx, a Technology Platform for Custom VLIW Embedded Processors.

Embedded Control Systems Development with Giotto

Giotto is a principled, tool-supported design methodology for implementing embedded control systems on platforms of possibly distributed sensors, actuators, CPUs, and networks. Giotto is based on the principle that time-triggered task invocations plus time-triggered mode switches can form the abstract essence of programming real-time control systems. Giotto consists of a programming language with a formal semantics, and a retargetable compiler and runtime library. Giotto supports the automation of control system design by strictly separating platform-independent functionality and timing concerns from platform-dependent scheduling and communication issues. The time-triggered predictability of Giotto makes it particularly suitable for safety-critical applications with hard real-time constraints. We illustrate the platform-independence and time-triggered execution of Giotto by coordinating a heterogeneous flock of Intel x86 robots and Lego Mindstorms robots.

Processor modeling and code selection for retargetable compilation

Embedded processors in electronic systems typically are tuned to a few applications. Development of processor-specific compilers is prohibitively expensive and, as a result, such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a processor model that captures the connectivity, the parallelism, and all architectural peculiarities of an embedded processor. We also implemented a retargetable and optimizing compiler working on this model. We present the graph-based processor model, and formally define the code generation task as binding the intermediate representation of an application to this model. We also present a new method for code selection, based on this processor model, that is capable of handling directed acyclic graphs instead of trees.

Exploring Hypermedia Processor Design Space

Distributed hypermedia systems that support collaboration are important emerging tools for creation, discovery, management and delivery of information. These systems are becoming increasingly desired and practical as other areas of information technologies advance. A framework is developed for efficiently exploring the hypermedia design space while intelligently capitalizing on tradeoffs between performance and area. We focus on a category of processors that are programmable yet optimized to a hypermedia application. The key components of the framework presented in this paper are a retargetable instruction-level parallelism compiler, instruction level simulators, a set of complete media applications written in a high level language, and a media processor synthesis algorithm. The framework addresses the need for efficient use of silicon by exploiting the instruction-level parallelism found in media applications by compilers that target multiple-instruction-issue processors. Using the developed framework we conduct an extensive exploration of the design space for a hypermedia application. We find that there is enough instruction-level parallelism in the typical media and communication applications to achieve highly concurrent execution when throughput requirements are high. On the other hand, when throughput requirements are low, there is little value in multiple-instruction-issue processors. Increased area does not improve performance enough to justify the use of multiple-instruction-issue processors when throughput requirements are low. The framework introduced in this paper is valuable in making early architecture design decisions such as cache and issue width trade-off when area is constrained, and the number of branch units and instruction issue width.

The Design of the PROMIS Compiler—Towards Multi-Level Parallelization

Most systems that are under design and likely to be built in the future will employ hierarchical organization with many levels of memory hierarchy and parallelism. In order to efficiently utilize the multiple levels of parallelism available in the target architecture, a parallelizing compiler must orchestrate the interactions of fine-grain and coarse-grain program transformations. This article describes issues of multi-grain parallelization and how they are addressed in the PROMIS compiler design. PROMIS is a multilingual, parallelizing, and retargetable compiler with an integrated frontend and backend operating on a single unified and universal intermediate representation. PROMIS exploits multiple levels of static and dynamic parallelism, ranging from task- and loop-level parallelism to instruction-level parallelism, based on a target architecture description. The frontend and the backend are integrated through a unified internal representation common to the high-level, the low-level, and the instruction-level analyses and transformations.

Design challenges for new application specific processors

Embedded systems form a market that is already larger and growing more rapidly than that of general-purpose computers. In fact, real-time multimedia and signal processing embedded applications currently account for over 90% of all computer cycles. This article discusses challenges in developing retargetable compilers and synthesis tools for application-specific processor cores targeted at embedded portable digital communications and multimedia systems.

A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library

We address the problem of code generation for embedded DSP systems. Such systems devote a limited quantity of silicon to program memory, so the embedded software must be sufficiently dense. Additionally, this software must be written so as to meet various high-performance constraints. Unfortunately, current compiler technology is unable to generate dense, high-performance code for DSPs, due to the fact that it does not provide adequate support for the specialized architectural features of DSPs via machine-dependent code optimizations. Thus, designers often program the embedded software in assembly, a very time-consuming task. In order to increase productivity, compilers must be developed that are capable of generating high-quality code for DSPs. The compilation process must also be made retargetable, so that a variety of DSPs may be efficiently evaluated for potential use in an embedded system. We present a retargetable compilation methodology that enables high-quality code to be generated for a wide range of DSPs. Previous work in retargetable DSP compilation has focused on complete automation, and this desire for automation has limited the number of machine-dependent optimizations that can be supported. In our efforts, we have given code quality higher priority over completed automation. We demonstrate how by using a library of machine-dependent optimization routines accessible via a programming interface, it is possible to support a wide range of machine-dependent optimizations, albeit at some cost to automation. Experimental results demonstrate the effectiveness of our methodology, which has been uses to build good-quality compilers for three fixed-point DSPs.

FACE: Fine-tuned Architecture Codesign Environment for ASIP Development

High-performance, reliable, and robust products with a short development schedule are general design aims. FACE was developed to achieve these goals, including the organization of a design flow, a frequency-driven information analyzer, compiler techniques (code generator and instruction optimization), and a hierarchical object design library. This paper explores the design space of a retargetable compiler and a reconfigurable hardware, which combine both software and hardware reprogrammability. The environment, FACE, we have developed allows us to quickly move the functions between software and hardware in a state of flux. Finally, it generates the application specific integrated processor (ASIP) and a compiler for the new ASIP architecture. The case study is considered which demonstrates the efficiency in ASIP design of FACE.

Reverse interpretation + mutation analysis = automatic retargeting

There are three popular methods for constructing highly retargetable compilers: (1) the compiler emits abstract machine code which is interpreted at run-time, (2) the compiler emits C code which is subsequently compiled to machine code by the native C compiler, or (3) the compiler's code-generator is generated by a back-end generator from a formal machine description produced by the compiler writer.These methods incur high costs at run-time, compile-time, or compiler-construction time, respectively.In this paper we will describe a novel method which promises to significantly reduce the effort required to retarget a compiler to a new architecture, while at the same time producing fast and effective compilers. The basic idea is to use the native C compiler at compiler construction time to discover architectural features of the new architecture. From this information a formal machine description is produced. Given this machine description, a native code-generator can be generated by a back-end generator such as BEG or burg.A prototype Automatic Architecture Discovery Unit has been implemented. The current version is general enough to produce machine descriptions for the integer instruction sets of common RISC and CISC architectures such as the Sun SPARC, Digital Alpha, MIPS, DEC VAX, and Intel x86. The tool is completely automatic and requires minimal input from the user: principally, the user needs to provide the internet address of the target machine and the command-lines by which the C compiler, assembler, and linker are invoked.

Embedded system design

In the past decade the main engine of electronic design automation has been the widespread application of ASICs (Application Specific Integrated Circuits). Present technology supports complete systems on a chip, most often used as so-called embedded systems in an increasing number of applications. Embedded systems pose new design challenges which we believe will be the driving forces of design automation in the years to come. These include the design of electronic systems hardware, embedded software and hardware / software codesign. This paper explores the novel technical challenges in embedded system design and presents experiences and results of the work in this area using the CASTLE system. CASTLE supports the design of complex embedded systems and the design of the required tools. It provides a central design representation, Verilog, VHDL and C/C++ frontends, Hardware generation in VHDL and BLIF, a retargetable compiler backend and several analysis and visualization tools. Two design examples, video compression and a diesel injection control, illustrate the presented concepts.

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures

Integrated circuits in telecommunications and consumer electronics are rapidly evolving towards single chip solutions. New IC architectures are emerging, which combine instruction-set processor cores with customised hardware. This paper describes a high-level synthesis system for integration of real-time signal processing systems on such processor cores. The compiler supports a flexible architectural model. It can handle certain types of incompletely specified architectures, and offers capabilities for retargetable compilation and architectural exploration. Results for a realistic application from the domain of audio processing indicate the feasibility and power of the presented approach.

Simple register spilling in a retargetable compiler

AbstractThis paper describes the management of register spills in a retargetable C compiler. Spills are rare, which means that testing is a bigger problem than performance. The trade‐offs have been arranged so that the common case (no spills) generates respectable code quickly and the uncommon case (spills) is less efficient but as simple as possible. The technique has proven practical and is in production use on VAX, Motorola 68020, SPARC and MIPS machines.

A retargetable compiler for ANSI C

lcc is a new retargetable compiler for ANSI C. Versions for the VAX, Motorola 68020, SPARC, and MIPS are in production use at Princeton University and at AT&T Bell Laboratories. With a few exceptions, little about lcc is unusual --- it integrates several well engineered, existing techniques --- but it is smaller and faster than most other C compilers, and it generates code of comparable quality, lcc's target-independent front end performs a few simple, but effective, optimizations that contribute to good code; examples include simulating register declarations and partitioning switch statement cases into dense tables. It also implements target-independent function tracing and expression-level profiling.

The equational specification of efficient compiler code generation

We describe a retargetable compiler code generation system that has two distinguishing features. First, the system produces code generators from equational specifications. The equational notation directly supports the conceptually attractive view of code generation as term rewriting. Second, the system produces code generators that are very efficient. We discuss experimental evidence that indicates that code generators produced by our system run extremely fast. This experimental evidence includes direct comparisons to Davidson-Fraser code generators. Graham-Glanville code generators, and the Portable C compiler's code generator.