RESURF Effect Research Articles

Design Analysis of 4H-SiC MOSFET for High Power Application

Abstract Silicon Carbide has emerged as a promising candidate due to its superior material properties such as high breakdown voltage, wide bandgap, and high thermal conductivity. A new vertical trench-based high power MOSFET (VTMOS) on 4H-SiC is presented. The VTMOS device features two trenches, each containing a poly-Si gate positioned on opposite sides of the P-base region. This configuration results in two parallel channels within the device. The unique design of the VTMOS leverages the RESURF effect and parallel conduction of the drive current, leading to notable performance improvements. The AC and DC characteristics of the VTMOS are analyzed and compared with PRMOS using 2-D simulations. The results demonstrate the superior performance of the VTMOS compared to the PRMOS. Specifically, the VTMOS exhibits 2.35 times higher drive current, an 88% enhancement in gain, 52% higher breakdown voltage, an 11% reduction in threshold potential, a 43% decrease in on-resistance, and 5.55 times higher FOM compared to the PRMOS.

Implementation of Low Voltage MOSFET and Power LDMOS on InGaAs

In this paper, a new low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) have been proposed with concept of integration based on trench technology on InGaAs material. Junction isolation technique is used for the implementation of a low voltage MOSFET and a high power dual gate MOSFET in same InGaAs epitaxial layer side by side. The HV DG MOSFET consists of dual gate that are placed in drift region under the oxide-filled trenches. The proposed structure minimize on-resistance (Ron) along with increased breakdown voltage (Vbr) due to enhanced RESURF effect, the creation of dual channels, and due to folding technique of drift region in vertical direction. In the HV DG MOSFET, the drain current (ID) increases leading to enhanced transconductance (gm) by simultaneous conduction of channels with improved maximum oscillation frequency (fmax) and cut-off frequency (ft). On the other side, the low voltage MOSFET consists of a gate placed in a centre of the structure within an oxide trench to create two n-channels in the p-base. The two channels are conducting in parallel and give substantial enhancement in peak gm, ID, fmax and ft with more control over the short channel parameters. The design and performance analysis of low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) are carried out on 2-D ATLAS device simulator.

Simulative Researching of a 1200V SiC Trench MOSFET With an Enhanced Vertical RESURF Effect

A SiC trench MOSFET with an enhanced vertical RESURF effect is proposed and analyzed in this article. The device features a deep oxide trench surrounded by a P-type doping layer at the source-side. With the assistant depletion effect of the P-type layer, the concentration of the N-drift region is increased and the specific on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ) is thus reduced. The P-type doping can significantly reduce the intensity of the electric field at the gate oxide corner, and modulate the bulk electric field for the device. The breakdown voltage (BV) is therefore improved. As a result, the proposed SiC MOSFET has a better trade-off of BV and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> . The R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> decreases by 59% and the BV increases by 16% for the proposed device without a CSL layer compared with the conventional trench MOSFET with a CSL layer. Meanwhile, the device exhibits a lower gate-to-drain charge (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) which is reduced by 52% and the switching loss is also reduced by 19%.

Theoretical analytic model for RESURF AlGaN/GaN HEMTs**Project supported by the National Basic Research Program of China (Grant No. 2015CB351906), the National Natural Science Foundation of China (Grant No. 61774114), the Key Program of the National Natural Science Foundation of China (Grant No. 61334002), and the 111 Project, China (Grant No. B12026).

In this paper, we propose a two-dimensional (2D) analytic model for the channel potential and electric field distribution of the RESURF AlGaN/GaN high electron mobility transistors (HEMTs). The model is constructed by two-dimensional Poissonʼs equation with appropriate boundary conditions. In the RESURF AlGaN/GaN HEMTs, we utilize the RESURF effect generated by doped negative charge in the AlGaN layer and introduce new electric field peaks in the device channels, thus, homogenizing the distribution of electric field in channel and improving the breakdown voltage of the device. In order to reveal the influence of doped negative charge on the electric field distribution, we demonstrate in detail the influences of the charge doping density and doping position on the potential and electric field distribution of the RESURF AlGaN/GaN HEMTs with double low density drain (LDD). The validity of the model is verified by comparing the results obtained from the analytical model with the simulation results from the ISE software. This analysis method gives a physical insight into the mechanism of the AlGaN/GaN HEMTs and provides reference to modeling other AlGaN/GaN HEMTs device.

Optimization design on breakdown voltage of AlGaN/GaN high-electron mobility transistor**Project supported by the National Basic Research Program of China (No. 2014CB339900) and the Open Fund of Key Laboratory of Complex Electromagnetic Environment Science and Technology, China Academy of Engineering Physics (No. 2015-0214.XY.K).

Simulations are carried out to explore the possibility of achieving high breakdown voltage of GaN HEMT (high-electron mobility transistor). GaN cap layers with gradual increase in the doping concentration from 2 × 1016 to 5 × 1019 cm−3 of N-type and P-type cap are investigated, respectively. Simulation results show that HEMT with P-doped GaN cap layer shows more potential to achieve higher breakdown voltage than N-doped GaN cap layer under the same doping concentration. This is because the ionized net negative space charges in P-GaN cap layer could modulate the surface electric field which makes more contribution to RESURF effect. Furthermore, a novel GaN/AlGaN/GaN HEMT with P-doped GaN buried layer in GaN buffer between gate and drain electrode is proposed. It shows enhanced performance. The breakdown voltage of the proposed structure is 640 V which is increased by 12% in comparison to UID (un-intentionally doped) GaN/AlGaN/GaN HEMT. We calculated and analyzed the distribution of electrons' density. It is found that the depleted region is wider and electric field maximum value is induced at the left edge of buried layer. So the novel structure with P-doped GaN buried layer embedded in GaN buffer has the better improving characteristics of the power devices.

Improving breakdown, conductive, and thermal performances for SOI high voltage LDMOS using a partial compound buried layer

A novel SOI LDMOS with a partial compound buried layer structure (P-CBL SOI) is proposed in this paper. The buried oxide layer at the source-side is replaced by a compound buried layer (CBL) of “top oxide-middle polysilicon-bottom oxide”, and the buried oxide layer at the drain-side is just as the conventional SOI LDMOS (C-SOI). Firstly, a new peak of electric field is introduced at the interface and the whole lateral electric field in the top silicon layer is modulated, resulting in a higher lateral BV. Secondly, impurity doping meeting the RESURF effect in the top silicon layer is higher because the top oxide is thinner than the conventional buried oxide layer, leading to a lower Ron,sp at the on-state and an enhanced vertical BV at the off-state. Finally, thermal conductivity of polysilicon is higher than that of SiO2, offering a lower self-heating effect. The influences of structure parameters on the devices performances are investigated. Compared with those of C-SOI LDMOS on the same top silicon layer of 4μm, buried dielectric layer of 4μm, and drift region of 40μm, BV of P-CBL SOI LDMOS is enhanced by 33.4%, Ron,sp is reduced by 37.4%, and the maximum temperature at the power of 1mW/μm is depressed by 13.3K, respectively.

A novel low specific on-resistance double-gate LDMOS with multiple buried p-layers in the drift region based on the Silicon-On-Insulator substrate

A novel double-gate SOI LDMOS with multiple buried p-layers in the drift region (MBP SOI LDMOS) is proposed in this paper. MBP SOI LDMOS has two gates, the planar gate and the trench gate. The big feature of MBP LDMOS is the multiple buried p-layers with intervals in the drift region which is an arithmetic progression and decreases successively. Firstly, double gates of the structure form dual current conduction channels, leading to a low specific on-resistance (Ron,sp). Secondly, the multiple buried p-layers form a more significant triple RESURF effect, which not only increases the drift doping concentration but also modulates the electric field of the drift region, resulting in a low Ron,sp and a high breakdown voltage (BV). MBP SOI LDMOS is thus owning a reduced Ron,sp and an improved BV. The effects of structure parameters on the device performances are investigated. Compared with the conventional SOI LDMOS, the Ron,sp of MBP SOI LDMOS is reduced by 52.5% with BV increasing by 36.4% at the same 16-μm-drift region.

A lateral DMOS with partial buried-oxide layer to achieve better RESURF effect

A lateral DMOS with partial buried-oxide layer to achieve better RESURF effect

Mechanism and optimal design of a high-k dielectric conduction enhancement SOI LDMOS

A high-k dielectric conduction enhancement SOI LDMOS is proposed and investigated by simulation. The high-k dielectric pillars are located at sidewalls of the drift region. The high-k dielectric assists the self-adapted depletion in the drift region, reshapes the electric field distribution, and makes the three-dimensional RESURF effect realized in a high-voltage blocking state. Dependences of the breakdown voltage (VB) and the specific on-resistance (Ron,sp) on device parameters are exhibited using three-dimensional simulation. Simulation results show that the proposed structure increases VB by 16%–18% and decreases Ron.sp by 13%–20%, compared with the conventional super-junction SOI LDMOS. Furthermore, the charge-imbalance caused by the substrate-assisted depletion effect is alleviated.

High voltage SOI SJ-LDMOS with dynamic back-gate voltage

The impact of dynamic back-gate voltage on SOI SJ-LDMOS (super junction LDMOS on silicon-on-insulator) is investigated. The variable back-gate voltage induces the holes besides electrons below the buried oxide layer, which optimises the substrate-assisted depletion effect and promotes the charge balance between N and P pillars of SJ. As a result, the uniform electric field is achieved, resulting in improving breakdown voltage. In addition, SJ-LDMOS with dynamic back-gate voltage keeps the low on-resistance, in contrast to the conventional LDMOS with positive back-gate voltage which increases on-resistance because of weakening RESURF effect.

Analytical modelling for the RESURF effect in JI and SOI power devices

The authors present a review and assessment of state-of-the-art analytical models which describe the breakdown behaviour of JI and SOI RESURF power devices. The results are compared with numerical values, and a short evaluation of strengths and weaknesses specific to each model is given. A new modelling concept for the breakdown regime in RESURF power structures is introduced, and the results are assessed against numerical values. The same technique can be used to derive the breakdown voltage of RESURF devices fabricated in JI and SOI technologies, and is potentially useful for non-standard technologies, such as linearly graded SOI, partial SOI and 3-D RESURF. The model provides accurate description for punch-through, non-punch-through and volume breakdown.

High voltage (450 V) 6H-SiC lateral MESFET structure

A high voltage 6H-SiC lateral MESFET has been fabricated using a three mask process. Selective ion implantation was used to create the conducting layer (N-region) demonstrating the RESURF effect in SiC for first time, as well as easy isolation and edge termination. This MESFET was able to withstand a forward blocking voltage of 450 V at a gate voltage of -20 V. The specific on-resistance and transconductance for a device with a drain gate separation of 15 /spl mu/m was found to be 83 m/spl Omega/ cm/sup 2/ and 2 mS/mm, respectively.