Abstract
The impact of dynamic back-gate voltage on SOI SJ-LDMOS (super junction LDMOS on silicon-on-insulator) is investigated. The variable back-gate voltage induces the holes besides electrons below the buried oxide layer, which optimises the substrate-assisted depletion effect and promotes the charge balance between N and P pillars of SJ. As a result, the uniform electric field is achieved, resulting in improving breakdown voltage. In addition, SJ-LDMOS with dynamic back-gate voltage keeps the low on-resistance, in contrast to the conventional LDMOS with positive back-gate voltage which increases on-resistance because of weakening RESURF effect.
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